<p>Mario Scheithauer <strong>uploaded patch set #2</strong> to this change.</p><p><a href="https://review.coreboot.org/29549">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl3: Disable PCI clock outputs on XIO bridges<br><br>On this mainboard there are legacy PCI device, which are connected to<br>different PCIe root ports via PCIe-2-PCI bridges. This patch disables<br>the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.<br><br>Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c<br>1 file changed, 13 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29549/2</pre><p>To view, visit <a href="https://review.coreboot.org/29549">change 29549</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29549"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newpatchset </div>
<div style="display:none"> Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 </div>
<div style="display:none"> Gerrit-Change-Number: 29549 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>
<div style="display:none"> Gerrit-Reviewer: Werner Zeh <werner.zeh@siemens.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>