<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29551">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/cannonlake: Remove SmbusEnable from devicetree<br><br>Remove the SmbusEnable parameter from all Cannon Lake mainboards.<br>Instead this will be determined by the enable state of the SMBUS<br>PCI device.<br><br>Change-Id: I7ece6768da4c517747af12a07012583575816ae1<br>Signed-off-by: Duncan Laurie <dlaurie@google.com><br>---<br>M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb<br>M src/mainboard/google/zoombini/variants/meowth/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb<br>M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb<br>M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb<br>7 files changed, 0 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29551/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>index c7ef264..36c6595 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>@@ -20,7 +20,6 @@</span><br><span> </span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">- register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span> </span><br><span> # Intel Common SoC Config</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>index c3a546e..b014353 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>@@ -29,7 +29,6 @@</span><br><span> </span><br><span> # FSP configuration</span><br><span> register "SaGv" = "SaGv_Enabled"</span><br><span style="color: hsl(0, 100%, 40%);">- register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span> </span><br><span> # Intel Common SoC Config</span><br><span>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>index da439d5..bb963c9 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>@@ -6,7 +6,6 @@</span><br><span> </span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">- register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span> </span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>index a1c8586..55afde2 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>@@ -6,7 +6,6 @@</span><br><span> </span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">- register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span> </span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>index 4a2fad9..35aa624 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>@@ -7,7 +7,6 @@</span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span> register "RMT" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span> </span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)"</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb</span><br><span>index 2b47f00..bbfc9e7 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb</span><br><span>@@ -7,7 +7,6 @@</span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span> register "RMT" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span> </span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)"</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb</span><br><span>index da439d5..bb963c9 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb</span><br><span>@@ -6,7 +6,6 @@</span><br><span> </span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">- register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span> </span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29551">change 29551</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7ece6768da4c517747af12a07012583575816ae1 </div>
<div style="display:none"> Gerrit-Change-Number: 29551 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>