<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29523">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[DoNotMerge]soc/intel/cannonlake: Enable Debugging<br><br>Change-Id: I5986007f3f36bc7fdc8e427fa311f98890069cd3<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/mainboard/google/sarien/variants/arcada/devicetree.cb<br>M src/soc/intel/cannonlake/romstage/fsp_params.c<br>2 files changed, 4 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29523/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>index e3b9680..4eaec99 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>@@ -8,6 +8,9 @@</span><br><span>    register "gpe0_dw1" = "PMC_GPP_C"</span><br><span>        register "gpe0_dw2" = "PMC_GPP_D"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+    #Debug</span><br><span style="color: hsl(120, 100%, 40%);">+    register "DebugConsent" = DebugConsent_DCI_DBC</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>        # EC host command ranges</span><br><span>     register "gen1_dec" = "0x00040931" # 0x930-0x937</span><br><span>         register "gen2_dec" = "0x00040941" # 0x940-0x947</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c</span><br><span>index 8506214..9c57b12 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/fsp_params.c</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c</span><br><span>@@ -61,6 +61,7 @@</span><br><span>                m_cfg->PchIshEnable = 0;</span><br><span>  else</span><br><span>                 m_cfg->PchIshEnable = dev->enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+     m_cfg->PchTraceHubMode = 2;</span><br><span> }</span><br><span> </span><br><span> void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29523">change 29523</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29523"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5986007f3f36bc7fdc8e427fa311f98890069cd3 </div>
<div style="display:none"> Gerrit-Change-Number: 29523 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>