<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29539">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/sarien: Set runtime IRQs to reset on PLTRST<br><br>GPIOs that use GPI_APIC setting with DEEP can cause an IRQ storm after<br>S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic<br>reset over PLTRST to prevent IRQ strom after S3 resume.<br><br>For sarien/arcada these are all runtime IRQs only, not wake capable.<br><br>Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f<br>Signed-off-by: Duncan Laurie <dlaurie@google.com><br>---<br>M src/mainboard/google/sarien/variants/arcada/gpio.c<br>M src/mainboard/google/sarien/variants/sarien/gpio.c<br>2 files changed, 12 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/29539/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c</span><br><span>index eb4ee76..91ff089 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/arcada/gpio.c</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/gpio.c</span><br><span>@@ -46,7 +46,7 @@</span><br><span> /* CORE_VID0 */</span><br><span> /* CORE_VID1 */</span><br><span> /* VRALERT# */ PAD_NC(GPP_B2, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */</span><br><span> /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */</span><br><span> /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),</span><br><span>@@ -93,10 +93,10 @@</span><br><span> /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */</span><br><span> /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */</span><br><span> /* UART2_RTS# */ PAD_NC(GPP_C22, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* TS_INT# */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */</span><br><span> /* SPI1_CLK */ PAD_NC(GPP_D1, NONE),</span><br><span> /* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */</span><br><span>@@ -117,7 +117,7 @@</span><br><span> /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */</span><br><span> /* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE),</span><br><span> /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */</span><br><span> /* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE),</span><br><span> /* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE),</span><br><span>@@ -232,7 +232,7 @@</span><br><span> /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */</span><br><span> /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */</span><br><span> /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */</span><br><span> /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */</span><br><span> /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>index 690af1f..31b42ef 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>@@ -46,7 +46,7 @@</span><br><span> /* CORE_VID0 */</span><br><span> /* CORE_VID1 */</span><br><span> /* VRALERT# */ PAD_NC(GPP_B2, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */</span><br><span> /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */</span><br><span> /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),</span><br><span>@@ -63,7 +63,7 @@</span><br><span> /* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),</span><br><span> /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),</span><br><span> /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* HDD_FALL_INT */</span><br><span> /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */</span><br><span> /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */</span><br><span>@@ -94,10 +94,10 @@</span><br><span> /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */</span><br><span> /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */</span><br><span> /* UART2_RTS# */ PAD_NC(GPP_C22, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* TS_INT# */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */</span><br><span> /* SPI1_CLK */ PAD_NC(GPP_D1, NONE),</span><br><span> /* SPI1_MISO */ PAD_NC(GPP_D2, NONE),</span><br><span>@@ -116,7 +116,7 @@</span><br><span> /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */</span><br><span> /* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE),</span><br><span> /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */</span><br><span> /* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE),</span><br><span> /* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE),</span><br><span>@@ -143,7 +143,7 @@</span><br><span> /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */</span><br><span> /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */</span><br><span> /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* FFS_INT2 */</span><br><span> /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span> /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),</span><br><span>@@ -232,7 +232,7 @@</span><br><span> /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */</span><br><span> /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */</span><br><span> /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */</span><br><span> /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */</span><br><span> /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29539">change 29539</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f </div>
<div style="display:none"> Gerrit-Change-Number: 29539 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>