<p>Aamir Bohra would like Subrata Banik to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/29495">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/icelake: Update GPIOs for Icelake SOC<br><br>This implementation updates the GPIO pins, communities and<br>groups mapping.<br><br>Change details:<br><br>1. Update 5 GPIO community includes 11 GPIO groups<br> GPIO COM 0<br> GPP_G, GPP_B, GPP_A<br> GPIO COM 1<br> GPP_H, GPP_D, GPP_F<br> GPIO COM 2<br> GPD<br> GPIO COM 4<br> GPP_C, GPP_E<br> GPIO COM 5<br> GPP_R, GPP_S<br><br>2. Update GPIO IRQ routing<br><br>Change-Id: I223abacc18f78631a42f340952f13d45fa9a4703<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>---<br>M src/soc/intel/icelake/acpi/gpio.asl<br>M src/soc/intel/icelake/gpio.c<br>M src/soc/intel/icelake/include/soc/gpio.h<br>M src/soc/intel/icelake/include/soc/gpio_defs.h<br>M src/soc/intel/icelake/include/soc/gpio_soc_defs.h<br>M src/soc/intel/icelake/include/soc/pmc.h<br>6 files changed, 533 insertions(+), 581 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/29495/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/icelake/acpi/gpio.asl b/src/soc/intel/icelake/acpi/gpio.asl</span><br><span>index 5784fb1..c8d4fef 100644</span><br><span>--- a/src/soc/intel/icelake/acpi/gpio.asl</span><br><span>+++ b/src/soc/intel/icelake/acpi/gpio.asl</span><br><span>@@ -19,7 +19,7 @@</span><br><span> </span><br><span> Device (GPIO)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_HID, "INT34BB")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, "INT3455")</span><br><span> Name (_UID, 0)</span><br><span> Name (_DDN, "GPIO Controller")</span><br><span> </span><br><span>@@ -28,8 +28,8 @@</span><br><span> Memory32Fixed (ReadWrite, 0, 0, COM0)</span><br><span> Memory32Fixed (ReadWrite, 0, 0, COM1)</span><br><span> Memory32Fixed (ReadWrite, 0, 0, COM2)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed (ReadWrite, 0, 0, COM3)</span><br><span> Memory32Fixed (ReadWrite, 0, 0, COM4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadWrite, 0, 0, COM5)</span><br><span> Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)</span><br><span> { GPIO_IRQ14 }</span><br><span> })</span><br><span>@@ -54,19 +54,18 @@</span><br><span> Store (^^PCRB (PID_GPIOCOM2), BAS2)</span><br><span> Store (GPIO_BASE_SIZE, LEN2)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO Community 3 */</span><br><span style="color: hsl(0, 100%, 40%);">- CreateDWordField (^RBUF, ^COM3._BAS, BAS3)</span><br><span style="color: hsl(0, 100%, 40%);">- CreateDWordField (^RBUF, ^COM3._LEN, LEN3)</span><br><span style="color: hsl(0, 100%, 40%);">- Store (^^PCRB (PID_GPIOCOM3), BAS3)</span><br><span style="color: hsl(0, 100%, 40%);">- Store (GPIO_BASE_SIZE, LEN3)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* GPIO Community 4 */</span><br><span> CreateDWordField (^RBUF, ^COM4._BAS, BAS4)</span><br><span> CreateDWordField (^RBUF, ^COM4._LEN, LEN4)</span><br><span> Store (^^PCRB (PID_GPIOCOM4), BAS4)</span><br><span> Store (GPIO_BASE_SIZE, LEN4)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDWordField (^RBUF, ^COM5._BAS, BAS5)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDWordField (^RBUF, ^COM5._LEN, LEN5)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (^^PCRB (PID_GPIOCOM5), BAS5)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (GPIO_BASE_SIZE, LEN5)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> Return (RBUF)</span><br><span> }</span><br><span> </span><br><span>@@ -83,13 +82,13 @@</span><br><span> Method (GADD, 1, NotSerialized)</span><br><span> {</span><br><span> /* GPIO Community 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPIO_RSVD_11)))</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_G0), LLessEqual (Arg0, GPP_A23)))</span><br><span> {</span><br><span> Store (PID_GPIOCOM0, Local0)</span><br><span> Subtract (Arg0, GPP_A0, Local1)</span><br><span> }</span><br><span> /* GPIO Community 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPIO_RSVD_52)))</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_H0), LLessEqual (Arg0, GPP_F19)))</span><br><span> {</span><br><span> Store (PID_GPIOCOM1, Local0)</span><br><span> Subtract (Arg0, GPP_D0, Local1)</span><br><span>@@ -97,21 +96,21 @@</span><br><span> /* GPIO Community 2 */</span><br><span> If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, GPD11)))</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- Store (PID_GPIOCOM1, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PID_GPIOCOM2, Local0)</span><br><span> Subtract (Arg0, GPD0, Local1)</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO Community 3 */</span><br><span style="color: hsl(0, 100%, 40%);">- If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_78)))</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- Store (PID_GPIOCOM1, Local0)</span><br><span style="color: hsl(0, 100%, 40%);">- Subtract (Arg0, HDA_BCLK, Local1)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO Community 04*/</span><br><span style="color: hsl(0, 100%, 40%);">- If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_67)))</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_E23)))</span><br><span> {</span><br><span> Store (PID_GPIOCOM4, Local0)</span><br><span> Subtract (Arg0, GPP_C0, Local1)</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 05*/</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_R0), LLessEqual (Arg0, GPP_S7)))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PID_GPIOCOM5, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Arg0, GPP_R0, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> Store (PCRB (Local0), Local2)</span><br><span> Add (Local2, PAD_CFG_BASE, Local2)</span><br><span> Return (Add (Local2, Multiply (Local1, 16)))</span><br><span>diff --git a/src/soc/intel/icelake/gpio.c b/src/soc/intel/icelake/gpio.c</span><br><span>index e965494..b244437 100644</span><br><span>--- a/src/soc/intel/icelake/gpio.c</span><br><span>+++ b/src/soc/intel/icelake/gpio.c</span><br><span>@@ -33,63 +33,63 @@</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group icl_community0_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPP_A0, GPIO_RSVD_0), /* GPP_A */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPP_B0, GPIO_RSVD_2), /* GPP_B */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPP_G0, GPP_G7), /* GPP_G */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPIO_RSVD_3, GPIO_RSVD_11), /* SPI */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_G0, GPP_G0, GPP_G7), /* GPP_G */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_G0, GPP_B0, GPP_B23), /* GPP_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_G0, GPIO_RSVD_0, GPIO_RSVD_1),</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_G0, GPP_A0, GPP_A23), /* GPP_A */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group icl_community1_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_D0, GPP_D0, GPIO_RSVD_12), /* GPP_D */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_D0, GPP_F0, GPP_F23), /* GPP_F */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_D0, GPP_H0, GPP_H23), /* GPP_H */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_D0, GPIO_RSVD_12, GPIO_RSVD_52), /* VGPIO */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_H0, GPP_H0, GPP_H23), /* GPP_H */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_H0, GPP_D0, GPIO_RSVD_2), /* GPP_D */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_H0, GPP_F0, GPP_F19), /* GPP_F */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group icl_community2_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const struct pad_group icl_community3_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD), /* AZA */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(HDA_BCLK, GPIO_RSVD_68, GPIO_RSVD_78), /* CPU */</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span> </span><br><span> static const struct pad_group icl_community4_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP_E */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPIO_RSVD_53, GPIO_RSVD_61), /* JTAG */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPIO_RSVD_62, GPIO_RSVD_67), /* HVMOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP_E */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_8),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_group icl_community5_groups[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_R0, GPP_R0, GPP_R7), /* GPP_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPP_S0, GPP_S7), /* GPP_S */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_community icl_communities[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- { /* GPP A, B, G, SPI */</span><br><span style="color: hsl(120, 100%, 40%);">+ { /* GPP G, B, A */</span><br><span> .port = PID_GPIOCOM0,</span><br><span style="color: hsl(0, 100%, 40%);">- .first_pad = GPP_A0,</span><br><span style="color: hsl(0, 100%, 40%);">- .last_pad = GPIO_RSVD_11,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPP_G0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPP_A23,</span><br><span> .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,</span><br><span> .pad_cfg_base = PAD_CFG_BASE,</span><br><span> .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span> .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span> .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span> .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(0, 100%, 40%);">- .name = "GPP_ABG",</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_GBA",</span><br><span> .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span> .reset_map = rst_map_com0,</span><br><span> .num_reset_vals = ARRAY_SIZE(rst_map_com0),</span><br><span> .groups = icl_community0_groups,</span><br><span> .num_groups = ARRAY_SIZE(icl_community0_groups),</span><br><span style="color: hsl(0, 100%, 40%);">- }, { /* GPP D, F, H, VGPIO */</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* GPP H, D, F */</span><br><span> .port = PID_GPIOCOM1,</span><br><span style="color: hsl(0, 100%, 40%);">- .first_pad = GPP_D0,</span><br><span style="color: hsl(0, 100%, 40%);">- .last_pad = GPIO_RSVD_52,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPP_H0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPP_F19,</span><br><span> .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,</span><br><span> .pad_cfg_base = PAD_CFG_BASE,</span><br><span> .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span> .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span> .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span> .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(0, 100%, 40%);">- .name = "GPP_DFH",</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_HDF",</span><br><span> .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span> .reset_map = rst_map,</span><br><span> .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span>@@ -111,38 +111,38 @@</span><br><span> .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span> .groups = icl_community2_groups,</span><br><span> .num_groups = ARRAY_SIZE(icl_community2_groups),</span><br><span style="color: hsl(0, 100%, 40%);">- }, { /* AZA, CPU */</span><br><span style="color: hsl(0, 100%, 40%);">- .port = PID_GPIOCOM3,</span><br><span style="color: hsl(0, 100%, 40%);">- .first_pad = HDA_BCLK,</span><br><span style="color: hsl(0, 100%, 40%);">- .last_pad = GPIO_RSVD_78,</span><br><span style="color: hsl(0, 100%, 40%);">- .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,</span><br><span style="color: hsl(0, 100%, 40%);">- .pad_cfg_base = PAD_CFG_BASE,</span><br><span style="color: hsl(0, 100%, 40%);">- .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span style="color: hsl(0, 100%, 40%);">- .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(0, 100%, 40%);">- .name = "GP_AC",</span><br><span style="color: hsl(0, 100%, 40%);">- .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span style="color: hsl(0, 100%, 40%);">- .reset_map = rst_map,</span><br><span style="color: hsl(0, 100%, 40%);">- .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span style="color: hsl(0, 100%, 40%);">- .groups = icl_community3_groups,</span><br><span style="color: hsl(0, 100%, 40%);">- .num_groups = ARRAY_SIZE(icl_community3_groups),</span><br><span style="color: hsl(0, 100%, 40%);">- }, { /* GPP C, E, JTAG, HVMOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* GPP C, E */</span><br><span> .port = PID_GPIOCOM4,</span><br><span> .first_pad = GPP_C0,</span><br><span style="color: hsl(0, 100%, 40%);">- .last_pad = GPIO_RSVD_67,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPP_E23,</span><br><span> .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,</span><br><span> .pad_cfg_base = PAD_CFG_BASE,</span><br><span> .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span> .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span> .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span> .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(0, 100%, 40%);">- .name = "GPP_CEJ",</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_CE",</span><br><span> .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span> .reset_map = rst_map,</span><br><span> .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span> .groups = icl_community4_groups,</span><br><span> .num_groups = ARRAY_SIZE(icl_community4_groups),</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* GPP R, S */</span><br><span style="color: hsl(120, 100%, 40%);">+ .port = PID_GPIOCOM5,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPP_R0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPP_S7,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pad_cfg_base = PAD_CFG_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_RS",</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset_map = rst_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span style="color: hsl(120, 100%, 40%);">+ .groups = icl_community5_groups,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_groups = ARRAY_SIZE(icl_community5_groups),</span><br><span> }</span><br><span> };</span><br><span> </span><br><span>@@ -155,15 +155,18 @@</span><br><span> const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)</span><br><span> {</span><br><span> static const struct pmc_to_gpio_route routes[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_A, GPP_A },</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_B, GPP_B },</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_C, GPP_C },</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_D, GPP_D },</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_E, GPP_E },</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_F, GPP_F },</span><br><span> { PMC_GPP_G, GPP_G },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_B, GPP_B },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_A, GPP_A },</span><br><span> { PMC_GPP_H, GPP_H },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_D, GPP_D },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_F, GPP_F },</span><br><span> { PMC_GPD, GPD },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_C, GPP_C },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_E, GPP_E },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_R, GPP_R },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_S, GPP_S }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> };</span><br><span> *num = ARRAY_SIZE(routes);</span><br><span> return routes;</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/gpio.h b/src/soc/intel/icelake/include/soc/gpio.h</span><br><span>index 2e55e74..333dba1 100644</span><br><span>--- a/src/soc/intel/icelake/include/soc/gpio.h</span><br><span>+++ b/src/soc/intel/icelake/include/soc/gpio.h</span><br><span>@@ -19,6 +19,6 @@</span><br><span> #include <soc/gpio_defs.h></span><br><span> #include <intelblocks/gpio.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define CROS_GPIO_DEVICE_NAME "INT34BB:00"</span><br><span style="color: hsl(120, 100%, 40%);">+#define CROS_GPIO_DEVICE_NAME "INT3455:00"</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h</span><br><span>index 44425f4..86d5fb2 100644</span><br><span>--- a/src/soc/intel/icelake/include/soc/gpio_defs.h</span><br><span>+++ b/src/soc/intel/icelake/include/soc/gpio_defs.h</span><br><span>@@ -30,216 +30,235 @@</span><br><span> #define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)</span><br><span> #define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)</span><br><span> #define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)</span><br><span style="color: hsl(0, 100%, 40%);">-#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)</span><br><span> #define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)</span><br><span> </span><br><span> #define NUM_GPI_STATUS_REGS \</span><br><span> ((NUM_GPIO_COM0_GPI_REGS) +\</span><br><span> (NUM_GPIO_COM1_GPI_REGS) +\</span><br><span> (NUM_GPIO_COM2_GPI_REGS) +\</span><br><span style="color: hsl(0, 100%, 40%);">- (NUM_GPIO_COM3_GPI_REGS) +\</span><br><span style="color: hsl(0, 100%, 40%);">- (NUM_GPIO_COM4_GPI_REGS))</span><br><span style="color: hsl(120, 100%, 40%);">+ (NUM_GPIO_COM4_GPI_REGS) +\</span><br><span style="color: hsl(120, 100%, 40%);">+ (NUM_GPIO_COM5_GPI_REGS))</span><br><span> /*</span><br><span> * IOxAPIC IRQs for the GPIOs</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Group A */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A0_IRQ 0x18</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A1_IRQ 0x19</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A2_IRQ 0x1a</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A3_IRQ 0x1b</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A4_IRQ 0x1c</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A5_IRQ 0x1d</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A6_IRQ 0x1e</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A7_IRQ 0x1f</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A8_IRQ 0x20</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A9_IRQ 0x21</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A10_IRQ 0x22</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A11_IRQ 0x23</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A12_IRQ 0x24</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A13_IRQ 0x25</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A14_IRQ 0x26</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A15_IRQ 0x27</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A16_IRQ 0x28</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A17_IRQ 0x29</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A18_IRQ 0x2a</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A19_IRQ 0x2b</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A20_IRQ 0x2c</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A21_IRQ 0x2d</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A22_IRQ 0x2e</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A23_IRQ 0x2f</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group B */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B0_IRQ 0x30</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B1_IRQ 0x31</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B2_IRQ 0x32</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B3_IRQ 0x33</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B4_IRQ 0x34</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B5_IRQ 0x35</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B6_IRQ 0x36</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B7_IRQ 0x37</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B8_IRQ 0x38</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B9_IRQ 0x39</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B10_IRQ 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B11_IRQ 0x3b</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B12_IRQ 0x3c</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B13_IRQ 0x3d</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B14_IRQ 0x3e</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B15_IRQ 0x3f</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B16_IRQ 0x40</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B17_IRQ 0x41</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B18_IRQ 0x42</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B19_IRQ 0x43</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B20_IRQ 0x44</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B21_IRQ 0x45</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B22_IRQ 0x46</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B23_IRQ 0x47</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group C */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C0_IRQ 0x48</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C1_IRQ 0x49</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C2_IRQ 0x4a</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C3_IRQ 0x4b</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C4_IRQ 0x4c</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C5_IRQ 0x4d</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C6_IRQ 0x4e</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C7_IRQ 0x4f</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C8_IRQ 0x50</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C9_IRQ 0x51</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C10_IRQ 0x52</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C11_IRQ 0x53</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C12_IRQ 0x54</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C13_IRQ 0x55</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C14_IRQ 0x56</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C15_IRQ 0x57</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C16_IRQ 0x58</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C17_IRQ 0x59</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C18_IRQ 0x5a</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C19_IRQ 0x5b</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C20_IRQ 0x5c</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C21_IRQ 0x5d</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C22_IRQ 0x5e</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C23_IRQ 0x5f</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group D */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D0_IRQ 0x60</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D1_IRQ 0x61</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D2_IRQ 0x62</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D3_IRQ 0x63</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D4_IRQ 0x64</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D5_IRQ 0x65</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D6_IRQ 0x66</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D7_IRQ 0x67</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D8_IRQ 0x68</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D9_IRQ 0x69</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D10_IRQ 0x6a</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D11_IRQ 0x6b</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D12_IRQ 0x6c</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D13_IRQ 0x6d</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D14_IRQ 0x6e</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D15_IRQ 0x6f</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D16_IRQ 0x70</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D17_IRQ 0x71</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D18_IRQ 0x72</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D19_IRQ 0x73</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D20_IRQ 0x74</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D21_IRQ 0x75</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D22_IRQ 0x76</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D23_IRQ 0x77</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group E */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E0_IRQ 0x18</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E1_IRQ 0x19</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E2_IRQ 0x1a</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E3_IRQ 0x1b</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E4_IRQ 0x1c</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E5_IRQ 0x1d</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E6_IRQ 0x1e</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E7_IRQ 0x1f</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E8_IRQ 0x20</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E9_IRQ 0x21</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E10_IRQ 0x22</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E11_IRQ 0x23</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E12_IRQ 0x24</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E13_IRQ 0x25</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E14_IRQ 0x26</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E15_IRQ 0x27</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E16_IRQ 0x28</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E17_IRQ 0x29</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E18_IRQ 0x2a</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E19_IRQ 0x2b</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E20_IRQ 0x2c</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E21_IRQ 0x2d</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E22_IRQ 0x2e</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E23_IRQ 0x2f</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group F */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F0_IRQ 0x30</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F1_IRQ 0x31</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F2_IRQ 0x32</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F3_IRQ 0x33</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F4_IRQ 0x34</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F5_IRQ 0x35</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F6_IRQ 0x36</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F7_IRQ 0x37</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F8_IRQ 0x38</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F9_IRQ 0x39</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F10_IRQ 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F11_IRQ 0x3b</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F12_IRQ 0x3c</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F13_IRQ 0x3d</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F14_IRQ 0x3e</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F15_IRQ 0x3f</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F16_IRQ 0x40</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F17_IRQ 0x41</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F18_IRQ 0x42</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F19_IRQ 0x43</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F20_IRQ 0x44</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F21_IRQ 0x45</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F22_IRQ 0x46</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F23_IRQ 0x47</span><br><span> /* Group G */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G0_IRQ 0x6c</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G1_IRQ 0x6d</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G2_IRQ 0x6e</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G3_IRQ 0x6f</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G4_IRQ 0x70</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G5_IRQ 0x71</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G6_IRQ 0x72</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G7_IRQ 0x73</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group GPD */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD0_IRQ 0x60</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD1_IRQ 0x61</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD2_IRQ 0x62</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD3_IRQ 0x63</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD4_IRQ 0x64</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD5_IRQ 0x65</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD6_IRQ 0x66</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD7_IRQ 0x67</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD8_IRQ 0x68</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD9_IRQ 0x69</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD10_IRQ 0x6a</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD11_IRQ 0x6b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G0_IRQ 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G1_IRQ 0x19</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G2_IRQ 0x1a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G3_IRQ 0x1b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G4_IRQ 0x1c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G5_IRQ 0x1d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G6_IRQ 0x1e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G7_IRQ 0x1f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group B */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B0_IRQ 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B1_IRQ 0x21</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B2_IRQ 0x22</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B3_IRQ 0x23</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B4_IRQ 0x24</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B5_IRQ 0x25</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B6_IRQ 0x26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B7_IRQ 0x27</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B8_IRQ 0x28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B9_IRQ 0x29</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B10_IRQ 0x2a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B11_IRQ 0x2b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B12_IRQ 0x2c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B13_IRQ 0x2d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B14_IRQ 0x2e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B15_IRQ 0x2f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B16_IRQ 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B17_IRQ 0x31</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B18_IRQ 0x32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B19_IRQ 0x33</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B20_IRQ 0x34</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B21_IRQ 0x35</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B22_IRQ 0x36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B23_IRQ 0x37</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group A */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A0_IRQ 0x38</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A1_IRQ 0x39</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A2_IRQ 0x3a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A3_IRQ 0x3b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A4_IRQ 0x3c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A5_IRQ 0x3d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A6_IRQ 0x3e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A7_IRQ 0x3f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A8_IRQ 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A9_IRQ 0x41</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A10_IRQ 0x42</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A11_IRQ 0x43</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A12_IRQ 0x44</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A13_IRQ 0x45</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A14_IRQ 0x46</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A15_IRQ 0x47</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A16_IRQ 0x48</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A17_IRQ 0x49</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A18_IRQ 0x4a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A19_IRQ 0x4b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A20_IRQ 0x4c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A21_IRQ 0x4d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A22_IRQ 0x4e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A23_IRQ 0x4f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Group H */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H0_IRQ 0x48</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H1_IRQ 0x49</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H2_IRQ 0x4a</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H3_IRQ 0x4b</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H4_IRQ 0x4c</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H5_IRQ 0x4d</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H6_IRQ 0x4e</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H7_IRQ 0x4f</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H8_IRQ 0x50</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H9_IRQ 0x51</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H10_IRQ 0x52</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H11_IRQ 0x53</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H12_IRQ 0x54</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H13_IRQ 0x55</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H14_IRQ 0x56</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H15_IRQ 0x57</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H16_IRQ 0x58</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H17_IRQ 0x59</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H18_IRQ 0x5a</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H19_IRQ 0x5b</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H20_IRQ 0x5c</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H21_IRQ 0x5d</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H22_IRQ 0x5e</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H23_IRQ 0x5f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H0_IRQ 0x70</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H1_IRQ 0x71</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H2_IRQ 0x72</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H3_IRQ 0x73</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H4_IRQ 0x74</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H5_IRQ 0x75</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H6_IRQ 0x76</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H7_IRQ 0x77</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H8_IRQ 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H9_IRQ 0x19</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H10_IRQ 0x1a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H11_IRQ 0x1b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H12_IRQ 0x1c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H13_IRQ 0x1d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H14_IRQ 0x1e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H15_IRQ 0x1f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H16_IRQ 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H17_IRQ 0x21</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H18_IRQ 0x22</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H19_IRQ 0x23</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H20_IRQ 0x24</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H21_IRQ 0x25</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H22_IRQ 0x26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H23_IRQ 0x27</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group D */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D0_IRQ 0x28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D1_IRQ 0x29</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D2_IRQ 0x2a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D3_IRQ 0x2b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D4_IRQ 0x2c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D5_IRQ 0x2d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D6_IRQ 0x2e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D7_IRQ 0x2f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D8_IRQ 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D9_IRQ 0x31</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D10_IRQ 0x32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D11_IRQ 0x33</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D12_IRQ 0x34</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D13_IRQ 0x35</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D14_IRQ 0x36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D15_IRQ 0x37</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D16_IRQ 0x38</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D17_IRQ 0x39</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D18_IRQ 0x3a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D19_IRQ 0x3b</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group F */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F0_IRQ 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F1_IRQ 0x41</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F2_IRQ 0x42</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F3_IRQ 0x43</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F4_IRQ 0x44</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F5_IRQ 0x45</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F6_IRQ 0x46</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F7_IRQ 0x47</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F8_IRQ 0x48</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F9_IRQ 0x49</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F10_IRQ 0x4a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F11_IRQ 0x4b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F12_IRQ 0x4c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F13_IRQ 0x4d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F14_IRQ 0x4e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F15_IRQ 0x4f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F16_IRQ 0x50</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F17_IRQ 0x51</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F18_IRQ 0x52</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F19_IRQ 0x53</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group GPD */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD0_IRQ 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD1_IRQ 0x65</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD2_IRQ 0x66</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD3_IRQ 0x67</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD4_IRQ 0x68</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD5_IRQ 0x69</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD6_IRQ 0x6a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD7_IRQ 0x6b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD8_IRQ 0x6c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD9_IRQ 0x6d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD10_IRQ 0x6e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD11_IRQ 0x6f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group C */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C0_IRQ 0x5a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C1_IRQ 0x5b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C2_IRQ 0x5c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C3_IRQ 0x5d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C4_IRQ 0x5e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C5_IRQ 0x5f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C6_IRQ 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C7_IRQ 0x61</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C8_IRQ 0x62</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C9_IRQ 0x63</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C10_IRQ 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C11_IRQ 0x65</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C12_IRQ 0x66</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C13_IRQ 0x67</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C14_IRQ 0x68</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C15_IRQ 0x69</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C16_IRQ 0x6a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C17_IRQ 0x6b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C18_IRQ 0x6c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C19_IRQ 0x6d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C20_IRQ 0x6e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C21_IRQ 0x6f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C22_IRQ 0x70</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C23_IRQ 0x71</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group E */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E0_IRQ 0x72</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E1_IRQ 0x73</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E2_IRQ 0x74</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E3_IRQ 0x75</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E4_IRQ 0x76</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E5_IRQ 0x77</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E6_IRQ 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E7_IRQ 0x19</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E8_IRQ 0x1a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E9_IRQ 0x1b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E10_IRQ 0x1c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E11_IRQ 0x1d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E12_IRQ 0x1e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E13_IRQ 0x1f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E14_IRQ 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E15_IRQ 0x21</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E16_IRQ 0x22</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E17_IRQ 0x23</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E18_IRQ 0x24</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E19_IRQ 0x25</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E20_IRQ 0x26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E21_IRQ 0x27</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E22_IRQ 0x28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E23_IRQ 0x29</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group R*/</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R0_IRQ 0x50</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R1_IRQ 0x51</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R2_IRQ 0x52</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R3_IRQ 0x53</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R4_IRQ 0x54</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R5_IRQ 0x55</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R6_IRQ 0x56</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R7_IRQ 0x57</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group S */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S0_IRQ 0x5c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S1_IRQ 0x5d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S2_IRQ 0x5e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S3_IRQ 0x5f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S4_IRQ 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S5_IRQ 0x61</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S6_IRQ 0x62</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S7_IRQ 0x63</span><br><span> </span><br><span> /* Register defines. */</span><br><span> #define GPIO_MISCCFG 0x10</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h</span><br><span>index 34216bc..08555da 100644</span><br><span>--- a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h</span><br><span>+++ b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h</span><br><span>@@ -21,334 +21,263 @@</span><br><span> * The GPIO groups are accessed through register blocks called</span><br><span> * communities.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G 0</span><br><span> #define GPP_B 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define GROUP_SPI 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H 3</span><br><span> #define GPP_D 4</span><br><span> #define GPP_F 5</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define GROUP_VGPIO 7</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD 9</span><br><span style="color: hsl(0, 100%, 40%);">-#define GROUP_AZA 0xA</span><br><span style="color: hsl(0, 100%, 40%);">-#define GROUP_CPU 0xB</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C 0xC</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E 0xD</span><br><span style="color: hsl(0, 100%, 40%);">-#define GROUP_JTAG 0xE</span><br><span style="color: hsl(0, 100%, 40%);">-#define GROUP_HVMOS 0xF</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C 7</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S 0xA</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_NUM_GROUPS 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_NUM_GROUPS 11</span><br><span> #define GPIO_MAX_NUM_PER_GROUP 24</span><br><span> </span><br><span> /*</span><br><span> * GPIOs are ordered monotonically increasing to match ACPI/OS driver.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Group A */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A0 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A1 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A2 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A3 3</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A4 4</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A5 5</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A6 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A7 7</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A8 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A9 9</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A10 10</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A11 11</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A12 12</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A13 13</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A14 14</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A15 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A16 16</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A17 17</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A18 18</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A19 19</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A20 20</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A21 21</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A22 22</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_A23 23</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_0 24</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group B */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B0 25</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B1 26</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B2 27</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B3 28</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B4 29</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B5 30</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B6 31</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B7 32</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B8 33</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B9 34</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B10 35</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B11 36</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B12 37</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B13 38</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B14 39</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B15 40</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B16 41</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B17 42</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B18 43</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B19 44</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B20 45</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B21 46</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B22 47</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B23 48</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_1 49</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_2 50</span><br><span> /* Group G */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G0 51</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G1 52</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G2 53</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G3 54</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G4 55</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G5 56</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G6 57</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G7 58</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group SPI */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_3 59</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_4 60</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_5 61</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_6 62</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_7 63</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_8 64</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_9 65</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_10 66</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_11 67</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G0 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G1 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G2 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G3 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G4 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G5 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G6 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G7 7</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define NUM_GPIO_COM0_PADS (GPIO_RSVD_11 - GPP_A0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group B */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B0 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B1 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B2 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B3 11</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B4 12</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B5 13</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B6 14</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B7 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B8 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B9 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B10 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B11 19</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B12 20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B13 21</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B14 22</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B15 23</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B16 24</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B17 25</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B18 26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B19 27</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B20 28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B21 29</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B22 30</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B23 31</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_0 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_1 33</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group A */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A0 34</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A1 35</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A2 36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A3 37</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A4 38</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A5 39</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A6 40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A7 41</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A8 42</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A9 43</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A10 44</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A11 45</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A12 46</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A13 47</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A14 48</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A15 49</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A16 50</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A17 51</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A18 52</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A19 53</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A20 54</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A21 55</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A22 56</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A23 57</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM0_PADS (GPP_A23 - GPP_G0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group H */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H0 58</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H1 59</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H2 60</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H3 61</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H4 62</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H5 63</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H6 64</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H7 65</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H8 66</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H9 67</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H10 68</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H11 69</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H12 70</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H13 71</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H14 72</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H15 73</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H16 74</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H17 75</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H18 76</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H19 77</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H20 78</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H21 79</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H22 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H23 81</span><br><span> </span><br><span> /* Group D */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D0 68</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D1 69</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D2 70</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D3 71</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D4 72</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D5 73</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D6 74</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D7 75</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D8 76</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D9 77</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D10 78</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D11 79</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D12 80</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D13 81</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D14 82</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D15 83</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D16 84</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D17 85</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D18 86</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D19 87</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D20 88</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D21 89</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D22 90</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D23 91</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_12 92</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D0 82</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D1 83</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D2 84</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D3 85</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D4 86</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D5 87</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D6 88</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D7 89</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D8 90</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D9 91</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D10 92</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D11 93</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D12 94</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D13 95</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D14 96</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D15 97</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D16 98</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D17 99</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D18 100</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D19 101</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_2 102</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Group F */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F0 93</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F1 94</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F2 95</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F3 96</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F4 97</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F5 98</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F6 99</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F7 100</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F8 101</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F9 102</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F10 103</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F11 104</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F12 105</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F13 106</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F14 107</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F15 108</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F16 109</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F17 110</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F18 111</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F19 112</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F20 113</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F21 114</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F22 115</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F23 116</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group H */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H0 117</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H1 118</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H2 119</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H3 120</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H4 121</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H5 122</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H6 123</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H7 124</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H8 125</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H9 126</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H10 127</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H11 128</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H12 129</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H13 130</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H14 131</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H15 132</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H16 133</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H17 134</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H18 135</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H19 136</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H20 137</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H21 138</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H22 139</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H23 140</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group VGOIO */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_13 141</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_14 142</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_15 143</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_16 144</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_17 145</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_18 146</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_19 147</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_20 148</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_21 149</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_22 150</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_23 151</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_24 152</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_25 153</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_26 154</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_27 155</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_28 156</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_29 157</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_30 158</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_31 159</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_32 160</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_33 161</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_34 162</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_35 163</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_36 164</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_37 165</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_38 166</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_39 167</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_40 168</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_41 169</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_42 170</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_43 171</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_44 172</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_45 173</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_46 174</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_47 175</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_48 176</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_49 177</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_50 178</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_51 179</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_52 180</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F0 103</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F1 104</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F2 105</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F3 106</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F4 107</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F5 108</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F6 109</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F7 110</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F8 111</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F9 112</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F10 113</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F11 114</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F12 115</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F13 116</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F14 117</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F15 118</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F16 119</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F17 120</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F18 121</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F19 122</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define NUM_GPIO_COM1_PADS (GPIO_RSVD_52 - GPP_D0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM1_PADS (GPP_F19 - GPP_H0 + 1)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Group C */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C0 181</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C1 182</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C2 183</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C3 184</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C4 185</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C5 186</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C6 187</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C7 188</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C8 189</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C9 190</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C10 191</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C11 192</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C12 193</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C13 194</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C14 195</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C15 196</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C16 197</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C17 198</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C18 199</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C19 200</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C20 201</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C21 202</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C22 203</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C23 204</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group E */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E0 205</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E1 206</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E2 207</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E3 208</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E4 209</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E5 210</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E6 211</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E7 212</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E8 213</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E9 214</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E10 215</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E11 216</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E12 217</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E13 218</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E14 219</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E15 220</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E16 221</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E17 222</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E18 223</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E19 224</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E20 225</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E21 226</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E22 227</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E23 228</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group Jtag */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_53 229</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_54 230</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_55 231</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_56 232</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_57 233</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_58 234</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_59 235</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_60 236</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_61 237</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group HVMOS */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_62 238</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_63 239</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_64 240</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_65 241</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_66 242</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_67 243</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define NUM_GPIO_COM4_PADS (GPIO_RSVD_67 - GPP_C0 + 1)</span><br><span> </span><br><span> /* Group GPD */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD0 244</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD1 245</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD2 246</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD3 247</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD4 248</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD5 249</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD6 250</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD7 251</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD8 252</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD9 253</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD10 254</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD11 255</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD0 123</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD1 124</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD2 125</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD3 126</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD4 127</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD5 128</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD6 129</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD7 130</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD8 131</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD9 132</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD10 133</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD11 134</span><br><span> </span><br><span> #define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Group AZA */</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDA_BCLK 256</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDA_RSTB 257</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDA_SYNC 258</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDA_SDO 259</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDA_SDI_0 260</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDA_SDI_1 261</span><br><span style="color: hsl(0, 100%, 40%);">-#define SSP1_SFRM 262</span><br><span style="color: hsl(0, 100%, 40%);">-#define SSP1_TXD 263</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group CPU */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_68 264</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_69 265</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_70 266</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_71 267</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_72 268</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_73 269</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_74 270</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_75 271</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_76 272</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_77 273</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_78 274</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group C */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C0 135</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C1 136</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C2 137</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C3 138</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C4 139</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C5 140</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C6 141</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C7 142</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C8 143</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C9 144</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C10 145</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C11 146</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C12 147</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C13 148</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C14 149</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C15 150</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C16 151</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C17 152</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C18 153</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C19 154</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C20 155</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C21 156</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C22 157</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C23 158</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_3 159</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_4 160</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_5 161</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_6 162</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_7 163</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_8 164</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define NUM_GPIO_COM3_PADS (GPIO_RSVD_78 - HDA_BCLK + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group E */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E0 165</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E1 166</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E2 167</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E3 168</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E4 169</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E5 170</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E6 171</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E7 172</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E8 173</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E9 174</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E10 175</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E11 176</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E12 177</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E13 178</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E14 179</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E15 180</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E16 181</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E17 182</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E18 183</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E19 184</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E20 185</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E21 186</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E22 187</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E23 188</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define TOTAL_PADS 275</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM4_PADS (GPP_E23 - GPP_C0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group R*/</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R0 189</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R1 190</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R2 191</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R3 192</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R4 193</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R5 194</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R6 195</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_R7 196</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group S */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S0 197</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S1 198</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S2 199</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S3 200</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S4 201</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S5 202</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S6 203</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_S7 204</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM5_PADS (GPP_S7 - GPP_R0 + 1 )</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOTAL_PADS 205</span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/pmc.h b/src/soc/intel/icelake/include/soc/pmc.h</span><br><span>index 9418c73..448dbb5 100644</span><br><span>--- a/src/soc/intel/icelake/include/soc/pmc.h</span><br><span>+++ b/src/soc/intel/icelake/include/soc/pmc.h</span><br><span>@@ -115,15 +115,17 @@</span><br><span> #define GPE0_DWX_MASK 0xf</span><br><span> #define GPE0_DW_SHIFT(x) (4*(x))</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define PMC_GPP_A 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_G 0x0</span><br><span> #define PMC_GPP_B 0x1</span><br><span style="color: hsl(0, 100%, 40%);">-#define PMC_GPP_C 0xD</span><br><span style="color: hsl(0, 100%, 40%);">-#define PMC_GPP_D 0x4</span><br><span style="color: hsl(0, 100%, 40%);">-#define PMC_GPP_E 0xE</span><br><span style="color: hsl(0, 100%, 40%);">-#define PMC_GPP_F 0x5</span><br><span style="color: hsl(0, 100%, 40%);">-#define PMC_GPP_G 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_A 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_R 0x3</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_S 0x4</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPD 0x5</span><br><span> #define PMC_GPP_H 0x6</span><br><span style="color: hsl(0, 100%, 40%);">-#define PMC_GPD 0xA</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_D 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_F 0x8</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_C 0xA</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_E 0xB</span><br><span> </span><br><span> #define GBLRST_CAUSE0 0x1924</span><br><span> #define GBLRST_CAUSE0_THERMTRIP (1 << 5)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29495">change 29495</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I223abacc18f78631a42f340952f13d45fa9a4703 </div>
<div style="display:none"> Gerrit-Change-Number: 29495 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>