<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29513">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices<br><br>On this mainboard there is a legacy PCI device, which is connected to<br>the PCIe root port via a PCIe-2-PCI bridge. This device only supports<br>legacy interrupt routing. For this reason we have to adjust the PIR6<br>register (0x314c) which is responsible for PCIe device 13h and 14h. This<br>means that the interrupt routing will also be the same for both PCIe<br>devices. The bridge is connected to PCIe root port 2 and 3 over two<br>lanes (Device 13.0 and 13.1).<br><br>The following routing is required:<br>INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC#<br><br>Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c<br>1 file changed, 2 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/29513/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c</span><br><span>index ccf3ab8..f6858b0 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c</span><br><span>@@ -34,9 +34,9 @@</span><br><span> </span><br><span>        /*</span><br><span>    * PIR6 register mapping for PCIe root ports</span><br><span style="color: hsl(0, 100%, 40%);">-     * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#</span><br><span style="color: hsl(120, 100%, 40%);">+     * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC#</span><br><span>    */</span><br><span style="color: hsl(0, 100%, 40%);">-     pcr_write16(PID_ITSS, 0x314c, 0x0321);</span><br><span style="color: hsl(120, 100%, 40%);">+        pcr_write16(PID_ITSS, 0x314c, 0x2103);</span><br><span> </span><br><span>   /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */</span><br><span>     dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29513">change 29513</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29513"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87 </div>
<div style="display:none"> Gerrit-Change-Number: 29513 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>