<p>Li1 Feng has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29493">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">ish: enable for Sarien<br><br>WIP: not merge<br>C12/C13 is configured for ISH UART1<br>Signed-off-by: li feng <li1.feng@intel.com><br><br>Change-Id: Ibdb9eae3bb5e8beef3b6727ef8aae88d16893666<br>---<br>M src/mainboard/google/sarien/variants/sarien/devicetree.cb<br>M src/mainboard/google/sarien/variants/sarien/gpio.c<br>2 files changed, 3 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29493/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>index 1360b3f..55c2d11 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>@@ -106,6 +106,7 @@</span><br><span>           device pci 02.0 on  end # Integrated Graphics Device</span><br><span>                 device pci 04.0 on  end # SA Thermal device</span><br><span>          device pci 12.0 on  end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+           device pci 13.0 on  end # ISH</span><br><span>                device pci 12.5 off end # UFS SCS</span><br><span>            device pci 12.6 off end # GSPI #2</span><br><span>            device pci 14.0 on  end # USB xHCI</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>index 690af1f..95e395f 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>@@ -82,9 +82,8 @@</span><br><span> /* UART0_TXD */          PAD_NC(GPP_C9, NONE),</span><br><span> /* UART0_RTS# */       PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */</span><br><span> /* UART0_CTS# */      PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_RXD */         PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">-                              EDGE_SINGLE), /* SIO_EXT_WAKE# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_TXD */            PAD_NC(GPP_C13, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_RXD */     PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_TXD */              PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),</span><br><span> /* UART1_RTS# */       PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */</span><br><span> /* UART1_CTS# */        PAD_NC(GPP_C15, NONE),</span><br><span> /* I2C0_SDA */                PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29493">change 29493</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29493"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibdb9eae3bb5e8beef3b6727ef8aae88d16893666 </div>
<div style="display:none"> Gerrit-Change-Number: 29493 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Li1 Feng <li1.feng@intel.com> </div>