<p>Aamir Bohra would like Subrata Banik to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/29436">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/icelake: Add PID based on Icelake EDS<br><br>Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>---<br>M src/soc/intel/icelake/bootblock/pch.c<br>M src/soc/intel/icelake/include/soc/pcr_ids.h<br>2 files changed, 15 insertions(+), 33 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29436/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c</span><br><span>index 2fc94f4..bfdcd7e 100644</span><br><span>--- a/src/soc/intel/icelake/bootblock/pch.c</span><br><span>+++ b/src/soc/intel/icelake/bootblock/pch.c</span><br><span>@@ -34,9 +34,7 @@</span><br><span> #include <soc/pm.h></span><br><span> #include <soc/smbus.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP 0x1400</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 0x0980</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600</span><br><span> #define PCR_PSFX_TO_SHDW_BAR0 0</span><br><span> #define PCR_PSFX_TO_SHDW_BAR1 0x4</span><br><span> #define PCR_PSFX_TO_SHDW_BAR2 0x8</span><br><span>@@ -56,20 +54,6 @@</span><br><span> #define PCR_DMI_LPCIOD 0x2770</span><br><span> #define PCR_DMI_LPCIOE 0x2774</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static uint32_t get_pmc_reg_base(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t pch_series;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pch_series = get_pch_series();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (pch_series == PCH_H)</span><br><span style="color: hsl(0, 100%, 40%);">- return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H;</span><br><span style="color: hsl(0, 100%, 40%);">- else if (pch_series == PCH_LP)</span><br><span style="color: hsl(0, 100%, 40%);">- return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP;</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void soc_config_pwrmbase(void)</span><br><span> {</span><br><span> uint32_t reg32;</span><br><span>@@ -113,26 +97,22 @@</span><br><span> static void soc_config_acpibase(void)</span><br><span> {</span><br><span> uint32_t pmc_reg_value;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t pmc_base_reg;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pmc_base_reg = get_pmc_reg_base();</span><br><span style="color: hsl(0, 100%, 40%);">- if (!pmc_base_reg)</span><br><span style="color: hsl(0, 100%, 40%);">- die("Invalid PMC base address\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +</span><br><span style="color: hsl(120, 100%, 40%);">+ PCR_PSFX_TO_SHDW_BAR4);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg +</span><br><span style="color: hsl(0, 100%, 40%);">- PCR_PSFX_TO_SHDW_BAR4);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (pmc_reg_value != 0xFFFFFFFF) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pmc_reg_value != 0xFFFFFFFF)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span> /* Disable Io Space before changing the address */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_rmw32(PID_PSF3, pmc_base_reg +</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +</span><br><span> PCR_PSFX_T0_SHDW_PCIEN,</span><br><span> ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);</span><br><span> /* Program ABASE in PSF3 PMC space BAR4*/</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_PSF3, pmc_base_reg +</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +</span><br><span> PCR_PSFX_TO_SHDW_BAR4,</span><br><span> ACPI_BASE_ADDRESS);</span><br><span> /* Enable IO Space */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_rmw32(PID_PSF3, pmc_base_reg +</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +</span><br><span> PCR_PSFX_T0_SHDW_PCIEN,</span><br><span> ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/pcr_ids.h b/src/soc/intel/icelake/include/soc/pcr_ids.h</span><br><span>index b75bf67..a6ad30b 100644</span><br><span>--- a/src/soc/intel/icelake/include/soc/pcr_ids.h</span><br><span>+++ b/src/soc/intel/icelake/include/soc/pcr_ids.h</span><br><span>@@ -20,11 +20,13 @@</span><br><span> */</span><br><span> #define PID_EMMC 0x52</span><br><span> #define PID_SDX 0x53</span><br><span style="color: hsl(0, 100%, 40%);">-#define PID_GPIOCOM4 0x6a</span><br><span style="color: hsl(0, 100%, 40%);">-#define PID_GPIOCOM3 0x6b</span><br><span style="color: hsl(0, 100%, 40%);">-#define PID_GPIOCOM2 0x6c</span><br><span style="color: hsl(0, 100%, 40%);">-#define PID_GPIOCOM1 0x6d</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define PID_GPIOCOM0 0x6e</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIOCOM1 0x6d</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIOCOM2 0x6c</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIOCOM4 0x6a</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIOCOM5 0x69</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define PID_DMI 0x88</span><br><span> #define PID_PSTH 0x89</span><br><span> #define PID_CSME0 0x90</span><br><span>@@ -35,7 +37,7 @@</span><br><span> #define PID_PSF4 0xbd</span><br><span> #define PID_SCS 0xc0</span><br><span> #define PID_RTC 0xc3</span><br><span style="color: hsl(0, 100%, 40%);">-#define PID_ITSS 0xc2</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_ITSS 0xc4</span><br><span> #define PID_LPC 0xc7</span><br><span> #define PID_SERIALIO 0xcb</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29436">change 29436</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10 </div>
<div style="display:none"> Gerrit-Change-Number: 29436 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>