<p>Nico Huber <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/29403">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Add missing include <stdint.h><br><br>Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>Reviewed-on: https://review.coreboot.org/29403<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/arch/x86/include/arch/registers.h<br>M src/cpu/ti/am335x/uart.h<br>M src/drivers/i2c/max98373/chip.h<br>M src/drivers/i2c/rt5663/chip.h<br>M src/drivers/i2c/w83795/chip.h<br>M src/drivers/intel/fsp2_0/include/fsp/upd.h<br>M src/drivers/net/chip.h<br>M src/drivers/parade/ps8625/ps8625.h<br>M src/drivers/siemens/nc_fpga/nc_fpga.h<br>M src/include/cpu/amd/vr.h<br>M src/include/device/path.h<br>M src/include/swab.h<br>M src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h<br>M src/mainboard/google/urara/urara_boardid.h<br>M src/mainboard/pcengines/apu1/gpio_ftns.h<br>M src/northbridge/intel/e7505/raminit.h<br>M src/northbridge/intel/haswell/pei_data.h<br>M src/northbridge/intel/sandybridge/pei_data.h<br>M src/security/tpm/tss/tcg-1.2/tss_commands.h<br>M src/security/tpm/tss/tcg-1.2/tss_internal.h<br>M src/security/tpm/tss_errors.h<br>M src/soc/broadcom/cygnus/include/soc/tz.h<br>M src/soc/cavium/cn81xx/include/soc/cpu.h<br>M src/soc/cavium/common/include/soc/bootblock.h<br>M src/soc/intel/apollolake/include/soc/usb.h<br>M src/soc/intel/broadwell/chip.h<br>M src/soc/intel/cannonlake/include/soc/ebda.h<br>M src/soc/intel/denverton_ns/chip.h<br>M src/soc/intel/icelake/include/soc/ebda.h<br>M src/soc/intel/quark/include/soc/i2c.h<br>M src/soc/intel/skylake/include/soc/ebda.h<br>M src/soc/nvidia/tegra210/include/soc/flow_ctrl.h<br>M src/soc/qualcomm/ipq806x/include/soc/ebi2.h<br>M src/southbridge/intel/bd82x6x/chip.h<br>M src/southbridge/intel/fsp_bd82x6x/chip.h<br>M src/southbridge/intel/fsp_i89xx/chip.h<br>M src/southbridge/intel/i82801dx/chip.h<br>M src/southbridge/intel/i82801gx/chip.h<br>M src/southbridge/intel/i82801ix/chip.h<br>M src/southbridge/intel/i82801jx/chip.h<br>M src/southbridge/intel/lynxpoint/chip.h<br>M src/superio/nuvoton/npcd378/npcd378.h<br>42 files changed, 90 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h</span><br><span>index 08f83ac..1d3b90a 100644</span><br><span>--- a/src/arch/x86/include/arch/registers.h</span><br><span>+++ b/src/arch/x86/include/arch/registers.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #define __ARCH_REGISTERS_H</span><br><span> </span><br><span> #if !defined(__ASSEMBLER__)</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define DOWNTO8(A) \</span><br><span> union { \</span><br><span> struct { \</span><br><span>diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h</span><br><span>index 000a45d..fe9197f 100644</span><br><span>--- a/src/cpu/ti/am335x/uart.h</span><br><span>+++ b/src/cpu/ti/am335x/uart.h</span><br><span>@@ -15,6 +15,8 @@</span><br><span> #ifndef AM335X_UART_H</span><br><span> #define AM335X_UART_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define AM335X_UART0_BASE 0x44e09000</span><br><span> #define AM335X_UART1_BASE 0x48020000</span><br><span> #define AM335X_UART2_BASE 0x48024000</span><br><span>diff --git a/src/drivers/i2c/max98373/chip.h b/src/drivers/i2c/max98373/chip.h</span><br><span>index ad81395..dcaf357 100644</span><br><span>--- a/src/drivers/i2c/max98373/chip.h</span><br><span>+++ b/src/drivers/i2c/max98373/chip.h</span><br><span>@@ -16,6 +16,9 @@</span><br><span> /*</span><br><span> * Maxim MAX98373 audio codec devicetree bindings</span><br><span> */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct drivers_i2c_max98373_config {</span><br><span> /* I2C Bus Frequency in Hertz (default 400kHz) */</span><br><span> uint32_t bus_speed;</span><br><span>diff --git a/src/drivers/i2c/rt5663/chip.h b/src/drivers/i2c/rt5663/chip.h</span><br><span>index 1b367c9..5720b18 100644</span><br><span>--- a/src/drivers/i2c/rt5663/chip.h</span><br><span>+++ b/src/drivers/i2c/rt5663/chip.h</span><br><span>@@ -16,6 +16,9 @@</span><br><span> /*</span><br><span> * Realtek RT5663 audio codec devicetree bindings</span><br><span> */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct drivers_i2c_rt5663_config {</span><br><span> /* I2C Bus Frequency in Hertz (default 400kHz) */</span><br><span> unsigned int bus_speed;</span><br><span>diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h</span><br><span>index b48c523..e3426de 100644</span><br><span>--- a/src/drivers/i2c/w83795/chip.h</span><br><span>+++ b/src/drivers/i2c/w83795/chip.h</span><br><span>@@ -13,6 +13,8 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct drivers_i2c_w83795_config {</span><br><span> uint8_t fanin_ctl1;</span><br><span> uint8_t fanin_ctl2;</span><br><span>diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h</span><br><span>index 15094df..19c5423 100644</span><br><span>--- a/src/drivers/intel/fsp2_0/include/fsp/upd.h</span><br><span>+++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h</span><br><span>@@ -12,6 +12,8 @@</span><br><span> #ifndef _FSP2_0_UPD_H_</span><br><span> #define _FSP2_0_UPD_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct FSP_UPD_HEADER {</span><br><span> ///</span><br><span> /// UPD Region Signature. This signature will be</span><br><span>diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h</span><br><span>index 383614f..985a85a 100644</span><br><span>--- a/src/drivers/net/chip.h</span><br><span>+++ b/src/drivers/net/chip.h</span><br><span>@@ -14,6 +14,8 @@</span><br><span> #ifndef __DRIVERS_R8168_CHIP_H__</span><br><span> #define __DRIVERS_R8168_CHIP_H__</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct drivers_net_config {</span><br><span> uint16_t customized_leds;</span><br><span> unsigned wake; /* Wake pin for ACPI _PRW */</span><br><span>diff --git a/src/drivers/parade/ps8625/ps8625.h b/src/drivers/parade/ps8625/ps8625.h</span><br><span>index 1fbb01c..a5132f1 100644</span><br><span>--- a/src/drivers/parade/ps8625/ps8625.h</span><br><span>+++ b/src/drivers/parade/ps8625/ps8625.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef __PS8625_H__</span><br><span> #define __PS8625_H__</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct parade_write {</span><br><span> uint8_t offset;</span><br><span> uint8_t reg;</span><br><span>diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.h b/src/drivers/siemens/nc_fpga/nc_fpga.h</span><br><span>index fe5f612..f1982d2 100644</span><br><span>--- a/src/drivers/siemens/nc_fpga/nc_fpga.h</span><br><span>+++ b/src/drivers/siemens/nc_fpga/nc_fpga.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef _SIEMENS_NC_FPGA_H_</span><br><span> #define _SIEMENS_NC_FPGA_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define NC_MAGIC_OFFSET 0x020</span><br><span> #define NC_FPGA_MAGIC 0x4E433746</span><br><span> #define NC_CAP1_OFFSET 0x080</span><br><span>diff --git a/src/include/cpu/amd/vr.h b/src/include/cpu/amd/vr.h</span><br><span>index e5ab840..8c62e44 100644</span><br><span>--- a/src/include/cpu/amd/vr.h</span><br><span>+++ b/src/include/cpu/amd/vr.h</span><br><span>@@ -7,6 +7,8 @@</span><br><span> #ifndef CPU_AMD_VR_H</span><br><span> #define CPU_AMD_VR_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define VRC_INDEX 0xAC1C // Index register</span><br><span> #define VRC_DATA 0xAC1E // Data register</span><br><span> #define VR_UNLOCK 0xFC53 // Virtual register unlock code</span><br><span>diff --git a/src/include/device/path.h b/src/include/device/path.h</span><br><span>index 0d9c681..6736bed 100644</span><br><span>--- a/src/include/device/path.h</span><br><span>+++ b/src/include/device/path.h</span><br><span>@@ -1,6 +1,8 @@</span><br><span> #ifndef DEVICE_PATH_H</span><br><span> #define DEVICE_PATH_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> enum device_path_type {</span><br><span> DEVICE_PATH_NONE = 0,</span><br><span> DEVICE_PATH_ROOT,</span><br><span>diff --git a/src/include/swab.h b/src/include/swab.h</span><br><span>index 7d781a0..956cfa5 100644</span><br><span>--- a/src/include/swab.h</span><br><span>+++ b/src/include/swab.h</span><br><span>@@ -1,6 +1,3 @@</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef _SWAB_H</span><br><span style="color: hsl(0, 100%, 40%);">-#define _SWAB_H</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /*</span><br><span> * linux/byteorder/swab.h</span><br><span> * Byte-swapping, independently from CPU endianness</span><br><span>@@ -18,6 +15,12 @@</span><br><span> /* casts are necessary for constants, because we never know how for sure</span><br><span> * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way.</span><br><span> */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SWAB_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SWAB_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define swab16(x) \</span><br><span> ((unsigned short)( \</span><br><span> (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \</span><br><span>diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h</span><br><span>index 903ebaa..8f1e24c 100644</span><br><span>--- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h</span><br><span>+++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> * Copyed over from qemu soure tree, include/hw/nvram/fw_cfg.h</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define FW_CFG_SIGNATURE 0x00</span><br><span> #define FW_CFG_ID 0x01</span><br><span> #define FW_CFG_UUID 0x02</span><br><span>diff --git a/src/mainboard/google/urara/urara_boardid.h b/src/mainboard/google/urara/urara_boardid.h</span><br><span>index 7c7c045..fbd9179 100644</span><br><span>--- a/src/mainboard/google/urara/urara_boardid.h</span><br><span>+++ b/src/mainboard/google/urara/urara_boardid.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__</span><br><span> #define __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * List of URARA derivatives board ID definitions. They are stored in uint8_t</span><br><span> * across the code, using #defines here not to imply any specific size.</span><br><span>diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.h b/src/mainboard/pcengines/apu1/gpio_ftns.h</span><br><span>index 8eadebd..fce8afe 100644</span><br><span>--- a/src/mainboard/pcengines/apu1/gpio_ftns.h</span><br><span>+++ b/src/mainboard/pcengines/apu1/gpio_ftns.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef GPIO_FTNS_H</span><br><span> #define GPIO_FTNS_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> uintptr_t find_gpio_base(void);</span><br><span> void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting);</span><br><span> u8 read_gpio(uintptr_t base_addr, u32 gpio);</span><br><span>diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h</span><br><span>index 1581b82..cdfc92a 100644</span><br><span>--- a/src/northbridge/intel/e7505/raminit.h</span><br><span>+++ b/src/northbridge/intel/e7505/raminit.h</span><br><span>@@ -14,6 +14,8 @@</span><br><span> #ifndef RAMINIT_H</span><br><span> #define RAMINIT_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define MAX_DIMM_SOCKETS_PER_CHANNEL 4</span><br><span> #define MAX_NUM_CHANNELS 2</span><br><span> #define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL)</span><br><span>diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h</span><br><span>index 319b9e7..dfc34d8 100644</span><br><span>--- a/src/northbridge/intel/haswell/pei_data.h</span><br><span>+++ b/src/northbridge/intel/haswell/pei_data.h</span><br><span>@@ -30,6 +30,8 @@</span><br><span> #ifndef PEI_DATA_H</span><br><span> #define PEI_DATA_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> typedef void (*tx_byte_func)(unsigned char byte);</span><br><span> #define PEI_VERSION 15</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h</span><br><span>index 00534ca..0a60707 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/pei_data.h</span><br><span>+++ b/src/northbridge/intel/sandybridge/pei_data.h</span><br><span>@@ -30,6 +30,8 @@</span><br><span> #ifndef PEI_DATA_H</span><br><span> #define PEI_DATA_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> typedef struct {</span><br><span> uint16_t mode; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto</span><br><span> uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable</span><br><span>diff --git a/src/security/tpm/tss/tcg-1.2/tss_commands.h b/src/security/tpm/tss/tcg-1.2/tss_commands.h</span><br><span>index 9d30bfc..acdc8be 100644</span><br><span>--- a/src/security/tpm/tss/tcg-1.2/tss_commands.h</span><br><span>+++ b/src/security/tpm/tss/tcg-1.2/tss_commands.h</span><br><span>@@ -14,6 +14,8 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> const struct s_tpm_extend_cmd{</span><br><span> uint8_t buffer[34];</span><br><span> uint16_t pcrNum;</span><br><span>diff --git a/src/security/tpm/tss/tcg-1.2/tss_internal.h b/src/security/tpm/tss/tcg-1.2/tss_internal.h</span><br><span>index 01912bb..e999cb9 100644</span><br><span>--- a/src/security/tpm/tss/tcg-1.2/tss_internal.h</span><br><span>+++ b/src/security/tpm/tss/tcg-1.2/tss_internal.h</span><br><span>@@ -6,6 +6,8 @@</span><br><span> #ifndef TCG_TSS_INTERNAL_H_</span><br><span> #define TCG_TSS_INTERNAL_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * These numbers derive from adding the sizes of command fields as shown in the</span><br><span> * TPM commands manual.</span><br><span>diff --git a/src/security/tpm/tss_errors.h b/src/security/tpm/tss_errors.h</span><br><span>index c80ffa1..316661c 100644</span><br><span>--- a/src/security/tpm/tss_errors.h</span><br><span>+++ b/src/security/tpm/tss_errors.h</span><br><span>@@ -12,6 +12,8 @@</span><br><span> #ifndef TSS_ERRORS_H_</span><br><span> #define TSS_ERRORS_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define TPM_E_BASE 0x0</span><br><span> #define TPM_E_NON_FATAL 0x800</span><br><span> </span><br><span>diff --git a/src/soc/broadcom/cygnus/include/soc/tz.h b/src/soc/broadcom/cygnus/include/soc/tz.h</span><br><span>index a6777fd..1d5d234 100644</span><br><span>--- a/src/soc/broadcom/cygnus/include/soc/tz.h</span><br><span>+++ b/src/soc/broadcom/cygnus/include/soc/tz.h</span><br><span>@@ -14,6 +14,8 @@</span><br><span> #ifndef __SOC_BROADCOM_CYGNUS_TZ_H__</span><br><span> #define __SOC_BROADCOM_CYGNUS_TZ_H__</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define TZ_STATE_SECURE 0</span><br><span> #define TZ_STATE_NON_SECURE 1</span><br><span> </span><br><span>diff --git a/src/soc/cavium/cn81xx/include/soc/cpu.h b/src/soc/cavium/cn81xx/include/soc/cpu.h</span><br><span>index b2472d7..1c6a30d 100644</span><br><span>--- a/src/soc/cavium/cn81xx/include/soc/cpu.h</span><br><span>+++ b/src/soc/cavium/cn81xx/include/soc/cpu.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef __SOC_CAVIUM_CN81XX_CPU_H__</span><br><span> #define __SOC_CAVIUM_CN81XX_CPU_H__</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /**</span><br><span> * Number of the Core on which the program is currently running.</span><br><span> *</span><br><span>diff --git a/src/soc/cavium/common/include/soc/bootblock.h b/src/soc/cavium/common/include/soc/bootblock.h</span><br><span>index 76fd4a15..1df444f 100644</span><br><span>--- a/src/soc/cavium/common/include/soc/bootblock.h</span><br><span>+++ b/src/soc/cavium/common/include/soc/bootblock.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_</span><br><span> #define SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void bootblock_mainboard_early_init(void);</span><br><span> void bootblock_soc_early_init(void);</span><br><span> void bootblock_soc_init(void);</span><br><span>diff --git a/src/soc/intel/apollolake/include/soc/usb.h b/src/soc/intel/apollolake/include/soc/usb.h</span><br><span>index 7220023..7dd9ec0 100644</span><br><span>--- a/src/soc/intel/apollolake/include/soc/usb.h</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/usb.h</span><br><span>@@ -18,6 +18,8 @@</span><br><span> #ifndef _SOC_APOLLOLAKE_USB_H_</span><br><span> #define _SOC_APOLLOLAKE_USB_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define APOLLOLAKE_USB2_PORT_MAX 8</span><br><span> </span><br><span> struct usb2_eye_per_port {</span><br><span>diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h</span><br><span>index 46c2c1d..0885c2d 100644</span><br><span>--- a/src/soc/intel/broadwell/chip.h</span><br><span>+++ b/src/soc/intel/broadwell/chip.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef _SOC_INTEL_BROADWELL_CHIP_H_</span><br><span> #define _SOC_INTEL_BROADWELL_CHIP_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct soc_intel_broadwell_config {</span><br><span> /*</span><br><span> * Interrupt Routing configuration</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/ebda.h b/src/soc/intel/cannonlake/include/soc/ebda.h</span><br><span>index 15a9d28..ad62394 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/ebda.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/ebda.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef SOC_EBDA_H</span><br><span> #define SOC_EBDA_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct ebda_config {</span><br><span> uint32_t signature; /* 0x00 - EBDA signature */</span><br><span> uint32_t tolum_base; /* 0x04 - coreboot memory start */</span><br><span>diff --git a/src/soc/intel/denverton_ns/chip.h b/src/soc/intel/denverton_ns/chip.h</span><br><span>index bfa6a01..f2a67dd 100644</span><br><span>--- a/src/soc/intel/denverton_ns/chip.h</span><br><span>+++ b/src/soc/intel/denverton_ns/chip.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef SOC_INTEL_DENVERTON_NS_CHIP_H</span><br><span> #define SOC_INTEL_DENVERTON_NS_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct soc_intel_denverton_ns_config {</span><br><span> /**</span><br><span> * Interrupt Routing configuration</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/ebda.h b/src/soc/intel/icelake/include/soc/ebda.h</span><br><span>index 9c44a50..f4d89e9 100644</span><br><span>--- a/src/soc/intel/icelake/include/soc/ebda.h</span><br><span>+++ b/src/soc/intel/icelake/include/soc/ebda.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef SOC_EBDA_H</span><br><span> #define SOC_EBDA_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct ebda_config {</span><br><span> uint32_t signature; /* 0x00 - EBDA signature */</span><br><span> uint32_t tolum_base; /* 0x04 - coreboot memory start */</span><br><span>diff --git a/src/soc/intel/quark/include/soc/i2c.h b/src/soc/intel/quark/include/soc/i2c.h</span><br><span>index 85ae7b9..f3c585f 100644</span><br><span>--- a/src/soc/intel/quark/include/soc/i2c.h</span><br><span>+++ b/src/soc/intel/quark/include/soc/i2c.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef _QUARK_I2C_H_</span><br><span> #define _QUARK_I2C_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> typedef volatile struct _I2C_REGS {</span><br><span> volatile uint32_t ic_con; /* 00: Control Register */</span><br><span> volatile uint32_t ic_tar; /* 04: Master Target Address */</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/ebda.h b/src/soc/intel/skylake/include/soc/ebda.h</span><br><span>index 15a9d28..ad62394 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/ebda.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/ebda.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef SOC_EBDA_H</span><br><span> #define SOC_EBDA_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct ebda_config {</span><br><span> uint32_t signature; /* 0x00 - EBDA signature */</span><br><span> uint32_t tolum_base; /* 0x04 - coreboot memory start */</span><br><span>diff --git a/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h</span><br><span>index 2dd1f9f..602c75c 100644</span><br><span>--- a/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h</span><br><span>+++ b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef _TEGRA210_FLOW_CTRL_H_</span><br><span> #define _TEGRA210_FLOW_CTRL_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void flowctrl_cpu_off(int cpu);</span><br><span> void flowctrl_cpu_on(int cpu);</span><br><span> void flowctrl_cpu_suspend(int cpu);</span><br><span>diff --git a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h</span><br><span>index 3e99c3b..5dcd9b8 100644</span><br><span>--- a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h</span><br><span>+++ b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h</span><br><span>@@ -19,6 +19,8 @@</span><br><span> #ifndef __SOC_QUALCOMM_IPQ806X_EBI2_H_</span><br><span> #define __SOC_QUALCOMM_IPQ806X_EBI2_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define EBI2CR_BASE (0x1A600000)</span><br><span> </span><br><span> struct ebi2cr_regs {</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h</span><br><span>index ce8a804..29f6881 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/chip.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H</span><br><span> #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct southbridge_intel_bd82x6x_config {</span><br><span> /**</span><br><span> * GPI Routing configuration</span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/chip.h b/src/southbridge/intel/fsp_bd82x6x/chip.h</span><br><span>index 9d6a9e4..8da3936 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/chip.h</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H</span><br><span> #define SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct southbridge_intel_fsp_bd82x6x_config {</span><br><span> /**</span><br><span> * Interrupt Routing configuration</span><br><span>diff --git a/src/southbridge/intel/fsp_i89xx/chip.h b/src/southbridge/intel/fsp_i89xx/chip.h</span><br><span>index 69e1dc7..bea3e07 100644</span><br><span>--- a/src/southbridge/intel/fsp_i89xx/chip.h</span><br><span>+++ b/src/southbridge/intel/fsp_i89xx/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef SOUTHBRIDGE_INTEL_I89XX_CHIP_H</span><br><span> #define SOUTHBRIDGE_INTEL_I89XX_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct southbridge_intel_fsp_i89xx_config {</span><br><span> /**</span><br><span> * Interrupt Routing configuration</span><br><span>diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h</span><br><span>index f77413d..a0961ee 100644</span><br><span>--- a/src/southbridge/intel/i82801dx/chip.h</span><br><span>+++ b/src/southbridge/intel/i82801dx/chip.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef I82801DX_CHIP_H</span><br><span> #define I82801DX_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct southbridge_intel_i82801dx_config {</span><br><span> int enable_usb;</span><br><span> int enable_native_ide;</span><br><span>diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h</span><br><span>index e89fcc4..3a20ab1 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/chip.h</span><br><span>+++ b/src/southbridge/intel/i82801gx/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H</span><br><span> #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct southbridge_intel_i82801gx_config {</span><br><span> /**</span><br><span> * Interrupt Routing configuration</span><br><span>diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h</span><br><span>index 307b751..0b3e0b5 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/chip.h</span><br><span>+++ b/src/southbridge/intel/i82801ix/chip.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H</span><br><span> #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> enum {</span><br><span> THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3,</span><br><span> THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7</span><br><span>diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h</span><br><span>index 533254a..1712b81 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/chip.h</span><br><span>+++ b/src/southbridge/intel/i82801jx/chip.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H</span><br><span> #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> enum {</span><br><span> THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3,</span><br><span> THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h</span><br><span>index d11ce5f..09f1c90 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/chip.h</span><br><span>+++ b/src/southbridge/intel/lynxpoint/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H</span><br><span> #define SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct southbridge_intel_lynxpoint_config {</span><br><span> /**</span><br><span> * Interrupt Routing configuration</span><br><span>diff --git a/src/superio/nuvoton/npcd378/npcd378.h b/src/superio/nuvoton/npcd378/npcd378.h</span><br><span>index 53541a9..cf0b804 100644</span><br><span>--- a/src/superio/nuvoton/npcd378/npcd378.h</span><br><span>+++ b/src/superio/nuvoton/npcd378/npcd378.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef SUPERIO_NUVOTON_NPCD378_H</span><br><span> #define SUPERIO_NUVOTON_NPCD378_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* HWM at LDN8 */</span><br><span> #define NPCD837_HWM_WRITE_LOCK_CTRL 0x4</span><br><span> #define NPCD837_HWM_WRITE_LOCK_BIT 0x1</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29403">change 29403</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29403"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 </div>
<div style="display:none"> Gerrit-Change-Number: 29403 </div>
<div style="display:none"> Gerrit-PatchSet: 9 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>