<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29420">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek: Refactor PMIC wrapper code among similar SoCs<br><br>Refactor PMIC wrapper code which will be reused among similar SoCs.<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Kukui<br><br>Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d<br>Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com><br>---<br>A src/soc/mediatek/common/include/soc/pmic_wrap_common.h<br>A src/soc/mediatek/common/pmic_wrap.c<br>M src/soc/mediatek/mt8173/Makefile.inc<br>M src/soc/mediatek/mt8173/include/soc/pmic_wrap.h<br>M src/soc/mediatek/mt8173/pmic_wrap.c<br>5 files changed, 376 insertions(+), 337 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/29420/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h</span><br><span>new file mode 100644</span><br><span>index 0000000..f01e9b0</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h</span><br><span>@@ -0,0 +1,204 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_MEDIATEK_PMIC_WRAP_COMMON_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_MEDIATEK_PMIC_WRAP_COMMON_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PWRAPTAG "[PWRAP] "</span><br><span style="color: hsl(120, 100%, 40%);">+#define pwrap_err(fmt, arg ...) printk(BIOS_ERR, PWRAPTAG "ERROR,line=%d" fmt, \</span><br><span style="color: hsl(120, 100%, 40%);">+ __LINE__, ## arg)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* external API */</span><br><span style="color: hsl(120, 100%, 40%);">+s32 pwrap_read(u16 adr, u16 *rdata);</span><br><span style="color: hsl(120, 100%, 40%);">+s32 pwrap_write(u16 adr, u16 wdata);</span><br><span style="color: hsl(120, 100%, 40%);">+s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check);</span><br><span style="color: hsl(120, 100%, 40%);">+s32 pwrap_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* internal API */</span><br><span style="color: hsl(120, 100%, 40%);">+s32 pwrap_reset_spislv(void);</span><br><span style="color: hsl(120, 100%, 40%);">+s32 pwrap_read_nochk(u16 adr, u16 *rdata);</span><br><span style="color: hsl(120, 100%, 40%);">+s32 pwrap_write_nochk(u16 adr, u16 wdata);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* dewrapper defaule value */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DEFAULT_VALUE_READ_TEST = 0x5aa5,</span><br><span style="color: hsl(120, 100%, 40%);">+ WRITE_TEST_VALUE = 0xa55a</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* timeout setting */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ TIMEOUT_READ_US = 255,</span><br><span style="color: hsl(120, 100%, 40%);">+ TIMEOUT_WAIT_IDLE_US = 255</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* manual commnd */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ OP_WR = 0x1,</span><br><span style="color: hsl(120, 100%, 40%);">+ OP_CSH = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ OP_CSL = 0x1,</span><br><span style="color: hsl(120, 100%, 40%);">+ OP_OUTS = 0x8,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_WACS_RDATA_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_WACS_FSM_SHIFT = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_WACS_REQ_SHIFT = 19,</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_SYNC_IDLE_SHIFT,</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_INIT_DONE_SHIFT,</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_SYS_IDLE_SHIFT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_WACS_RDATA_MASK = 0xffff,</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_WACS_FSM_MASK = 0x7,</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_WACS_REQ_MASK = 0x1,</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_SYNC_IDLE_MASK = 0x1,</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_INIT_DONE_MASK = 0x1,</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_SYS_IDLE_MASK = 0x1,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* WACS_FSM */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ WACS_FSM_IDLE = 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ WACS_FSM_REQ = 0x02,</span><br><span style="color: hsl(120, 100%, 40%);">+ WACS_FSM_WFDLE = 0x04, /* wait for dle, wait for read data done */</span><br><span style="color: hsl(120, 100%, 40%);">+ WACS_FSM_WFVLDCLR = 0x06, /* finish read data, wait for valid flag</span><br><span style="color: hsl(120, 100%, 40%);">+ * clearing */</span><br><span style="color: hsl(120, 100%, 40%);">+ WACS_INIT_DONE = 0x01,</span><br><span style="color: hsl(120, 100%, 40%);">+ WACS_SYNC_IDLE = 0x01,</span><br><span style="color: hsl(120, 100%, 40%);">+ WACS_SYNC_BUSY = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* error information flag */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INVALID_ARG = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INVALID_RW = 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INVALID_ADDR = 3,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INVALID_WDAT = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INVALID_OP_MANUAL = 5,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_NOT_IDLE_STATE = 6,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_NOT_INIT_DONE = 7,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_NOT_INIT_DONE_READ = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_WAIT_IDLE_TIMEOUT = 9,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INIT_SIDLY_FAIL = 11,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_RESET_TIMEOUT = 12,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_TIMEOUT = 13,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INIT_RESET_SPI = 20,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INIT_SIDLY = 21,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INIT_REG_CLOCK = 22,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INIT_ENABLE_PMIC = 23,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INIT_DIO = 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INIT_CIPHER = 25,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INIT_WRITE_TEST = 26,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INIT_ENABLE_CRC = 27,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INIT_ENABLE_DEWRAP = 28,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_INIT_ENABLE_EVENT = 29,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_READ_TEST_FAIL = 30,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_WRITE_TEST_FAIL = 31,</span><br><span style="color: hsl(120, 100%, 40%);">+ E_PWR_SWITCH_DIO = 32</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+typedef u32 (*loop_condition_fp)(u32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 wait_for_fsm_vldclr(u32 x)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return ((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=</span><br><span style="color: hsl(120, 100%, 40%);">+ WACS_FSM_WFVLDCLR;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 wait_for_sync(u32 x)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return ((x >> RDATA_SYNC_IDLE_SHIFT) & RDATA_SYNC_IDLE_MASK) !=</span><br><span style="color: hsl(120, 100%, 40%);">+ WACS_SYNC_IDLE;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 wait_for_idle_and_sync(u32 x)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return ((((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=</span><br><span style="color: hsl(120, 100%, 40%);">+ WACS_FSM_IDLE) || (((x >> RDATA_SYNC_IDLE_SHIFT) &</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_SYNC_IDLE_MASK) != WACS_SYNC_IDLE));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 wait_for_cipher_ready(u32 x)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return x != 3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 wait_for_state_idle(u32 timeout_us, void *wacs_register,</span><br><span style="color: hsl(120, 100%, 40%);">+ void *wacs_vldclr_register,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *read_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg_rdata;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ struct stopwatch sw;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ stopwatch_init_usecs_expire(&sw, timeout_us);</span><br><span style="color: hsl(120, 100%, 40%);">+ do {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg_rdata = read32((wacs_register));</span><br><span style="color: hsl(120, 100%, 40%);">+ /* if last read command timeout,clear vldclr bit</span><br><span style="color: hsl(120, 100%, 40%);">+ read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;</span><br><span style="color: hsl(120, 100%, 40%);">+ write:FSM_REQ-->idle */</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) &</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_WACS_FSM_MASK)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case WACS_FSM_WFVLDCLR:</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(wacs_vldclr_register, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pwrap_err("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case WACS_FSM_WFDLE:</span><br><span style="color: hsl(120, 100%, 40%);">+ pwrap_err("WACS_FSM = WACS_FSM_WFDLE\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case WACS_FSM_REQ:</span><br><span style="color: hsl(120, 100%, 40%);">+ pwrap_err("WACS_FSM = WACS_FSM_REQ\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (stopwatch_expired(&sw))</span><br><span style="color: hsl(120, 100%, 40%);">+ return E_PWR_WAIT_IDLE_TIMEOUT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ } while (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=</span><br><span style="color: hsl(120, 100%, 40%);">+ WACS_FSM_IDLE); /* IDLE State */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (read_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+ *read_reg = reg_rdata;</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us,</span><br><span style="color: hsl(120, 100%, 40%);">+ void *wacs_register, u32 *read_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg_rdata;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct stopwatch sw;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ stopwatch_init_usecs_expire(&sw, timeout_us);</span><br><span style="color: hsl(120, 100%, 40%);">+ do {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg_rdata = read32((wacs_register));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (stopwatch_expired(&sw)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pwrap_err("timeout when waiting for idle\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return E_PWR_WAIT_IDLE_TIMEOUT;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } while (fp(reg_rdata)); /* IDLE State */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (read_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+ *read_reg = reg_rdata;</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOC_MEDIATEK_PMIC_WRAP_COMMON_H */</span><br><span>diff --git a/src/soc/mediatek/common/pmic_wrap.c b/src/soc/mediatek/common/pmic_wrap.c</span><br><span>new file mode 100644</span><br><span>index 0000000..9e0832a</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/common/pmic_wrap.c</span><br><span>@@ -0,0 +1,133 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pmic_wrap.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+s32 pwrap_reset_spislv(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ret = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 return_value = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->hiprio_arb_en, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->wrap_en, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->mux_sel, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->man_en, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->dio_en, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_CSL << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ /* to reset counter */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_CSH << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * In order to pull CSN signal to PMIC,</span><br><span style="color: hsl(120, 100%, 40%);">+ * PMIC will count it then reset spi slave</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return_value = wait_for_state_ready(wait_for_sync,</span><br><span style="color: hsl(120, 100%, 40%);">+ TIMEOUT_WAIT_IDLE_US,</span><br><span style="color: hsl(120, 100%, 40%);">+ &mtk_pwrap->wacs2_rdata, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (return_value != 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pwrap_err("%s fail,return_value=%#x\n", __func__, return_value);</span><br><span style="color: hsl(120, 100%, 40%);">+ ret = E_PWR_TIMEOUT;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->man_en, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->mux_sel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return ret;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+s32 pwrap_read_nochk(u16 adr, u16 *rdata)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return pwrap_wacs2(0, adr, 0, rdata, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+s32 pwrap_write_nochk(u16 adr, u16 wdata)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return pwrap_wacs2(1, adr, wdata, 0, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg_rdata = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 wacs_write = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 wacs_adr = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 wacs_cmd = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 return_value = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (init_check) {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg_rdata = read32(&mtk_pwrap->wacs2_rdata);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Prevent someone to used pwrap before pwrap init */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) &</span><br><span style="color: hsl(120, 100%, 40%);">+ RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pwrap_err("initialization isn't finished\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return E_PWR_NOT_INIT_DONE;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ reg_rdata = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Check IDLE in advance */</span><br><span style="color: hsl(120, 100%, 40%);">+ return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE_US,</span><br><span style="color: hsl(120, 100%, 40%);">+ &mtk_pwrap->wacs2_rdata,</span><br><span style="color: hsl(120, 100%, 40%);">+ &mtk_pwrap->wacs2_vldclr,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (return_value != 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pwrap_err("wait_for_fsm_idle fail,return_value=%d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ return_value);</span><br><span style="color: hsl(120, 100%, 40%);">+ return E_PWR_WAIT_IDLE_TIMEOUT;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ wacs_write = write << 31;</span><br><span style="color: hsl(120, 100%, 40%);">+ wacs_adr = (adr >> 1) << 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ wacs_cmd = wacs_write | wacs_adr | wdata;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->wacs2_cmd, wacs_cmd);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (write == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (rdata == NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pwrap_err("rdata is a NULL pointer\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return E_PWR_INVALID_ARG;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return_value = wait_for_state_ready(wait_for_fsm_vldclr,</span><br><span style="color: hsl(120, 100%, 40%);">+ TIMEOUT_READ_US,</span><br><span style="color: hsl(120, 100%, 40%);">+ &mtk_pwrap->wacs2_rdata,</span><br><span style="color: hsl(120, 100%, 40%);">+ ®_rdata);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (return_value != 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pwrap_err("wait_for_fsm_vldclr fail,return_value=%d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ return_value);</span><br><span style="color: hsl(120, 100%, 40%);">+ return E_PWR_WAIT_IDLE_TIMEOUT_READ;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ & RDATA_WACS_RDATA_MASK);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->wacs2_vldclr, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* external API for pmic_wrap user */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+s32 pwrap_read(u16 adr, u16 *rdata)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return pwrap_wacs2(0, adr, 0, rdata, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+s32 pwrap_write(u16 adr, u16 wdata)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return pwrap_wacs2(1, adr, wdata, 0, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>index e125e03..b2a5ebd 100644</span><br><span>--- a/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>+++ b/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>@@ -27,7 +27,8 @@</span><br><span> bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c</span><br><span> endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += ../common/gpio.c gpio.c gpio_init.c pmic_wrap.c mt6391.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += ../common/gpio.c gpio.c gpio_init.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c</span><br><span> bootblock-y += ../common/wdt.c</span><br><span> bootblock-y += ../common/mmu_operations.c mmu_operations.c</span><br><span> </span><br><span>@@ -56,7 +57,7 @@</span><br><span> romstage-y += ../common/cbmem.c</span><br><span> romstage-y += ../common/gpio.c gpio.c</span><br><span> romstage-y += ../common/spi.c spi.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += pmic_wrap.c mt6391.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c</span><br><span> romstage-y += memory.c</span><br><span> romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c</span><br><span> romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c</span><br><span>@@ -72,7 +73,7 @@</span><br><span> ramstage-y += ../common/timer.c</span><br><span> ramstage-y += timer.c</span><br><span> ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += pmic_wrap.c mt6391.c i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c i2c.c</span><br><span> ramstage-y += mt6311.c</span><br><span> ramstage-y += da9212.c</span><br><span> ramstage-y += ../common/gpio.c gpio.c</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h</span><br><span>index 6807b13..3687a29 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h</span><br><span>@@ -17,15 +17,10 @@</span><br><span> #define SOC_MEDIATEK_MT8173_PMIC_WRAP_H</span><br><span> </span><br><span> #include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pmic_wrap_common.h></span><br><span> #include <types.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* external API */</span><br><span style="color: hsl(0, 100%, 40%);">-s32 pwrap_read(u16 adr, u16 *rdata);</span><br><span style="color: hsl(0, 100%, 40%);">-s32 pwrap_write(u16 adr, u16 wdata);</span><br><span style="color: hsl(0, 100%, 40%);">-s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check);</span><br><span style="color: hsl(0, 100%, 40%);">-s32 pwrap_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct mt8173_pwrap_regs *const mt8173_pwrap = (void *)PMIC_WRAP_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8173_pwrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;</span><br><span> </span><br><span> enum {</span><br><span> WACS2 = 1 << 4</span><br><span>@@ -44,12 +39,6 @@</span><br><span> PMIC_TOP_CKCON3 = PMIC_BASE + 0x01D4</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* timeout setting */</span><br><span style="color: hsl(0, 100%, 40%);">-enum {</span><br><span style="color: hsl(0, 100%, 40%);">- TIMEOUT_READ_US = 255,</span><br><span style="color: hsl(0, 100%, 40%);">- TIMEOUT_WAIT_IDLE_US = 255</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* PMIC_WRAP registers */</span><br><span> struct mt8173_pwrap_regs {</span><br><span> u32 mux_sel;</span><br><span>@@ -136,36 +125,6 @@</span><br><span> </span><br><span> check_member(mt8173_pwrap_regs, dcm_dbc_prd, 0x148);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-enum {</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_WACS_RDATA_SHIFT = 0,</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_WACS_FSM_SHIFT = 16,</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_WACS_REQ_SHIFT = 19,</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_SYNC_IDLE_SHIFT,</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_INIT_DONE_SHIFT,</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_SYS_IDLE_SHIFT,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-enum {</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_WACS_RDATA_MASK = 0xffff,</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_WACS_FSM_MASK = 0x7,</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_WACS_REQ_MASK = 0x1,</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_SYNC_IDLE_MASK = 0x1,</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_INIT_DONE_MASK = 0x1,</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_SYS_IDLE_MASK = 0x1,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* WACS_FSM */</span><br><span style="color: hsl(0, 100%, 40%);">-enum {</span><br><span style="color: hsl(0, 100%, 40%);">- WACS_FSM_IDLE = 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- WACS_FSM_REQ = 0x02,</span><br><span style="color: hsl(0, 100%, 40%);">- WACS_FSM_WFDLE = 0x04, /* wait for dle, wait for read data done */</span><br><span style="color: hsl(0, 100%, 40%);">- WACS_FSM_WFVLDCLR = 0x06, /* finish read data, wait for valid flag</span><br><span style="color: hsl(0, 100%, 40%);">- * clearing */</span><br><span style="color: hsl(0, 100%, 40%);">- WACS_INIT_DONE = 0x01,</span><br><span style="color: hsl(0, 100%, 40%);">- WACS_SYNC_IDLE = 0x01,</span><br><span style="color: hsl(0, 100%, 40%);">- WACS_SYNC_BUSY = 0x00</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* dewrapper regsister */</span><br><span> enum {</span><br><span> DEW_EVENT_OUT_EN = DEW_BASE + 0x0,</span><br><span>@@ -195,57 +154,10 @@</span><br><span> DEW_CIPHER_IV5 = DEW_BASE + 0x30</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* dewrapper defaule value */</span><br><span style="color: hsl(0, 100%, 40%);">-enum {</span><br><span style="color: hsl(0, 100%, 40%);">- DEFAULT_VALUE_READ_TEST = 0x5aa5,</span><br><span style="color: hsl(0, 100%, 40%);">- WRITE_TEST_VALUE = 0xa55a</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> enum pmic_regck {</span><br><span> REG_CLOCK_18MHZ,</span><br><span> REG_CLOCK_26MHZ,</span><br><span> REG_CLOCK_SAFE_MODE</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* manual commnd */</span><br><span style="color: hsl(0, 100%, 40%);">-enum {</span><br><span style="color: hsl(0, 100%, 40%);">- OP_WR = 0x1,</span><br><span style="color: hsl(0, 100%, 40%);">- OP_CSH = 0x0,</span><br><span style="color: hsl(0, 100%, 40%);">- OP_CSL = 0x1,</span><br><span style="color: hsl(0, 100%, 40%);">- OP_OUTS = 0x8,</span><br><span style="color: hsl(0, 100%, 40%);">- OP_OUTD = 0x9,</span><br><span style="color: hsl(0, 100%, 40%);">- OP_INS = 0xC,</span><br><span style="color: hsl(0, 100%, 40%);">- OP_IND = 0xD</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* error information flag */</span><br><span style="color: hsl(0, 100%, 40%);">-enum {</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INVALID_ARG = 1,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INVALID_RW = 2,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INVALID_ADDR = 3,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INVALID_WDAT = 4,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INVALID_OP_MANUAL = 5,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_NOT_IDLE_STATE = 6,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_NOT_INIT_DONE = 7,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_NOT_INIT_DONE_READ = 8,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_WAIT_IDLE_TIMEOUT = 9,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INIT_SIDLY_FAIL = 11,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_RESET_TIMEOUT = 12,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_TIMEOUT = 13,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INIT_RESET_SPI = 20,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INIT_SIDLY = 21,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INIT_REG_CLOCK = 22,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INIT_ENABLE_PMIC = 23,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INIT_DIO = 24,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INIT_CIPHER = 25,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INIT_WRITE_TEST = 26,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INIT_ENABLE_CRC = 27,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INIT_ENABLE_DEWRAP = 28,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_INIT_ENABLE_EVENT = 29,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_READ_TEST_FAIL = 30,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_WRITE_TEST_FAIL = 31,</span><br><span style="color: hsl(0, 100%, 40%);">- E_PWR_SWITCH_DIO = 32</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #endif /* SOC_MEDIATEK_MT8173_PMIC_WRAP_H */</span><br><span>diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c</span><br><span>index d7d4193..2c60e76 100644</span><br><span>--- a/src/soc/mediatek/mt8173/pmic_wrap.c</span><br><span>+++ b/src/soc/mediatek/mt8173/pmic_wrap.c</span><br><span>@@ -15,183 +15,10 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <assert.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span> #include <delay.h></span><br><span> #include <soc/infracfg.h></span><br><span> #include <soc/pmic_wrap.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <timer.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define PWRAPTAG "[PWRAP] "</span><br><span style="color: hsl(0, 100%, 40%);">-#define pwrap_log(fmt, arg ...) printk(BIOS_INFO, PWRAPTAG fmt, ## arg)</span><br><span style="color: hsl(0, 100%, 40%);">-#define pwrap_err(fmt, arg ...) printk(BIOS_ERR, PWRAPTAG "ERROR,line=%d" fmt, \</span><br><span style="color: hsl(0, 100%, 40%);">- __LINE__, ## arg)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* define macro and inline function (for do while loop) */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-typedef u32 (*loop_condition_fp)(u32);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 wait_for_fsm_vldclr(u32 x)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return ((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=</span><br><span style="color: hsl(0, 100%, 40%);">- WACS_FSM_WFVLDCLR;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 wait_for_sync(u32 x)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return ((x >> RDATA_SYNC_IDLE_SHIFT) & RDATA_SYNC_IDLE_MASK) !=</span><br><span style="color: hsl(0, 100%, 40%);">- WACS_SYNC_IDLE;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 wait_for_idle_and_sync(u32 x)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return ((((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=</span><br><span style="color: hsl(0, 100%, 40%);">- WACS_FSM_IDLE) || (((x >> RDATA_SYNC_IDLE_SHIFT) &</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_SYNC_IDLE_MASK)!= WACS_SYNC_IDLE));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 wait_for_cipher_ready(u32 x)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return x != 3;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 wait_for_state_idle(u32 timeout_us, void *wacs_register,</span><br><span style="color: hsl(0, 100%, 40%);">- void *wacs_vldclr_register,</span><br><span style="color: hsl(0, 100%, 40%);">- u32 *read_reg)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg_rdata;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- struct stopwatch sw;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- stopwatch_init_usecs_expire(&sw, timeout_us);</span><br><span style="color: hsl(0, 100%, 40%);">- do {</span><br><span style="color: hsl(0, 100%, 40%);">- reg_rdata = read32((wacs_register));</span><br><span style="color: hsl(0, 100%, 40%);">- /* if last read command timeout,clear vldclr bit</span><br><span style="color: hsl(0, 100%, 40%);">- read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;</span><br><span style="color: hsl(0, 100%, 40%);">- write:FSM_REQ-->idle */</span><br><span style="color: hsl(0, 100%, 40%);">- switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) &</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_WACS_FSM_MASK)) {</span><br><span style="color: hsl(0, 100%, 40%);">- case WACS_FSM_WFVLDCLR:</span><br><span style="color: hsl(0, 100%, 40%);">- write32(wacs_vldclr_register, 1);</span><br><span style="color: hsl(0, 100%, 40%);">- pwrap_err("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case WACS_FSM_WFDLE:</span><br><span style="color: hsl(0, 100%, 40%);">- pwrap_err("WACS_FSM = WACS_FSM_WFDLE\n");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case WACS_FSM_REQ:</span><br><span style="color: hsl(0, 100%, 40%);">- pwrap_err("WACS_FSM = WACS_FSM_REQ\n");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- default:</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (stopwatch_expired(&sw))</span><br><span style="color: hsl(0, 100%, 40%);">- return E_PWR_WAIT_IDLE_TIMEOUT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- } while (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=</span><br><span style="color: hsl(0, 100%, 40%);">- WACS_FSM_IDLE); /* IDLE State */</span><br><span style="color: hsl(0, 100%, 40%);">- if (read_reg)</span><br><span style="color: hsl(0, 100%, 40%);">- *read_reg = reg_rdata;</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us,</span><br><span style="color: hsl(0, 100%, 40%);">- void *wacs_register, u32 *read_reg)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg_rdata;</span><br><span style="color: hsl(0, 100%, 40%);">- struct stopwatch sw;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- stopwatch_init_usecs_expire(&sw, timeout_us);</span><br><span style="color: hsl(0, 100%, 40%);">- do {</span><br><span style="color: hsl(0, 100%, 40%);">- reg_rdata = read32((wacs_register));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (stopwatch_expired(&sw)) {</span><br><span style="color: hsl(0, 100%, 40%);">- pwrap_err("timeout when waiting for idle\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return E_PWR_WAIT_IDLE_TIMEOUT;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- } while (fp(reg_rdata)); /* IDLE State */</span><br><span style="color: hsl(0, 100%, 40%);">- if (read_reg)</span><br><span style="color: hsl(0, 100%, 40%);">- *read_reg = reg_rdata;</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg_rdata = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 wacs_write = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 wacs_adr = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 wacs_cmd = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 return_value = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (init_check) {</span><br><span style="color: hsl(0, 100%, 40%);">- reg_rdata = read32(&mt8173_pwrap->wacs2_rdata);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Prevent someone to used pwrap before pwrap init */</span><br><span style="color: hsl(0, 100%, 40%);">- if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) &</span><br><span style="color: hsl(0, 100%, 40%);">- RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) {</span><br><span style="color: hsl(0, 100%, 40%);">- pwrap_err("initialization isn't finished\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return E_PWR_NOT_INIT_DONE;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- reg_rdata = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Check IDLE in advance */</span><br><span style="color: hsl(0, 100%, 40%);">- return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE_US,</span><br><span style="color: hsl(0, 100%, 40%);">- &mt8173_pwrap->wacs2_rdata,</span><br><span style="color: hsl(0, 100%, 40%);">- &mt8173_pwrap->wacs2_vldclr,</span><br><span style="color: hsl(0, 100%, 40%);">- 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (return_value != 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- pwrap_err("wait_for_fsm_idle fail,return_value=%d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- return_value);</span><br><span style="color: hsl(0, 100%, 40%);">- return E_PWR_WAIT_IDLE_TIMEOUT;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- wacs_write = write << 31;</span><br><span style="color: hsl(0, 100%, 40%);">- wacs_adr = (adr >> 1) << 16;</span><br><span style="color: hsl(0, 100%, 40%);">- wacs_cmd = wacs_write | wacs_adr | wdata;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->wacs2_cmd, wacs_cmd);</span><br><span style="color: hsl(0, 100%, 40%);">- if (write == 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (NULL == rdata) {</span><br><span style="color: hsl(0, 100%, 40%);">- pwrap_err("rdata is a NULL pointer\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return E_PWR_INVALID_ARG;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- return_value = wait_for_state_ready(wait_for_fsm_vldclr,</span><br><span style="color: hsl(0, 100%, 40%);">- TIMEOUT_READ_US,</span><br><span style="color: hsl(0, 100%, 40%);">- &mt8173_pwrap->wacs2_rdata,</span><br><span style="color: hsl(0, 100%, 40%);">- ®_rdata);</span><br><span style="color: hsl(0, 100%, 40%);">- if (return_value != 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- pwrap_err("wait_for_fsm_vldclr fail,return_value=%d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- return_value);</span><br><span style="color: hsl(0, 100%, 40%);">- return E_PWR_WAIT_IDLE_TIMEOUT_READ;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">- & RDATA_WACS_RDATA_MASK);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->wacs2_vldclr, 1);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* external API for pmic_wrap user */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-s32 pwrap_read(u16 adr, u16 *rdata)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return pwrap_wacs2(0, adr, 0, rdata, 1);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-s32 pwrap_write(u16 adr, u16 wdata)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return pwrap_wacs2(1, adr, wdata, 0, 1);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static s32 pwrap_read_nochk(u16 adr, u16 *rdata)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return pwrap_wacs2(0, adr, 0, rdata, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static s32 pwrap_write_nochk(u16 adr, u16 wdata)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return pwrap_wacs2(1, adr, wdata, 0, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* call it in pwrap_init,mustn't check init done */</span><br><span> static s32 pwrap_init_dio(u32 dio_en)</span><br><span> {</span><br><span> u16 rdata = 0;</span><br><span>@@ -203,13 +30,13 @@</span><br><span> return_value =</span><br><span> wait_for_state_ready(wait_for_idle_and_sync,</span><br><span> TIMEOUT_WAIT_IDLE_US,</span><br><span style="color: hsl(0, 100%, 40%);">- &mt8173_pwrap->wacs2_rdata,</span><br><span style="color: hsl(120, 100%, 40%);">+ &mtk_pwrap->wacs2_rdata,</span><br><span> 0);</span><br><span> if (return_value != 0) {</span><br><span> pwrap_err("%s fail,return_value=%#x\n", __func__, return_value);</span><br><span> return return_value;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->dio_en, dio_en);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->dio_en, dio_en);</span><br><span> /* Read Test */</span><br><span> pwrap_read_nochk(DEW_READ_TEST, &rdata);</span><br><span> if (rdata != DEFAULT_VALUE_READ_TEST) {</span><br><span>@@ -235,7 +62,7 @@</span><br><span> u32 sidly = 0;</span><br><span> </span><br><span> for (i = 0; i < 4; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->sidly, i);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->sidly, i);</span><br><span> pwrap_wacs2(0, DEW_READ_TEST, 0, &rdata, 0);</span><br><span> if (rdata == DEFAULT_VALUE_READ_TEST)</span><br><span> pass |= 1 << i;</span><br><span>@@ -285,49 +112,11 @@</span><br><span> die("sidly pass range not continuous\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->sidly, sidly);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->sidly, sidly);</span><br><span> </span><br><span> return 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static s32 pwrap_reset_spislv(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 ret = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 return_value = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->hiprio_arb_en, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->wrap_en, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->mux_sel, 1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->man_en, 1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->dio_en, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSL << 8));</span><br><span style="color: hsl(0, 100%, 40%);">- /* to reset counter */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSH << 8));</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * In order to pull CSN signal to PMIC,</span><br><span style="color: hsl(0, 100%, 40%);">- * PMIC will count it then reset spi slave</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return_value = wait_for_state_ready(wait_for_sync,</span><br><span style="color: hsl(0, 100%, 40%);">- TIMEOUT_WAIT_IDLE_US,</span><br><span style="color: hsl(0, 100%, 40%);">- &mt8173_pwrap->wacs2_rdata, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (return_value != 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- pwrap_err("%s fail,return_value=%#x\n", __func__, return_value);</span><br><span style="color: hsl(0, 100%, 40%);">- ret = E_PWR_TIMEOUT;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->man_en, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->mux_sel, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return ret;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static s32 pwrap_init_reg_clock(enum pmic_regck regck_sel)</span><br><span> {</span><br><span> u16 wdata = 0;</span><br><span>@@ -350,25 +139,25 @@</span><br><span> /* Config SPI Waveform according to reg clk */</span><br><span> switch (regck_sel) {</span><br><span> case REG_CLOCK_18MHZ:</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->rddmy, 0xc);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->cshext_write, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->cshext_read, 0x4);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->cslext_start, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->cslext_end, 0x4);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->rddmy, 0xc);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->cshext_write, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->cshext_read, 0x4);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->cslext_start, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->cslext_end, 0x4);</span><br><span> break;</span><br><span> case REG_CLOCK_26MHZ:</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->rddmy, 0xc);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->cshext_write, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->cshext_read, 0x4);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->cslext_start, 0x2);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->cslext_end, 0x2);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->rddmy, 0xc);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->cshext_write, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->cshext_read, 0x4);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->cslext_start, 0x2);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->cslext_end, 0x2);</span><br><span> break;</span><br><span> default:</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->rddmy, 0xf);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->cshext_write, 0xf);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->cshext_read, 0xf);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->cslext_start, 0xf);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->cslext_end, 0xf);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->rddmy, 0xf);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->cshext_write, 0xf);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->cshext_read, 0xf);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->cslext_start, 0xf);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->cslext_end, 0xf);</span><br><span> break;</span><br><span> }</span><br><span> </span><br><span>@@ -388,8 +177,8 @@</span><br><span> clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST);</span><br><span> </span><br><span> /* Enable DCM */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->dcm_en, 3);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->dcm_dbc_prd, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->dcm_en, 3);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->dcm_dbc_prd, 0);</span><br><span> </span><br><span> /* Reset SPISLV */</span><br><span> sub_return = pwrap_reset_spislv();</span><br><span>@@ -399,9 +188,9 @@</span><br><span> return E_PWR_INIT_RESET_SPI;</span><br><span> }</span><br><span> /* Enable WACS2 */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->wrap_en, 1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->hiprio_arb_en, WACS2);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->wacs2_en, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->wrap_en, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->hiprio_arb_en, WACS2);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->wacs2_en, 1);</span><br><span> </span><br><span> /* SIDLY setting */</span><br><span> sub_return = pwrap_init_sidly();</span><br><span>@@ -461,14 +250,14 @@</span><br><span> pwrap_err("enable CRC fail,sub_return=%#x\n", sub_return);</span><br><span> return E_PWR_INIT_ENABLE_CRC;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->crc_en, 0x1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->sig_mode, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->sig_adr, DEW_CRC_VAL);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->crc_en, 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->sig_mode, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->sig_adr, DEW_CRC_VAL);</span><br><span> </span><br><span> /* PMIC_WRAP enables */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->hiprio_arb_en, 0x1ff);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->wacs0_en, 0x1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->wacs1_en, 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->hiprio_arb_en, 0x1ff);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->wacs0_en, 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->wacs1_en, 0x1);</span><br><span> </span><br><span> /*</span><br><span> * switch event pin from usbdl mode to normal mode for pmic interrupt,</span><br><span>@@ -481,9 +270,9 @@</span><br><span> sub_return);</span><br><span> </span><br><span> /* Initialization Done */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->init_done2, 0x1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->init_done0, 0x1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_pwrap->init_done1, 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->init_done2, 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->init_done0, 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_pwrap->init_done1, 0x1);</span><br><span> </span><br><span> return 0;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29420">change 29420</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29420"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d </div>
<div style="display:none"> Gerrit-Change-Number: 29420 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>