<p>Frans Hendriks has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29397">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstage<br><br>soc_rtc_init() is executed in ramstage<br>The soc_rtc_init() needs to be executeed before FSP is called. Move the RTC<br>init from ramstage to romstage..<br><br>BUG=N/A<br>TEST=Intel CherryHill CRB<br><br>Change-Id: Ic19c768bf9d9aef7505fb9327e4eedf7212b0057<br>Signed-off-by: Frans Hendriks <fhendriks@eltan.com><br>---<br>M src/soc/intel/braswell/romstage/romstage.c<br>M src/soc/intel/braswell/southcluster.c<br>2 files changed, 21 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/29397/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c</span><br><span>index f485dfd..c777f72 100644</span><br><span>--- a/src/soc/intel/braswell/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/braswell/romstage/romstage.c</span><br><span>@@ -3,6 +3,7 @@</span><br><span> *</span><br><span> * Copyright (C) 2013 Google Inc.</span><br><span> * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Eltan B.V.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -43,6 +44,9 @@</span><br><span> #include <soc/romstage.h></span><br><span> #include <soc/smm.h></span><br><span> #include <soc/spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <build.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <pc80/mc146818rtc.h></span><br><span> </span><br><span> void program_base_addresses(void)</span><br><span> {</span><br><span>@@ -89,6 +93,22 @@</span><br><span> write32(bcr, reg);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_rtc_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int rtc_failed = rtc_failure();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (rtc_failed) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "RTC Failure detected. Resetting Date to %x/%x/%x%x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ COREBOOT_BUILD_MONTH_BCD,</span><br><span style="color: hsl(120, 100%, 40%);">+ COREBOOT_BUILD_DAY_BCD,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20,</span><br><span style="color: hsl(120, 100%, 40%);">+ COREBOOT_BUILD_YEAR_BCD);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cmos_init(rtc_failed);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static struct chipset_power_state power_state CAR_GLOBAL;</span><br><span> </span><br><span> static void migrate_power_state(int is_recovery)</span><br><span>@@ -172,6 +192,7 @@</span><br><span> void car_soc_post_console_init(void)</span><br><span> {</span><br><span> /* Continue chipset initialization */</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_rtc_init();</span><br><span> set_max_freq();</span><br><span> spi_init();</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c</span><br><span>index ca87d63..dd0c78e 100644</span><br><span>--- a/src/soc/intel/braswell/southcluster.c</span><br><span>+++ b/src/soc/intel/braswell/southcluster.c</span><br><span>@@ -26,7 +26,6 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/mc146818rtc.h></span><br><span> #include <romstage_handoff.h></span><br><span> #include <soc/acpi.h></span><br><span> #include <soc/iomap.h></span><br><span>@@ -149,12 +148,6 @@</span><br><span> sc_add_io_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_rtc_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__);</span><br><span style="color: hsl(0, 100%, 40%);">- cmos_init(rtc_failure());</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void sc_init(struct device *dev)</span><br><span> {</span><br><span> int i;</span><br><span>@@ -181,8 +174,6 @@</span><br><span> /* Route SCI to IRQ9 */</span><br><span> write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- sc_rtc_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> if (config->disable_slp_x_stretch_sus_fail) {</span><br><span> printk(BIOS_DEBUG, "Disabling slp_x stretching.\n");</span><br><span> write32(gen_pmcon1,</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29397">change 29397</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic19c768bf9d9aef7505fb9327e4eedf7212b0057 </div>
<div style="display:none"> Gerrit-Change-Number: 29397 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Frans Hendriks <fhendriks@eltan.com> </div>