<p>Tristan Corrick has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29387">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/lynxpoint: Generate the ACPI FADT with a common function<br><br>The function `acpi_fill_fadt()` is based on that of sb/intel/bd82x6x.<br><br>Tested on an ASRock H81M-HDS and a Google Peppy board, both using Linux<br>4.9 with `acpi=strict`. No ACPI errors or warnings appear in the kernel<br>log. System reset, poweroff, and S3 suspend/resume continue to work.<br><br>General improvements<br>--------------------<br><br>- `fadt->preferred_pm_profile` is set based on the value of<br> `CONFIG_SYSTEM_TYPE_LAPTOP` instead of being hardcoded.<br><br>- Constants are used instead of magic values in more locations.<br><br>- `fadt->gpe0_blk`, `fadt->gpe0_blk_len`, and `fadt->x_gpe0_blk` are set<br> appropriately depending on whether the system uses Lynx Point LP or<br> not.<br><br>- The C2 and C3 latencies can be set in the devicetree. If unset, the<br> FADT will indicate that the C-state is unsupported.<br><br>- Boards can indicate docking support in the FADT via the devicetree.<br><br>Changes to existing Lynx Point boards<br>-------------------------------------<br><br>- `header->asl_compiler_revision` changes from 1 to 0.<br><br>- `fadt->model` is left at 0 instead of being set to 1. This field is<br> only needed for ACPI 1.0 compatibility.<br><br>- `fadt->flush_size` and `fadt->flush_stride` are set to 0. This is<br> because their values are ignored, since `ACPI_FADT_WBINVD` is set in<br> `fadt->flags`.<br><br>- `fadt->duty_offset` is set to 0 instead of 1. None of the existing<br> boards indicate support for changing the processor duty cycle (as<br> `fadt->duty_width` is set to 0), so `fadt->duty_offset` does not<br> currently need to be set.<br><br>- Access sizes of registers are set.<br><br>- On mb/intel/baskingridge, the pmbase is now read using the common<br> function `get_pmbase()` instead of `pci_read_config16(...)`.<br><br>- On mb/intel/baskingridge, the value of `fadt->x_gpe0_blk.bit_width`<br> changes from 64 to 128. The correct value should be 128 (bits), to<br> match `fadt->gpe0_blk_len`, which is set to 16 (bytes).<br><br>- On Lynx Point LP systems, the unused extended address<br> `fadt->x_gpe0_blk` sets its address space ID to be consistent with<br> other unused extended addresses. Such a change should not alter the<br> interpretation of the registers as being unused. Why not set them all<br> to zero? Simply because the existing practice, in both coreboot and<br> some other vendors' firmware, has them set in such a case.<br><br>A diff of the FADT from a Google Peppy board is below:<br><br>--- pre/facp.dsl 2018-10-30 20:14:52.676570798 +1300<br>+++ post/facp.dsl 2018-10-30 20:15:06.904381436 +1300<br>@@ -1,179 +1,179 @@<br> /*<br> * Intel ACPI Component Architecture<br> * AML/ASL+ Disassembler version 20180810 (64-bit version)<br> * Copyright (c) 2000 - 2018 Intel Corporation<br> *<br>- * Disassembly of facp.dat, Tue Oct 30 20:14:52 2018<br>+ * Disassembly of facp.dat, Tue Oct 30 20:15:06 2018<br> *<br> * ACPI Data Table [FACP]<br> *<br> * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue<br> */<br><br> [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]<br> [004h 0004 4] Table Length : 000000F4<br> [008h 0008 1] Revision : 04<br>-[009h 0009 1] Checksum : 61<br>+[009h 0009 1] Checksum : 6E<br> [00Ah 0010 6] Oem ID : "CORE "<br> [010h 0016 8] Oem Table ID : "COREBOOT"<br> [018h 0024 4] Oem Revision : 00000000<br> [01Ch 0028 4] Asl Compiler ID : "CORE"<br>-[020h 0032 4] Asl Compiler Revision : 00000001<br>+[020h 0032 4] Asl Compiler Revision : 00000000<br><br> [024h 0036 4] FACS Address : 7BF46240<br> [028h 0040 4] DSDT Address : 7BF46280<br>-[02Ch 0044 1] Model : 01<br>+[02Ch 0044 1] Model : 00<br> [02Dh 0045 1] PM Profile : 02 [Mobile]<br> [02Eh 0046 2] SCI Interrupt : 0009<br> [030h 0048 4] SMI Command Port : 000000B2<br> [034h 0052 1] ACPI Enable Value : E1<br> [035h 0053 1] ACPI Disable Value : 1E<br> [036h 0054 1] S4BIOS Command : 00<br> [037h 0055 1] P-State Control : 00<br> [038h 0056 4] PM1A Event Block Address : 00001000<br> [03Ch 0060 4] PM1B Event Block Address : 00000000<br> [040h 0064 4] PM1A Control Block Address : 00001004<br> [044h 0068 4] PM1B Control Block Address : 00000000<br> [048h 0072 4] PM2 Control Block Address : 00001050<br> [04Ch 0076 4] PM Timer Block Address : 00001008<br> [050h 0080 4] GPE0 Block Address : 00001080<br> [054h 0084 4] GPE1 Block Address : 00000000<br> [058h 0088 1] PM1 Event Block Length : 04<br> [059h 0089 1] PM1 Control Block Length : 02<br> [05Ah 0090 1] PM2 Control Block Length : 01<br> [05Bh 0091 1] PM Timer Block Length : 04<br> [05Ch 0092 1] GPE0 Block Length : 20<br> [05Dh 0093 1] GPE1 Block Length : 00<br> [05Eh 0094 1] GPE1 Base Offset : 00<br> [05Fh 0095 1] _CST Support : 00<br> [060h 0096 2] C2 Latency : 0001<br> [062h 0098 2] C3 Latency : 0057<br>-[064h 0100 2] CPU Cache Size : 0400<br>-[066h 0102 2] Cache Flush Stride : 0010<br>-[068h 0104 1] Duty Cycle Offset : 01<br>+[064h 0100 2] CPU Cache Size : 0000<br>+[066h 0102 2] Cache Flush Stride : 0000<br>+[068h 0104 1] Duty Cycle Offset : 00<br> [069h 0105 1] Duty Cycle Width : 00<br> [06Ah 0106 1] RTC Day Alarm Index : 0D<br> [06Bh 0107 1] RTC Month Alarm Index : 00<br> [06Ch 0108 1] RTC Century Index : 00<br> [06Dh 0109 2] Boot Flags (decoded below) : 0003<br> Legacy Devices Supported (V2) : 1<br> 8042 Present on ports 60/64 (V2) : 1<br> VGA Not Present (V4) : 0<br> MSI Not Supported (V4) : 0<br> PCIe ASPM Not Supported (V4) : 0<br> CMOS RTC Not Present (V5) : 0<br> [06Fh 0111 1] Reserved : 00<br> [070h 0112 4] Flags (decoded below) : 00008CAD<br> WBINVD instruction is operational (V1) : 1<br> WBINVD flushes all caches (V1) : 0<br> All CPUs support C1 (V1) : 1<br> C2 works on MP system (V1) : 1<br> Control Method Power Button (V1) : 0<br> Control Method Sleep Button (V1) : 1<br> RTC wake not in fixed reg space (V1) : 0<br> RTC can wake system from S4 (V1) : 1<br> 32-bit PM Timer (V1) : 0<br> Docking Supported (V1) : 0<br> Reset Register Supported (V2) : 1<br> Sealed Case (V3) : 1<br> Headless - No Video (V3) : 0<br> Use native instr after SLP_TYPx (V3) : 0<br> PCIEXP_WAK Bits Supported (V4) : 0<br> Use Platform Timer (V4) : 1<br> RTC_STS valid on S4 wake (V4) : 0<br> Remote Power-on capable (V4) : 0<br> Use APIC Cluster Model (V4) : 0<br> Use APIC Physical Destination Mode (V4) : 0<br> Hardware Reduced (V5) : 0<br> Low Power S0 Idle (V5) : 0<br><br> [074h 0116 12] Reset Register : [Generic Address Structure]<br> [074h 0116 1] Space ID : 01 [SystemIO]<br> [075h 0117 1] Bit Width : 08<br> [076h 0118 1] Bit Offset : 00<br>-[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]<br>+[077h 0119 1] Encoded Access Width : 01 [Byte Access:8]<br> [078h 0120 8] Address : 0000000000000CF9<br><br> [080h 0128 1] Value to cause reset : 06<br> [081h 0129 2] ARM Flags (decoded below) : 0000<br> PSCI Compliant : 0<br> Must use HVC for PSCI : 0<br><br> [083h 0131 1] FADT Minor Revision : 00<br> [084h 0132 8] FACS Address : 000000007BF46240<br> [08Ch 0140 8] DSDT Address : 000000007BF46280<br> [094h 0148 12] PM1A Event Block : [Generic Address Structure]<br> [094h 0148 1] Space ID : 01 [SystemIO]<br> [095h 0149 1] Bit Width : 20<br> [096h 0150 1] Bit Offset : 00<br>-[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]<br>+[097h 0151 1] Encoded Access Width : 02 [Word Access:16]<br> [098h 0152 8] Address : 0000000000001000<br><br> [0A0h 0160 12] PM1B Event Block : [Generic Address Structure]<br> [0A0h 0160 1] Space ID : 01 [SystemIO]<br> [0A1h 0161 1] Bit Width : 00<br> [0A2h 0162 1] Bit Offset : 00<br> [0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]<br> [0A4h 0164 8] Address : 0000000000000000<br><br> [0ACh 0172 12] PM1A Control Block : [Generic Address Structure]<br> [0ACh 0172 1] Space ID : 01 [SystemIO]<br> [0ADh 0173 1] Bit Width : 10<br> [0AEh 0174 1] Bit Offset : 00<br>-[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]<br>+[0AFh 0175 1] Encoded Access Width : 02 [Word Access:16]<br> [0B0h 0176 8] Address : 0000000000001004<br><br> [0B8h 0184 12] PM1B Control Block : [Generic Address Structure]<br> [0B8h 0184 1] Space ID : 01 [SystemIO]<br> [0B9h 0185 1] Bit Width : 00<br> [0BAh 0186 1] Bit Offset : 00<br> [0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]<br> [0BCh 0188 8] Address : 0000000000000000<br><br> [0C4h 0196 12] PM2 Control Block : [Generic Address Structure]<br> [0C4h 0196 1] Space ID : 01 [SystemIO]<br> [0C5h 0197 1] Bit Width : 08<br> [0C6h 0198 1] Bit Offset : 00<br>-[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]<br>+[0C7h 0199 1] Encoded Access Width : 01 [Byte Access:8]<br> [0C8h 0200 8] Address : 0000000000001050<br><br> [0D0h 0208 12] PM Timer Block : [Generic Address Structure]<br> [0D0h 0208 1] Space ID : 01 [SystemIO]<br> [0D1h 0209 1] Bit Width : 20<br> [0D2h 0210 1] Bit Offset : 00<br>-[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]<br>+[0D3h 0211 1] Encoded Access Width : 03 [DWord Access:32]<br> [0D4h 0212 8] Address : 0000000000001008<br><br> [0DCh 0220 12] GPE0 Block : [Generic Address Structure]<br>-[0DCh 0220 1] Space ID : 00 [SystemMemory]<br>+[0DCh 0220 1] Space ID : 01 [SystemIO]<br> [0DDh 0221 1] Bit Width : 00<br> [0DEh 0222 1] Bit Offset : 00<br> [0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]<br> [0E0h 0224 8] Address : 0000000000000000<br><br> [0E8h 0232 12] GPE1 Block : [Generic Address Structure]<br> [0E8h 0232 1] Space ID : 01 [SystemIO]<br> [0E9h 0233 1] Bit Width : 00<br> [0EAh 0234 1] Bit Offset : 00<br> [0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]<br> [0ECh 0236 8] Address : 0000000000000000<br><br> Raw Table Data: Length 244 (0xF4)<br><br>- 0000: 46 41 43 50 F4 00 00 00 04 61 43 4F 52 45 20 20 // FACP.....aCORE<br>+ 0000: 46 41 43 50 F4 00 00 00 04 6E 43 4F 52 45 20 20 // FACP.....nCORE<br> 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE<br>- 0020: 01 00 00 00 40 62 F4 7B 80 62 F4 7B 01 02 09 00 // ....@b.{.b.{....<br>+ 0020: 00 00 00 00 40 62 F4 7B 80 62 F4 7B 00 02 09 00 // ....@b.{.b.{....<br> 0030: B2 00 00 00 E1 1E 00 00 00 10 00 00 00 00 00 00 // ................<br> 0040: 04 10 00 00 00 00 00 00 50 10 00 00 08 10 00 00 // ........P.......<br> 0050: 80 10 00 00 00 00 00 00 04 02 01 04 20 00 00 00 // ............ ...<br>- 0060: 01 00 57 00 00 04 10 00 01 00 0D 00 00 03 00 00 // ..W.............<br>- 0070: AD 8C 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................<br>+ 0060: 01 00 57 00 00 00 00 00 00 00 0D 00 00 03 00 00 // ..W.............<br>+ 0070: AD 8C 00 00 01 08 00 01 F9 0C 00 00 00 00 00 00 // ................<br> 0080: 06 00 00 00 40 62 F4 7B 00 00 00 00 80 62 F4 7B // ....@b.{.....b.{<br>- 0090: 00 00 00 00 01 20 00 00 00 10 00 00 00 00 00 00 // ..... ..........<br>- 00A0: 01 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................<br>+ 0090: 00 00 00 00 01 20 00 02 00 10 00 00 00 00 00 00 // ..... ..........<br>+ 00A0: 01 00 00 00 00 00 00 00 00 00 00 00 01 10 00 02 // ................<br> 00B0: 04 10 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................<br>- 00C0: 00 00 00 00 01 08 00 00 50 10 00 00 00 00 00 00 // ........P.......<br>- 00D0: 01 20 00 00 08 10 00 00 00 00 00 00 00 00 00 00 // . ..............<br>+ 00C0: 00 00 00 00 01 08 00 01 50 10 00 00 00 00 00 00 // ........P.......<br>+ 00D0: 01 20 00 03 08 10 00 00 00 00 00 00 01 00 00 00 // . ..............<br> 00E0: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................<br> 00F0: 00 00 00 00 // ....<br><br>Change-Id: I9638bb5ff998518eb750e3e7e85b51cdaf1f070e<br>Signed-off-by: Tristan Corrick <tristan@corrick.kiwi><br>---<br>M src/mainboard/google/beltino/devicetree.cb<br>D src/mainboard/google/beltino/fadt.c<br>D src/mainboard/google/slippy/fadt.c<br>M src/mainboard/google/slippy/variants/falco/devicetree.cb<br>M src/mainboard/google/slippy/variants/leon/devicetree.cb<br>M src/mainboard/google/slippy/variants/peppy/devicetree.cb<br>M src/mainboard/google/slippy/variants/wolf/devicetree.cb<br>M src/mainboard/intel/baskingridge/devicetree.cb<br>D src/mainboard/intel/baskingridge/fadt.c<br>M src/southbridge/intel/lynxpoint/Kconfig<br>M src/southbridge/intel/lynxpoint/chip.h<br>M src/southbridge/intel/lynxpoint/lpc.c<br>12 files changed, 172 insertions(+), 453 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/29387/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb</span><br><span>index 89758dd..1c8c356 100644</span><br><span>--- a/src/mainboard/google/beltino/devicetree.cb</span><br><span>+++ b/src/mainboard/google/beltino/devicetree.cb</span><br><span>@@ -71,6 +71,9 @@</span><br><span> # Route all USB ports to XHCI per default</span><br><span> register "xhci_default" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_latency" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_latency" = "87"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> device pci 13.0 off end # Smart Sound Audio DSP</span><br><span> device pci 14.0 on end # USB3 XHCI</span><br><span> device pci 15.0 off end # Serial I/O DMA</span><br><span>diff --git a/src/mainboard/google/beltino/fadt.c b/src/mainboard/google/beltino/fadt.c</span><br><span>deleted file mode 100644</span><br><span>index 5c2cafd..0000000</span><br><span>--- a/src/mainboard/google/beltino/fadt.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,151 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/lynxpoint/pch.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- acpi_header_t *header = &(fadt->header);</span><br><span style="color: hsl(0, 100%, 40%);">- u16 pmbase = get_pmbase();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- memset((void *) fadt, 0, sizeof(acpi_fadt_t));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(header->signature, "FACP", 4);</span><br><span style="color: hsl(0, 100%, 40%);">- header->length = sizeof(acpi_fadt_t);</span><br><span style="color: hsl(0, 100%, 40%);">- header->revision = get_acpi_table_revision(FADT);</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(header->oem_id, OEM_ID, 6);</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(header->asl_compiler_id, ASLC, 4);</span><br><span style="color: hsl(0, 100%, 40%);">- header->asl_compiler_revision = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->firmware_ctrl = (unsigned long) facs;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->dsdt = (unsigned long) dsdt;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->model = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->preferred_pm_profile = PM_MOBILE;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->sci_int = 0x9;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->smi_cmd = APM_CNT;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->acpi_enable = APM_CNT_ACPI_ENABLE;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->acpi_disable = APM_CNT_ACPI_DISABLE;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->s4bios_req = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pstate_cnt = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1a_evt_blk = pmbase;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1b_evt_blk = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1a_cnt_blk = pmbase + 0x4;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1b_cnt_blk = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm2_cnt_blk = pmbase + 0x50;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm_tmr_blk = pmbase + 0x8;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe0_blk = pmbase + 0x80;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe1_blk = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1_evt_len = 4;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1_cnt_len = 2;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm2_cnt_len = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm_tmr_len = 4;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe0_blk_len = 32;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe1_blk_len = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe1_base = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->cst_cnt = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->p_lvl2_lat = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->p_lvl3_lat = 87;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->flush_size = 1024;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->flush_stride = 16;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->duty_offset = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->duty_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->day_alrm = 0xd;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->mon_alrm = 0x00;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->century = 0x00;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |</span><br><span style="color: hsl(0, 100%, 40%);">- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |</span><br><span style="color: hsl(0, 100%, 40%);">- ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |</span><br><span style="color: hsl(0, 100%, 40%);">- ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.bit_width = 8;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.addrl = 0xcf9;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.addrh = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_value = 6;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_firmware_ctl_l = (unsigned long)facs;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_firmware_ctl_h = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_dsdt_l = (unsigned long)dsdt;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_dsdt_h = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.bit_width = 32;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.addrl = pmbase;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.bit_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.addrl = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.bit_width = 16;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.bit_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.addrl = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.bit_width = 8;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.bit_width = 32;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.space_id = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.bit_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.addrl = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.bit_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.addrl = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- header->checksum = acpi_checksum((void *) fadt, header->length);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/slippy/fadt.c b/src/mainboard/google/slippy/fadt.c</span><br><span>deleted file mode 100644</span><br><span>index 52a099f..0000000</span><br><span>--- a/src/mainboard/google/slippy/fadt.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,151 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/lynxpoint/pch.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- acpi_header_t *header = &(fadt->header);</span><br><span style="color: hsl(0, 100%, 40%);">- u16 pmbase = get_pmbase();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- memset((void *) fadt, 0, sizeof(acpi_fadt_t));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(header->signature, "FACP", 4);</span><br><span style="color: hsl(0, 100%, 40%);">- header->length = sizeof(acpi_fadt_t);</span><br><span style="color: hsl(0, 100%, 40%);">- header->revision = get_acpi_table_revision(FADT);</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(header->oem_id, OEM_ID, 6);</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(header->asl_compiler_id, ASLC, 4);</span><br><span style="color: hsl(0, 100%, 40%);">- header->asl_compiler_revision = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->firmware_ctrl = (unsigned long) facs;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->dsdt = (unsigned long) dsdt;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->model = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->preferred_pm_profile = PM_MOBILE;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->sci_int = 0x9;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->smi_cmd = APM_CNT;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->acpi_enable = APM_CNT_ACPI_ENABLE;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->acpi_disable = APM_CNT_ACPI_DISABLE;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->s4bios_req = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pstate_cnt = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1a_evt_blk = pmbase;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1b_evt_blk = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1a_cnt_blk = pmbase + 0x4;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1b_cnt_blk = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm2_cnt_blk = pmbase + 0x50;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm_tmr_blk = pmbase + 0x8;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe0_blk = pmbase + 0x80;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe1_blk = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1_evt_len = 4;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1_cnt_len = 2;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm2_cnt_len = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm_tmr_len = 4;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe0_blk_len = 32;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe1_blk_len = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe1_base = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->cst_cnt = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->p_lvl2_lat = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->p_lvl3_lat = 87;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->flush_size = 1024;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->flush_stride = 16;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->duty_offset = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->duty_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->day_alrm = 0xd;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->mon_alrm = 0x00;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->century = 0x00;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |</span><br><span style="color: hsl(0, 100%, 40%);">- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |</span><br><span style="color: hsl(0, 100%, 40%);">- ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |</span><br><span style="color: hsl(0, 100%, 40%);">- ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.bit_width = 8;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.addrl = 0xcf9;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.addrh = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_value = 6;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_firmware_ctl_l = (unsigned long)facs;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_firmware_ctl_h = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_dsdt_l = (unsigned long)dsdt;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_dsdt_h = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.bit_width = 32;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.addrl = pmbase;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.bit_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.addrl = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.bit_width = 16;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.bit_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.addrl = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.bit_width = 8;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.bit_width = 32;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.space_id = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.bit_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.addrl = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.bit_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.addrl = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- header->checksum = acpi_checksum((void *) fadt, header->length);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/variants/falco/devicetree.cb</span><br><span>index f2a9520..3cfe4be 100644</span><br><span>--- a/src/mainboard/google/slippy/variants/falco/devicetree.cb</span><br><span>+++ b/src/mainboard/google/slippy/variants/falco/devicetree.cb</span><br><span>@@ -84,6 +84,9 @@</span><br><span> # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP</span><br><span> register "icc_clock_disable" = "0x013e0000"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_latency" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_latency" = "87"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> device pci 13.0 off end # Smart Sound Audio DSP</span><br><span> device pci 14.0 on end # USB3 XHCI</span><br><span> device pci 15.0 on end # Serial I/O DMA</span><br><span>diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb</span><br><span>index 8951e99..0aa92b7 100644</span><br><span>--- a/src/mainboard/google/slippy/variants/leon/devicetree.cb</span><br><span>+++ b/src/mainboard/google/slippy/variants/leon/devicetree.cb</span><br><span>@@ -89,6 +89,9 @@</span><br><span> # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP</span><br><span> register "icc_clock_disable" = "0x013c0000"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_latency" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_latency" = "87"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> device pci 13.0 off end # Smart Sound Audio DSP</span><br><span> device pci 14.0 on end # USB3 XHCI</span><br><span> device pci 15.0 on end # Serial I/O DMA</span><br><span>diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb</span><br><span>index 6451d95..a6c4b95 100644</span><br><span>--- a/src/mainboard/google/slippy/variants/peppy/devicetree.cb</span><br><span>+++ b/src/mainboard/google/slippy/variants/peppy/devicetree.cb</span><br><span>@@ -88,6 +88,9 @@</span><br><span> # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP</span><br><span> register "icc_clock_disable" = "0x013c0000"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_latency" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_latency" = "87"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> device pci 13.0 off end # Smart Sound Audio DSP</span><br><span> device pci 14.0 on end # USB3 XHCI</span><br><span> device pci 15.0 on end # Serial I/O DMA</span><br><span>diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb</span><br><span>index 2cad23b..9cdb59a 100644</span><br><span>--- a/src/mainboard/google/slippy/variants/wolf/devicetree.cb</span><br><span>+++ b/src/mainboard/google/slippy/variants/wolf/devicetree.cb</span><br><span>@@ -89,6 +89,9 @@</span><br><span> # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP</span><br><span> register "icc_clock_disable" = "0x013c0000"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_latency" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_latency" = "87"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> device pci 13.0 off end # Smart Sound Audio DSP</span><br><span> device pci 14.0 on end # USB3 XHCI</span><br><span> device pci 15.0 on end # Serial I/O DMA</span><br><span>diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb</span><br><span>index a9cfb49..8d5e799 100644</span><br><span>--- a/src/mainboard/intel/baskingridge/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/baskingridge/devicetree.cb</span><br><span>@@ -58,6 +58,9 @@</span><br><span> # SuperIO range is 0x700-0x73f</span><br><span> register "gen2_dec" = "0x003c0701"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_latency" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_latency" = "87"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> device pci 16.0 on end # Management Engine Interface 1</span><br><span> device pci 16.1 off end # Management Engine Interface 2</span><br><span> device pci 16.2 off end # Management Engine IDE-R</span><br><span>diff --git a/src/mainboard/intel/baskingridge/fadt.c b/src/mainboard/intel/baskingridge/fadt.c</span><br><span>deleted file mode 100644</span><br><span>index 54e95f8..0000000</span><br><span>--- a/src/mainboard/intel/baskingridge/fadt.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,151 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- acpi_header_t *header = &(fadt->header);</span><br><span style="color: hsl(0, 100%, 40%);">- u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),</span><br><span style="color: hsl(0, 100%, 40%);">- 0x40) & 0xfffe;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- memset((void *) fadt, 0, sizeof(acpi_fadt_t));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(header->signature, "FACP", 4);</span><br><span style="color: hsl(0, 100%, 40%);">- header->length = sizeof(acpi_fadt_t);</span><br><span style="color: hsl(0, 100%, 40%);">- header->revision = 3;</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(header->oem_id, OEM_ID, 6);</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(header->asl_compiler_id, ASLC, 4);</span><br><span style="color: hsl(0, 100%, 40%);">- header->asl_compiler_revision = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->firmware_ctrl = (unsigned long) facs;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->dsdt = (unsigned long) dsdt;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->model = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->preferred_pm_profile = PM_DESKTOP;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->sci_int = 0x9;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->smi_cmd = APM_CNT;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->acpi_enable = APM_CNT_ACPI_ENABLE;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->acpi_disable = APM_CNT_ACPI_DISABLE;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->s4bios_req = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pstate_cnt = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1a_evt_blk = pmbase;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1b_evt_blk = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1a_cnt_blk = pmbase + 0x4;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1b_cnt_blk = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm2_cnt_blk = pmbase + 0x50;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm_tmr_blk = pmbase + 0x8;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe0_blk = pmbase + 0x20;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe1_blk = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1_evt_len = 4;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm1_cnt_len = 2;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm2_cnt_len = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->pm_tmr_len = 4;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe0_blk_len = 16;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe1_blk_len = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe1_base = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->cst_cnt = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->p_lvl2_lat = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->p_lvl3_lat = 87;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->flush_size = 1024;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->flush_stride = 16;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->duty_offset = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->duty_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->day_alrm = 0xd;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->mon_alrm = 0x00;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->century = 0x00;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |</span><br><span style="color: hsl(0, 100%, 40%);">- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |</span><br><span style="color: hsl(0, 100%, 40%);">- ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |</span><br><span style="color: hsl(0, 100%, 40%);">- ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.bit_width = 8;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.addrl = 0xcf9;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_reg.addrh = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->reset_value = 6;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_firmware_ctl_l = (unsigned long)facs;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_firmware_ctl_h = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_dsdt_l = (unsigned long)dsdt;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_dsdt_h = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.bit_width = 32;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.addrl = pmbase;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_evt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.bit_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.addrl = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_evt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.bit_width = 16;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1a_cnt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.bit_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.addrl = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm1b_cnt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.bit_width = 8;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm2_cnt_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.bit_width = 32;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_pm_tmr_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.bit_width = 64;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.addrl = pmbase + 0x20;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe0_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.bit_width = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.addrl = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->x_gpe1_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- header->checksum = acpi_checksum((void *) fadt, header->length);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig</span><br><span>index 1e088c1..5837d6d 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/Kconfig</span><br><span>+++ b/src/southbridge/intel/lynxpoint/Kconfig</span><br><span>@@ -35,6 +35,7 @@</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ</span><br><span> select HAVE_INTEL_CHIPSET_LOCKDOWN</span><br><span style="color: hsl(120, 100%, 40%);">+ select COMMON_FADT</span><br><span> </span><br><span> config INTEL_LYNXPOINT_LP</span><br><span> bool</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h</span><br><span>index d11ce5f..f0f0383 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/chip.h</span><br><span>+++ b/src/southbridge/intel/lynxpoint/chip.h</span><br><span>@@ -110,6 +110,11 @@</span><br><span> </span><br><span> /* Route USB ports to XHCI per default */</span><br><span> uint8_t xhci_default;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Information for the ACPI FADT. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t c2_latency;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t c3_latency;</span><br><span style="color: hsl(120, 100%, 40%);">+ bool docking_supported;</span><br><span> };</span><br><span> </span><br><span> extern struct chip_operations southbridge_intel_lynxpoint_ops;</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>index cf5959e..6d29480 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>@@ -790,6 +790,154 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_fill_fadt(acpi_fadt_t *fadt)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 c2_latency = cfg->c2_latency;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 c3_latency = cfg->c3_latency;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 pmbase = get_pmbase();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->sci_int = 0x9;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->smi_cmd = APM_CNT;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->s4bios_req = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->pstate_cnt = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->pm1a_evt_blk = pmbase + PM1_STS;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->pm1b_evt_blk = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->pm1a_cnt_blk = pmbase + PM1_CNT;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->pm1b_cnt_blk = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->pm2_cnt_blk = pmbase + PM2_CNT;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->pm_tmr_blk = pmbase + PM1_TMR;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pch_is_lp())</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->gpe0_blk = pmbase + LP_GPE0_STS_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->gpe0_blk = pmbase + GPE0_STS;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->gpe1_blk = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Some of the lengths here are doubled. This is because they describe</span><br><span style="color: hsl(120, 100%, 40%);">+ * blocks containing two registers, where the size of each register</span><br><span style="color: hsl(120, 100%, 40%);">+ * is found by halving the block length. See Table 5-34 and section</span><br><span style="color: hsl(120, 100%, 40%);">+ * 4.8.3 of the ACPI specification for details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->pm1_evt_len = 2 * 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->pm1_cnt_len = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->pm2_cnt_len = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->pm_tmr_len = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pch_is_lp())</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->gpe0_blk_len = 2 * 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->gpe0_blk_len = 2 * 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->gpe1_blk_len = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->gpe1_base = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->cst_cnt = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->p_lvl2_lat = c2_latency ? c2_latency : ACPI_FADT_C2_NOT_SUPPORTED;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->p_lvl3_lat = c3_latency ? c3_latency : ACPI_FADT_C3_NOT_SUPPORTED;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->flush_size = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->flush_stride = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->duty_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->duty_width = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->day_alrm = 0xd;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->mon_alrm = 0x00;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->century = 0x00;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->flags = ACPI_FADT_WBINVD |</span><br><span style="color: hsl(120, 100%, 40%);">+ ACPI_FADT_C1_SUPPORTED |</span><br><span style="color: hsl(120, 100%, 40%);">+ ACPI_FADT_C2_MP_SUPPORTED |</span><br><span style="color: hsl(120, 100%, 40%);">+ ACPI_FADT_SLEEP_BUTTON |</span><br><span style="color: hsl(120, 100%, 40%);">+ ACPI_FADT_RESET_REGISTER |</span><br><span style="color: hsl(120, 100%, 40%);">+ ACPI_FADT_SEALED_CASE |</span><br><span style="color: hsl(120, 100%, 40%);">+ ACPI_FADT_S4_RTC_WAKE |</span><br><span style="color: hsl(120, 100%, 40%);">+ ACPI_FADT_PLATFORM_CLOCK;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cfg->docking_supported)</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->reset_reg.bit_width = 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->reset_reg.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->reset_reg.addrl = 0xcf9;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->reset_reg.addrh = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->reset_value = 6;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1a_evt_blk.bit_width = 2 * 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1a_evt_blk.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1a_evt_blk.addrh = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1b_evt_blk.bit_width = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1b_evt_blk.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1b_evt_blk.access_size = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1b_evt_blk.addrl = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1b_evt_blk.addrh = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1a_cnt_blk.bit_width = 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1a_cnt_blk.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1a_cnt_blk.addrh = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1b_cnt_blk.bit_width = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1b_cnt_blk.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1b_cnt_blk.access_size = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1b_cnt_blk.addrl = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm1b_cnt_blk.addrh = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm2_cnt_blk.bit_width = 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm2_cnt_blk.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm2_cnt_blk.addrh = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm_tmr_blk.bit_width = 32;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm_tmr_blk.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm_tmr_blk.addrh = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * We don't set `fadt->x_gpe0_blk` for Lynx Point LP since the correct</span><br><span style="color: hsl(120, 100%, 40%);">+ * bit width is 128 * 2, which is too large for an 8 bit unsigned int.</span><br><span style="color: hsl(120, 100%, 40%);">+ * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!pch_is_lp()) {</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe0_blk.bit_width = 2 * 64;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe0_blk.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe0_blk.addrh = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe0_blk.bit_width = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe0_blk.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe0_blk.access_size = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe0_blk.addrl = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe0_blk.addrh = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe1_blk.bit_width = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe1_blk.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe1_blk.access_size = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe1_blk.addrl = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_gpe1_blk.addrh = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static const char *lpc_acpi_name(const struct device *dev)</span><br><span> {</span><br><span> return "LPCB";</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29387">change 29387</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29387"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9638bb5ff998518eb750e3e7e85b51cdaf1f070e </div>
<div style="display:none"> Gerrit-Change-Number: 29387 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Corrick <tristan@corrick.kiwi> </div>