<p>Frans Hendriks has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29398">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc/intel/braswell/southcluster.c: Correct serail IRQ support<br><br>Serial IRQ was configured in quiet mode, but not enabled.<br>Enable serial IRQ when requested and make quiet mode configurable.<br><br>BUG=N/A<br>TEST=Intel CherryHill CRB<br><br>Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245<br>Signed-off-by: Frans Hendriks <fhendriks@eltan.com><br>---<br>M src/soc/intel/braswell/Kconfig<br>M src/soc/intel/braswell/southcluster.c<br>2 files changed, 27 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/29398/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig</span><br><span>index 2ba7992..e8e4f14 100644</span><br><span>--- a/src/soc/intel/braswell/Kconfig</span><br><span>+++ b/src/soc/intel/braswell/Kconfig</span><br><span>@@ -127,4 +127,17 @@</span><br><span>     string</span><br><span>       default "soc/intel/braswell/bootblock/timestamp.inc"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config ENABLE_SERIRQ</span><br><span style="color: hsl(120, 100%, 40%);">+      bool "Enable Serial IRQ"</span><br><span style="color: hsl(120, 100%, 40%);">+    default n</span><br><span style="color: hsl(120, 100%, 40%);">+     help</span><br><span style="color: hsl(120, 100%, 40%);">+          Enabled Serial IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SERIRQ_CONTINUOUS_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+   bool "Serial IRQ continuous mode"</span><br><span style="color: hsl(120, 100%, 40%);">+   default n</span><br><span style="color: hsl(120, 100%, 40%);">+     depends on ENABLE_SERIRQ</span><br><span style="color: hsl(120, 100%, 40%);">+      help</span><br><span style="color: hsl(120, 100%, 40%);">+          Enabled Serial IRQ continuous mode</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c</span><br><span>index dd0c78e..6e5ec63 100644</span><br><span>--- a/src/soc/intel/braswell/southcluster.c</span><br><span>+++ b/src/soc/intel/braswell/southcluster.c</span><br><span>@@ -77,6 +77,14 @@</span><br><span> #define LPC_DEFAULT_IO_RANGE_LOWER 0</span><br><span> #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_enable_serial_irqs(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+        u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+    write32(ilb_base + ILB_OIC, read32(ilb_base + ILB_OIC) | SIRQEN);</span><br><span style="color: hsl(120, 100%, 40%);">+     write8(ilb_base + SCNT, read8(ilb_base + SCNT) | SCNT_MODE);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static inline int io_range_in_default(int base, int size)</span><br><span> {</span><br><span>  /* Does it start above the range? */</span><br><span>@@ -161,6 +169,9 @@</span><br><span>   printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+       if (IS_ENABLED(CONFIG_ENABLE_SERIRQ))</span><br><span style="color: hsl(120, 100%, 40%);">+         sc_enable_serial_irqs(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>        /* Set up the PIRQ PIC routing based on static config. */</span><br><span>    for (i = 0; i < NUM_PIRQS; i++)</span><br><span>           write8((void *)(pr_base + i*sizeof(ir->pic[i])),</span><br><span>@@ -493,7 +504,9 @@</span><br><span>            write32(spi + LVSCC, cfg.lvscc | VCL);</span><br><span>       }</span><br><span>    spi_init();</span><br><span style="color: hsl(0, 100%, 40%);">-     enable_serirq_quiet_mode();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))</span><br><span style="color: hsl(120, 100%, 40%);">+                enable_serirq_quiet_mode();</span><br><span> </span><br><span>      printk(BIOS_DEBUG, "Finalizing SMM.\n");</span><br><span>   outb(APM_CNT_FINALIZE, APM_CNT);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29398">change 29398</a>. To unsubscribe, or for help writ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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 </div>
<div style="display:none"> Gerrit-Change-Number: 29398 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Frans Hendriks <fhendriks@eltan.com> </div>