<p>Tristan Corrick has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29381">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/lynxpoint: Automatically generate the ACPI PCI routing table<br><br>This patch is based on a8a9f34e9b7b ("sb/intel/i82801{g,j}x:<br>Automatically generate ACPI PIRQ tables")<br><br>Tested on an ASRock H81M-HDS. The generated _PRT object looks correct,<br>and the system doesn't show any issue when running. The following<br>assignments occur:<br><br> ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0<br> ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0<br> ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0<br> ACPI_PIRQ_GEN: PCI: 00:16.0: pin=0 pirq=0<br> ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=0<br> ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6<br> ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0<br> ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1<br> ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2<br> ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3<br> ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=7<br> ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=3<br> ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=2 pirq=2<br><br>Also tested on a Google Peppy board. The following assignments occur:<br><br> ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0<br> ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0<br> ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=2<br> ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6<br> ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0<br> ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3<br> ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=6<br> ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=2<br> ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=1<br><br>A diff of the _PRT object for the Google Peppy board is below. The code<br>used in the diff has been modified for clarity, but the semantics remain<br>the same. To summarise the diff:<br><br>* The disabled PCIe root ports are no longer included.<br><br>* The LPC controller is no longer included, as it has no interrupt pin.<br> The pins for the remaining LPC devices are each one less. Perhaps the<br> original _PRT object was incorrect?<br><br>* The SDIO device is no longer included, as it is disabled.<br><br>* The Serial IO devices are no longer included, but that is due to a<br> separate issue I am having with this system (the devices don't show up<br> under Linux regardless of this patch). In short: their omission is not<br> a fault of this patch.<br><br>--- pre/_PRT<br>+++ post/_PRT<br>@@ -1,301 +1,157 @@<br> Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table<br> {<br> If (PICM)<br> {<br>- Return (Package (0x12)<br>+ Return (Package (0x09)<br> {<br> Package (0x04)<br> {<br> 0x0002FFFF,<br> Zero,<br> Zero,<br> 0x10<br> },<br><br> Package (0x04)<br> {<br> 0x0003FFFF,<br> Zero,<br> Zero,<br> 0x10<br> },<br><br> Package (0x04)<br> {<br> 0x0014FFFF,<br> Zero,<br> Zero,<br> 0x12<br> },<br><br> Package (0x04)<br> {<br> 0x001BFFFF,<br> Zero,<br> Zero,<br> 0x16<br> },<br><br> Package (0x04)<br> {<br> 0x001CFFFF,<br> Zero,<br> Zero,<br> 0x10<br> },<br><br>- Package (0x04)<br>- {<br>- 0x001CFFFF,<br>- One,<br>- Zero,<br>- 0x11<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x001CFFFF,<br>- 0x02,<br>- Zero,<br>- 0x12<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x001CFFFF,<br>- 0x03,<br>- Zero,<br>- 0x13<br>- },<br>-<br> Package (0x04)<br> {<br> 0x001DFFFF,<br> Zero,<br> Zero,<br> 0x13<br> },<br><br> Package (0x04)<br> {<br> 0x001FFFFF,<br> Zero,<br> Zero,<br> 0x16<br> },<br><br> Package (0x04)<br> {<br> 0x001FFFFF,<br> One,<br> Zero,<br> 0x12<br> },<br><br> Package (0x04)<br> {<br> 0x001FFFFF,<br> 0x02,<br> Zero,<br> 0x11<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x001FFFFF,<br>- 0x03,<br>- Zero,<br>- 0x10<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x0015FFFF,<br>- Zero,<br>- Zero,<br>- 0x14<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x0015FFFF,<br>- One,<br>- Zero,<br>- 0x15<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x0015FFFF,<br>- 0x02,<br>- Zero,<br>- 0x15<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x0015FFFF,<br>- 0x03,<br>- Zero,<br>- 0x15<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x0017FFFF,<br>- Zero,<br>- Zero,<br>- 0x17<br> }<br> })<br> }<br> Else<br> {<br>- Return (Package (0x12)<br>+ Return (Package (0x09)<br> {<br> Package (0x04)<br> {<br> 0x0002FFFF,<br> Zero,<br> ^LPCB.LNKA,<br> Zero<br> },<br><br> Package (0x04)<br> {<br> 0x0003FFFF,<br> Zero,<br> ^LPCB.LNKA,<br> Zero<br> },<br><br> Package (0x04)<br> {<br> 0x0014FFFF,<br> Zero,<br> ^LPCB.LNKC,<br> Zero<br> },<br><br> Package (0x04)<br> {<br> 0x001BFFFF,<br> Zero,<br> ^LPCB.LNKG,<br> Zero<br> },<br><br> Package (0x04)<br> {<br> 0x001CFFFF,<br> Zero,<br> ^LPCB.LNKA,<br> Zero<br> },<br><br>- Package (0x04)<br>- {<br>- 0x001CFFFF,<br>- One,<br>- ^LPCB.LNKB,<br>- Zero<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x001CFFFF,<br>- 0x02,<br>- ^LPCB.LNKC,<br>- Zero<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x001CFFFF,<br>- 0x03,<br>- ^LPCB.LNKD,<br>- Zero<br>- },<br>-<br> Package (0x04)<br> {<br> 0x001DFFFF,<br> Zero,<br> ^LPCB.LNKD,<br> Zero<br> },<br><br> Package (0x04)<br> {<br> 0x001FFFFF,<br> Zero,<br> ^LPCB.LNKG,<br> Zero<br> },<br><br> Package (0x04)<br> {<br> 0x001FFFFF,<br> One,<br> ^LPCB.LNKC,<br> Zero<br> },<br><br> Package (0x04)<br> {<br> 0x001FFFFF,<br> 0x02,<br> ^LPCB.LNKB,<br> Zero<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x001FFFFF,<br>- 0x03,<br>- ^LPCB.LNKA,<br>- Zero<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x0015FFFF,<br>- Zero,<br>- ^LPCB.LNKE,<br>- Zero<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x0015FFFF,<br>- One,<br>- ^LPCB.LNKF,<br>- Zero<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x0015FFFF,<br>- 0x02,<br>- ^LPCB.LNKF,<br>- Zero<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x0015FFFF,<br>- 0x03,<br>- ^LPCB.LNKF,<br>- Zero<br>- },<br>-<br>- Package (0x04)<br>- {<br>- 0x0017FFFF,<br>- Zero,<br>- ^LPCB.LNKH,<br>- Zero<br> }<br> })<br> }<br> }<br><br>Change-Id: Id3f067cbf7c7d649fbbf774648d8ff928cb752a4<br>Signed-off-by: Tristan Corrick <tristan@corrick.kiwi><br>---<br>D src/mainboard/google/beltino/acpi/haswell_pci_irqs.asl<br>D src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl<br>D src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl<br>M src/northbridge/intel/haswell/acpi/hostbridge.asl<br>M src/northbridge/intel/haswell/northbridge.c<br>M src/southbridge/intel/lynxpoint/Kconfig<br>M src/southbridge/intel/lynxpoint/lpc.c<br>7 files changed, 31 insertions(+), 231 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29381/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/beltino/acpi/haswell_pci_irqs.asl b/src/mainboard/google/beltino/acpi/haswell_pci_irqs.asl</span><br><span>deleted file mode 100644</span><br><span>index 0900a3d..0000000</span><br><span>--- a/src/mainboard/google/beltino/acpi/haswell_pci_irqs.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,82 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* This is board specific information: IRQ routing for Haswell */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-// PCI Interrupt Routing</span><br><span style="color: hsl(0, 100%, 40%);">-Method(_PRT)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- If (PICM) {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (Package() {</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard graphics (IGD) 0:2.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0002ffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Mini-HD Audio 0:3.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0003ffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // High Definition Audio 0:1b.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001bffff, 0, 0, 22 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Root Ports 0:1c.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // EHCI 0:1d.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 0, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // XHCI 0:14.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0014ffff, 0, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- // LPC devices 0:1f.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 0, 0, 22 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 1, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 2, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 3, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Serial IO 0:15.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 0, 0, 20 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 1, 0, 21 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 2, 0, 21 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 3, 0, 21 },</span><br><span style="color: hsl(0, 100%, 40%);">- // SDIO 0:17.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0017ffff, 0, 0, 23 },</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">- } Else {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (Package() {</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard graphics (IGD) 0:2.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Mini-HD Audio 0:3.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // High Definition Audio 0:1b.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Root Ports 0:1c.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // EHCI 0:1d.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // XHCI 0:14.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // LPC device 0:1f.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Serial IO 0:15.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // SDIO 0:17.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl</span><br><span>deleted file mode 100644</span><br><span>index 0900a3d..0000000</span><br><span>--- a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,82 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* This is board specific information: IRQ routing for Haswell */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-// PCI Interrupt Routing</span><br><span style="color: hsl(0, 100%, 40%);">-Method(_PRT)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- If (PICM) {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (Package() {</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard graphics (IGD) 0:2.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0002ffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Mini-HD Audio 0:3.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0003ffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // High Definition Audio 0:1b.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001bffff, 0, 0, 22 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Root Ports 0:1c.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // EHCI 0:1d.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 0, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // XHCI 0:14.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0014ffff, 0, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- // LPC devices 0:1f.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 0, 0, 22 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 1, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 2, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 3, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Serial IO 0:15.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 0, 0, 20 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 1, 0, 21 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 2, 0, 21 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 3, 0, 21 },</span><br><span style="color: hsl(0, 100%, 40%);">- // SDIO 0:17.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0017ffff, 0, 0, 23 },</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">- } Else {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (Package() {</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard graphics (IGD) 0:2.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Mini-HD Audio 0:3.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // High Definition Audio 0:1b.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Root Ports 0:1c.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // EHCI 0:1d.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // XHCI 0:14.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // LPC device 0:1f.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Serial IO 0:15.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // SDIO 0:17.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl b/src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl</span><br><span>deleted file mode 100644</span><br><span>index 3e841e0..0000000</span><br><span>--- a/src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,64 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* This is board specific information: IRQ routing for IvyBridge */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-// PCI Interrupt Routing</span><br><span style="color: hsl(0, 100%, 40%);">-Method(_PRT)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- If (PICM) {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (Package() {</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard graphics (IGD) 0:2.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0002ffff, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // High Definition Audio 0:1b.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001bffff, 0, 0, 22 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Root Ports 0:1c.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 0, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 1, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 2, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 3, 0, 20 },</span><br><span style="color: hsl(0, 100%, 40%);">- // EHCI #1 0:1d.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 0, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // EHCI #2 0:1a.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 0, 0, 20 },</span><br><span style="color: hsl(0, 100%, 40%);">- // LPC devices 0:1f.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 0, 0, 21 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 1, 0, 22 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 2, 0, 23 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 3, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">- } Else {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (Package() {</span><br><span style="color: hsl(0, 100%, 40%);">- // Onboard graphics (IGD) 0:2.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // High Definition Audio 0:1b.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCIe Root Ports 0:1c.x</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // EHCI #1 0:1d.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // EHCI #2 0:1a.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- // LPC device 0:1f.0</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl</span><br><span>index 2565851..1ebdf28 100644</span><br><span>--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl</span><br><span>+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl</span><br><span>@@ -455,6 +455,3 @@</span><br><span> </span><br><span> Return (MCRS)</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */</span><br><span style="color: hsl(0, 100%, 40%);">-#include "acpi/haswell_pci_irqs.asl"</span><br><span>diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c</span><br><span>index ccfb234..4501afa 100644</span><br><span>--- a/src/northbridge/intel/haswell/northbridge.c</span><br><span>+++ b/src/northbridge/intel/haswell/northbridge.c</span><br><span>@@ -74,6 +74,22 @@</span><br><span> assign_resources(dev->link_list);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static const char *northbridge_acpi_name(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.type == DEVICE_PATH_DOMAIN)</span><br><span style="color: hsl(120, 100%, 40%);">+ return "PCI0";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (dev->path.pci.devfn) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(0, 0):</span><br><span style="color: hsl(120, 100%, 40%);">+ return "MCHC";</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* TODO We could determine how many PCIe busses we need in</span><br><span> * the bar. For now that number is hardcoded to a max of 64.</span><br><span> * See e7525/northbridge.c for an example.</span><br><span>@@ -84,6 +100,7 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_name = northbridge_acpi_name,</span><br><span> .write_acpi_tables = northbridge_write_acpi_tables,</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig</span><br><span>index 32485c5..1e088c1 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/Kconfig</span><br><span>+++ b/src/southbridge/intel/lynxpoint/Kconfig</span><br><span>@@ -33,6 +33,7 @@</span><br><span> select HAVE_SPI_CONSOLE_SUPPORT</span><br><span> select RTC</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ</span><br><span> select HAVE_INTEL_CHIPSET_LOCKDOWN</span><br><span> </span><br><span> config INTEL_LYNXPOINT_LP</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>index 6483e6d..cf5959e 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>@@ -36,6 +36,7 @@</span><br><span> #include <arch/acpigen.h></span><br><span> #include <cbmem.h></span><br><span> #include <drivers/intel/gma/i915.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/acpi_pirq_gen.h></span><br><span> </span><br><span> #define NMI_OFF 0</span><br><span> </span><br><span>@@ -789,6 +790,16 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static const char *lpc_acpi_name(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return "LPCB";</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_fill_ssdt(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ intel_acpi_gen_def_acpi_pirq(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static unsigned long southbridge_write_acpi_tables(struct device *device,</span><br><span> unsigned long start,</span><br><span> struct acpi_rsdp *rsdp)</span><br><span>@@ -835,7 +846,9 @@</span><br><span> .read_resources = pch_lpc_read_resources,</span><br><span> .set_resources = pci_dev_set_resources,</span><br><span> .enable_resources = pci_dev_enable_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_fill_ssdt_generator = southbridge_fill_ssdt,</span><br><span> .acpi_inject_dsdt_generator = southbridge_inject_dsdt,</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_name = lpc_acpi_name,</span><br><span> .write_acpi_tables = southbridge_write_acpi_tables,</span><br><span> .init = lpc_init,</span><br><span> .enable = pch_lpc_enable,</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29381">change 29381</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29381"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id3f067cbf7c7d649fbbf774648d8ff928cb752a4 </div>
<div style="display:none"> Gerrit-Change-Number: 29381 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Corrick <tristan@corrick.kiwi> </div>