<p>Martin Roth <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/29345">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Marshall Dawson: Looks good to me, approved
Richard Spiegel: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Get rid of domain_read_resources<br><br>The function domain_read_resources() didn't have any code to actually<br>reserve any resources - it was just creating an empty resource entry.<br><br>I looked at fixing it to actually reserve the space, but the values in<br>the registers at the point when this runs aren't the final values that<br>we want to reserve anyway, they're temp values with a range much larger<br>than we want to reserve.<br><br>I next looked at moving the amd_initcpuio() function earlier so that we<br>could get the correct values for the registers, but even that doesn't<br>give us what we really want.<br><br>Ultimately removing this whole function seems to be the right thing.<br><br>BUG=None<br>TEST=Verify that the only resource that changes is the empty resource:<br>PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 1080<br><br>Change-Id: I83bd3ea8db141416632c12fc883386070363f2f1<br>Signed-off-by: Martin Roth <martinroth@google.com><br>Reviewed-on: https://review.coreboot.org/29345<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/chip.c<br>M src/soc/amd/stoneyridge/northbridge.c<br>2 files changed, 1 insertion(+), 38 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c</span><br><span>index 33c1730..ef65887 100644</span><br><span>--- a/src/soc/amd/stoneyridge/chip.c</span><br><span>+++ b/src/soc/amd/stoneyridge/chip.c</span><br><span>@@ -114,7 +114,7 @@</span><br><span> };</span><br><span> </span><br><span> struct device_operations pci_domain_ops = {</span><br><span style="color: hsl(0, 100%, 40%);">- .read_resources = domain_read_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ .read_resources = pci_domain_read_resources,</span><br><span> .set_resources = domain_set_resources,</span><br><span> .enable_resources = domain_enable_resources,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>index 3dae2ba..d7a20a3 100644</span><br><span>--- a/src/soc/amd/stoneyridge/northbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>@@ -388,43 +388,6 @@</span><br><span> pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void domain_read_resources(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int reg;</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Find the already assigned resource pairs */</span><br><span style="color: hsl(0, 100%, 40%);">- for (reg = 0x80 ; reg <= 0xd8 ; reg += 0x08) {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 base, limit;</span><br><span style="color: hsl(0, 100%, 40%);">- base = pci_read_config32(addr_map, reg);</span><br><span style="color: hsl(0, 100%, 40%);">- limit = pci_read_config32(addr_map, reg + 4);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Is this register allocated? */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((base & 3) != 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int nodeid, reg_link;</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *reg_dev = dev_find_slot(0, HT_DEVFN);</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg < 0xc0) /* mmio */</span><br><span style="color: hsl(0, 100%, 40%);">- nodeid = (limit & 0xf) + (base & 0x30);</span><br><span style="color: hsl(0, 100%, 40%);">- else /* io */</span><br><span style="color: hsl(0, 100%, 40%);">- nodeid = (limit & 0xf) + ((base >> 4) & 0x30);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg_link = (limit >> 4) & 7;</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg_dev) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Reserve the resource */</span><br><span style="color: hsl(0, 100%, 40%);">- struct resource *res;</span><br><span style="color: hsl(0, 100%, 40%);">- res = new_resource(reg_dev,</span><br><span style="color: hsl(0, 100%, 40%);">- IOINDEX(0x1000 + reg,</span><br><span style="color: hsl(0, 100%, 40%);">- reg_link));</span><br><span style="color: hsl(0, 100%, 40%);">- if (res)</span><br><span style="color: hsl(0, 100%, 40%);">- res->flags = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- /* FIXME: do we need to check extend conf space?</span><br><span style="color: hsl(0, 100%, 40%);">- I don't believe that much preset value */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pci_domain_read_resources(dev);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void domain_enable_resources(struct device *dev)</span><br><span> {</span><br><span> /* Must be called after PCI enumeration and resource allocation */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29345">change 29345</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I83bd3ea8db141416632c12fc883386070363f2f1 </div>
<div style="display:none"> Gerrit-Change-Number: 29345 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Daniel Kurtz <djkurtz@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Marc Jones <marc@marcjonesconsulting.com> </div>
<div style="display:none"> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Raul Rangel <rrangel@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>