<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29409">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/sarien: Add new mainboard<br><br>Sarien is a new board using Intel Whiskey Lake SOC. It also uses<br>the newly added Wilco EC, enabled in a separate commit.<br><br>Sarien is not a true reference board, it is just one variant of<br>a very similar design. For that reason it is not considered the<br>baseboard but rather a standalone variant.<br><br>Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775<br>Signed-off-by: Duncan Laurie <dlaurie@google.com><br>---<br>A src/mainboard/google/sarien/Kconfig<br>A src/mainboard/google/sarien/Kconfig.name<br>A src/mainboard/google/sarien/Makefile.inc<br>A src/mainboard/google/sarien/acpi_tables.c<br>A src/mainboard/google/sarien/board_info.txt<br>A src/mainboard/google/sarien/bootblock.c<br>A src/mainboard/google/sarien/chromeos.c<br>A src/mainboard/google/sarien/chromeos.fmd<br>A src/mainboard/google/sarien/dsdt.asl<br>A src/mainboard/google/sarien/ramstage.c<br>A src/mainboard/google/sarien/romstage.c<br>A src/mainboard/google/sarien/variants/sarien/Makefile.inc<br>A src/mainboard/google/sarien/variants/sarien/devicetree.cb<br>A src/mainboard/google/sarien/variants/sarien/gpio.c<br>A src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h<br>15 files changed, 905 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/29409/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..4bf5191</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/Kconfig</span><br><span>@@ -0,0 +1,89 @@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_GOOGLE_BASEBOARD_SARIEN</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool n</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_32768</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_GENERIC</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_HID</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_SPI_ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_PS2_KEYBOARD</span><br><span style="color: hsl(120, 100%, 40%);">+ select GENERIC_SPD_BIN</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_I2C_TPM_CR50</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_TPM2</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COFFEELAKE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_CANNONLAKE_MEMCFG_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select SPD_READ_BY_WORD</span><br><span style="color: hsl(120, 100%, 40%);">+ select SYSTEM_TYPE_LAPTOP</span><br><span style="color: hsl(120, 100%, 40%);">+ select TPM2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_GOOGLE_BASEBOARD_SARIEN</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default y</span><br><span style="color: hsl(120, 100%, 40%);">+ select GBB_FLAG_FORCE_DEV_SWITCH_ON</span><br><span style="color: hsl(120, 100%, 40%);">+ select GBB_FLAG_FORCE_DEV_BOOT_USB</span><br><span style="color: hsl(120, 100%, 40%);">+ select GBB_FLAG_FORCE_DEV_BOOT_LEGACY</span><br><span style="color: hsl(120, 100%, 40%);">+ select GBB_FLAG_FORCE_MANUAL_RECOVERY</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/sarien/devicetree.cb" if BOARD_GOOGLE_SARIEN</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DIMM_MAX</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DIMM_SPD_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 512</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DRIVER_TPM_I2C_BUS</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DRIVER_TPM_I2C_ADDR</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x50</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config TPM_TIS_ACPI_INTERRUPT</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 82 # GPE0_DW2_18 (GPP_D18)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config GBB_HWID</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+ default "SARIEN TEST 2787" if BOARD_GOOGLE_SARIEN</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "google/sarien"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_FAMILY</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Google_Sarien" if BOARD_GOOGLE_SARIEN</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Sarien" if BOARD_GOOGLE_SARIEN</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_VENDOR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Google"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VARIANT_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "sarien" if BOARD_GOOGLE_SARIEN</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAS_RECOVERY_MRC_CACHE</span><br><span style="color: hsl(120, 100%, 40%);">+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_LID_SWITCH</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_GOOGLE_BASEBOARD_SARIEN</span><br><span>diff --git a/src/mainboard/google/sarien/Kconfig.name b/src/mainboard/google/sarien/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..dcf279b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/Kconfig.name</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+comment "Sarien"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_GOOGLE_SARIEN</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "-> Sarien"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_GOOGLE_BASEBOARD_SARIEN</span><br><span>diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..d0b1cef</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/Makefile.inc</span><br><span>@@ -0,0 +1,28 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += ramstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += romstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += variants/$(VARIANT_DIR)</span><br><span style="color: hsl(120, 100%, 40%);">+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include</span><br><span>diff --git a/src/mainboard/google/sarien/acpi_tables.c b/src/mainboard/google/sarien/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/acpi_tables.c</span><br><span>diff --git a/src/mainboard/google/sarien/board_info.txt b/src/mainboard/google/sarien/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..8b9436d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/board_info.txt</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor name: Google</span><br><span style="color: hsl(120, 100%, 40%);">+Board name: Sarien</span><br><span style="color: hsl(120, 100%, 40%);">+Category: laptop</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span>diff --git a/src/mainboard/google/sarien/bootblock.c b/src/mainboard/google/sarien/bootblock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..399a127</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/bootblock.c</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void early_config_gpio(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct pad_config *early_gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num_gpios = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ early_gpio_table = variant_early_gpio_table(&num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure_pads(early_gpio_table, num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_mainboard_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ early_config_gpio();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c</span><br><span>new file mode 100644</span><br><span>index 0000000..33647df</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/chromeos.c</span><br><span>@@ -0,0 +1,80 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <boot/coreboot_tables.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <rules.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void fill_lb_gpios(struct lb_gpios *gpios)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct lb_gpio chromeos_gpios[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, 0, "power"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, 0, "EC in RW"},</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int cros_get_gpio_value(int type)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct cros_gpio *cros_gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t i, num_gpios = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cros_gpios = variant_cros_gpios(&num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < num_gpios; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct cros_gpio *gpio = &cros_gpios[i];</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpio->type == type) {</span><br><span style="color: hsl(120, 100%, 40%);">+ int state = gpio_get(gpio->gpio_num);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpio->polarity == CROS_GPIO_ACTIVE_LOW)</span><br><span style="color: hsl(120, 100%, 40%);">+ return !state;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ return state;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_chromeos_acpi_generate(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct cros_gpio *cros_gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num_gpios = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cros_gpios = variant_cros_gpios(&num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chromeos_acpi_gpio_generate(cros_gpios, num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int get_write_protect_state(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return cros_get_gpio_value(CROS_GPIO_WP);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int get_recovery_mode_switch(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return cros_get_gpio_value(CROS_GPIO_REC);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int get_lid_switch(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd</span><br><span>new file mode 100644</span><br><span>index 0000000..6631769</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/chromeos.fmd</span><br><span>@@ -0,0 +1,46 @@</span><br><span style="color: hsl(120, 100%, 40%);">+FLASH@0xfe000000 0x2000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_ALL@0x0 0x1000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_DESC@0x0 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_EC@0x1000 0x100000</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_GBE@0x101000 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_ME@0x103000 0xefd000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_BIOS@0x1000000 0x1000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SECTION_A@0x0 0x280000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_A@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ FW_MAIN_A(CBFS)@0x10000 0x26ffc0</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_FWID_A@0x27ffc0 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SECTION_B@0x280000 0x280000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_B@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ FW_MAIN_B(CBFS)@0x10000 0x26ffc0</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_FWID_B@0x27ffc0 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_MISC@0x500000 0x30000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ UNIFIED_MRC_CACHE@0x0 0x20000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RECOVERY_MRC_CACHE@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_MRC_CACHE@0x10000 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_ELOG@0x20000 0x4000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SHARED@0x24000 0x4000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHARED_DATA@0x0 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_DEV@0x2000 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_VPD@0x28000 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_NVRAM@0x2a000 0x6000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ CONSOLE@0x530000 0x20000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_LEGACY(CBFS)@0x550000 0x6b0000</span><br><span style="color: hsl(120, 100%, 40%);">+ WP_RO@0xc00000 0x400000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_VPD@0x0 0x4000</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_UNUSED@0x4000 0xc000</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_SECTION@0x10000 0x3f0000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ FMAP@0x0 0x800</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_FRID@0x800 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_FRID_PAD@0x840 0x7c0</span><br><span style="color: hsl(120, 100%, 40%);">+ GBB@0x1000 0xef000</span><br><span style="color: hsl(120, 100%, 40%);">+ COREBOOT(CBFS)@0xf0000 0x300000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..3295078</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/dsdt.asl</span><br><span>@@ -0,0 +1,53 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x05, /* DSDT revision: ACPI v5.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", /* OEM id */</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", /* OEM table id */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20110725 /* OEM revision */</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Some generic macros */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/cannonlake/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* global NVS and variables */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/cannonlake/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/cannonlake/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PWRB)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0C0C"))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/cannonlake/acpi/northbridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/cannonlake/acpi/southbridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_CHROMEOS)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chrome OS specific */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <vendorcode/google/chromeos/acpi/chromeos.asl></span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chipset specific sleep states */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/cannonlake/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..c65104b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/ramstage.c</span><br><span>@@ -0,0 +1,37 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/ramstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_silicon_init_params(FSP_S_CONFIG *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct pad_config *gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num_gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_table = variant_gpio_table(&num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure_pads(gpio_table, num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..7284d55</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/romstage.c</span><br><span>@@ -0,0 +1,50 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cnl_memcfg_init.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct cnl_mb_cfg memcfg = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The dqs_map arrays map the ddr4 pins to the SoC pins</span><br><span style="color: hsl(120, 100%, 40%);">+ * for both channels.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * the index = pin number on ddr4 part</span><br><span style="color: hsl(120, 100%, 40%);">+ * the value = pin number on SoC</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 },</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Baseboard uses 121, 81 and 100 rcomp resistors */</span><br><span style="color: hsl(120, 100%, 40%);">+ .rcomp_resistor = { 121, 81, 100 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Baseboard Rcomp target values.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ .rcomp_targets = { 100, 40, 20, 20, 26 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable Early Command Training */</span><br><span style="color: hsl(120, 100%, 40%);">+ .ect = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_memory_init_params(FSPM_UPD *memupd)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct spd_info spd = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .spd_smbus_address[0] = 0xa0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .spd_smbus_address[2] = 0xa4</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg, &spd);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/Makefile.inc b/src/mainboard/google/sarien/variants/sarien/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..2bf028e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/Makefile.inc</span><br><span>@@ -0,0 +1,19 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += gpio.c</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..1f262bf</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>@@ -0,0 +1,163 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/cannonlake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "PMC_GPP_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "PMC_GPP_C"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "PMC_GPP_D"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "HeciEnabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataSalpSupport" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataMode" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "InternalGfx" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SkipExtGfxScan" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "VmxEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "speed_shift_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "s0ix_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Intel Common SoC Config</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Ext USB2 Port 1 Charge</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Ext USB2 Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)" # Ext USB2 Port 3</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_EMPTY"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # FPR in PB</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 2230 (BT)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB3 Port 1 Charge</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB3 Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Ext USB3 Port 3</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 3042 (WWAN)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[5]" = "USB3_PORT_EMPTY"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Intel Common SoC Config</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Field | Value |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| I2C0 | Touchscreen |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| I2C1 | Touchpad |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| I2C4 | H1 TPM |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "common_soc_config" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .i2c[0] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .i2c[1] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .i2c[4] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .early_init = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PCIe port 8 for Card Reader</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[4]" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[4]" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PCIe port 9 for LAN</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[3]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[3]" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PCIe port 10 for M.2 2230 WLAN</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[9]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[1]" = "9"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PCIe port 12 for M.2 3042</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[0]" = "11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[0]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PCIe port 13 for M.2 2280 SSD</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[12]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[2]" = "12"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[2]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 on end # SA Thermal device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.5 off end # UFS SCS</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.6 off end # GSPI #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # USB xHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.5 off end # SDCard</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # I2C #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/hid</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.hid" = ""ACPI0C50""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.desc" = ""Touchpad""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid_desc_reg_offset" = "0x20"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 2c on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # I2C #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 off end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 off end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.5 off end # Management Engine Interface 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = ""GOOG0005""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 50 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # I2C #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 off end # I2C #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 on end # UART #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 off end # eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCI Express Port 1 (USB)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off end # PCI Express Port 2 (USB)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCI Express Port 3 (USB)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCI Express Port 4 (USB)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 off end # PCI Express Port 5 (USB)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 on end # PCI Express Port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # PCI Express Port 9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 on end # PCI Express Port 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 on end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.4 on end # PCI Express Port 13 (x4)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 off end # UART #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 off end # GSPI #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on end # LPC/eSPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 on end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..3656afb</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>@@ -0,0 +1,263 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Pad configuration in ramstage */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* RCIN# */ PAD_NC(GPP_A0, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_IO0 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_IO1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_IO2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_IO3 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_CS# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SERIRQ */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PIRQA# */ PAD_NC(GPP_A7, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CLKRUN# */ PAD_NC(GPP_A8, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PME# */ PAD_NC(GPP_A11, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* BM_BUSY# */ PAD_NC(GPP_A12, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSWARN# */ PAD_NC(GPP_A13, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_RESET# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSACK# */ PAD_NC(GPP_A15, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP0 */ PAD_NC(GPP_A18, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP1 */ PAD_NC(GPP_A19, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP2 */ PAD_NC(GPP_A20, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP3 */ PAD_NC(GPP_A21, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP4 */ PAD_NC(GPP_A22, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP5 */ PAD_NC(GPP_A23, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID0 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* VRALERT# */ PAD_NC(GPP_B2, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ EDGE_SINGLE, INVERT), /* HDD_FALL_INT */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RXD */ PAD_NC(GPP_C8, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_TXD */ PAD_NC(GPP_C9, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ EDGE_SINGLE), /* SIO_EXT_WAKE# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_TXD */ PAD_NC(GPP_C13, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_CTS# */ PAD_NC(GPP_C15, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_RTS# */ PAD_NC(GPP_C22, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ EDGE_SINGLE, INVERT), /* TS_INT# */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_CLK */ PAD_NC(GPP_D1, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_MISO */ PAD_NC(GPP_D2, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* FASHTRIG */ PAD_NC(GPP_D4, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* WWAN_GPIO_PERST# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ EDGE_SINGLE), /* WWAN_GPIO_WAKE# */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* HDD_DET# */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* M3042_PCIE#_SATA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* M2880_PCIE_SATA# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* HDD_DEVSLP */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC3# */ PAD_NC(GPP_E12, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ EDGE_SINGLE, INVERT), /* FFS_INT2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_F1 */ PAD_NC(GPP_F1, NONE), /* T406 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_F2 */ PAD_NC(GPP_F2, NONE), /* T407 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_F3 */ PAD_NC(GPP_F3, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_F10 */ PAD_NC(GPP_F10, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CMD */ PAD_NC(GPP_F11, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_RCLK */ PAD_NC(GPP_F20, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CLK */ PAD_NC(GPP_F21, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_RESET# */ PAD_NC(GPP_F22, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA0 */ PAD_NC(GPP_G1, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA1 */ PAD_NC(GPP_G2, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* T383 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_WP */ PAD_NC(GPP_G7, NONE), /* T384 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_RXD */ PAD_NC(GPP_H3, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SDA */ PAD_NC(GPP_H4, NONE), /* T388 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* T389 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* T378 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SCL */ PAD_NC(GPP_H7, NONE), /* T379 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C5_SDA */ PAD_NC(GPP_H10, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C5_SCL */ PAD_NC(GPP_H11, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* M2_SKT2_CFG3 */ PAD_NC(GPP_H15, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_H21 */ PAD_NC(GPP_H21, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_H22 */ PAD_NC(GPP_H22, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_H23 */ PAD_NC(GPP_H23, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */</span><br><span style="color: hsl(120, 100%, 40%);">+/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPD7 */ PAD_NC(GPD7, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Early pad configuration in bootblock */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_early_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(early_gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return early_gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct cros_gpio cros_gpios[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ CROS_GPIO_REC_AH(GPP_E8, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(120, 100%, 40%);">+ CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cros_gpio *variant_cros_gpios(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(cros_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ return cros_gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..f7e0403</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h</span><br><span>@@ -0,0 +1,34 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef VARIANT_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define VARIANT_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpe.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Flash Write Protect */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PCH_WP GPP_E15</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Recovery mode */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_REC_MODE GPP_E8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_gpio_table(size_t *num);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_early_gpio_table(size_t *num);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct cros_gpio;</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cros_gpio *variant_cros_gpios(size_t *num);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29409">change 29409</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29409"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775 </div>
<div style="display:none"> Gerrit-Change-Number: 29409 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>