<p>Frans Hendriks has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29373">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc/intel/braswell/acpi/southcluster.asl: Remove disabled LPEdevices<br><br>ACPI code for LPE devices enabled, but devcies are disabled on the platform<br>Remove the LPE devices when these are disabled.<br><br>BUG=N/A<br>TEST=Intel CherryHill CRB<br><br>Change-Id: I9973ba88df82c61863d16a7b4f3955af2efb7a0d<br>Signed-off-by: Frans Hendriks <fhendriks@eltan.com><br>---<br>M src/soc/intel/braswell/Kconfig<br>M src/soc/intel/braswell/acpi/southcluster.asl<br>2 files changed, 9 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29373/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig</span><br><span>index 2ba7992..6e3adcd 100644</span><br><span>--- a/src/soc/intel/braswell/Kconfig</span><br><span>+++ b/src/soc/intel/braswell/Kconfig</span><br><span>@@ -127,4 +127,10 @@</span><br><span>        string</span><br><span>       default "soc/intel/braswell/bootblock/timestamp.inc"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config ENABLE_LPE_DEVICES</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Include ASL code for LPE devices"</span><br><span style="color: hsl(120, 100%, 40%);">+     default y</span><br><span style="color: hsl(120, 100%, 40%);">+     help</span><br><span style="color: hsl(120, 100%, 40%);">+          Enable this if the LPE interfaces are supported</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl</span><br><span>index f7e3168..7ec8c54 100644</span><br><span>--- a/src/soc/intel/braswell/acpi/southcluster.asl</span><br><span>+++ b/src/soc/intel/braswell/acpi/southcluster.asl</span><br><span>@@ -2,6 +2,7 @@</span><br><span>  * This file is part of the coreboot project.</span><br><span>  *</span><br><span>  * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Eltan B.V.</span><br><span>  *</span><br><span>  * This program is free software; you can redistribute it and/or</span><br><span>  * modify it under the terms of the GNU General Public License as</span><br><span>@@ -287,6 +288,8 @@</span><br><span>         /* SCC Devices */</span><br><span>    #include "scc.asl"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_ENABLE_LPE_DEVICES)</span><br><span>  /* LPE Device */</span><br><span>     #include "lpe.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29373">change 29373</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29373"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9973ba88df82c61863d16a7b4f3955af2efb7a0d </div>
<div style="display:none"> Gerrit-Change-Number: 29373 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Frans Hendriks <fhendriks@eltan.com> </div>