<p>Tristan Corrick has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29390">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard: Add ASRock H81M-HDS<br><br>Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with<br>kernel 4.9.<br><br>This board works quite well under coreboot. A list of what works and<br>what doesn't can be found in the documentation part of this commit.<br><br>The file `data.vbt` matches the VBT in the latest stable version of the<br>vendor firmware (version 2.20).<br><br>Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a<br>Signed-off-by: Tristan Corrick <tristan@corrick.kiwi><br>---<br>A Documentation/mainboard/asrock/h81m-hds.md<br>M Documentation/mainboard/index.md<br>A src/mainboard/asrock/h81m-hds/Kconfig<br>A src/mainboard/asrock/h81m-hds/Kconfig.name<br>A src/mainboard/asrock/h81m-hds/Makefile.inc<br>A src/mainboard/asrock/h81m-hds/acpi/ec.asl<br>A src/mainboard/asrock/h81m-hds/acpi/platform.asl<br>A src/mainboard/asrock/h81m-hds/acpi/superio.asl<br>A src/mainboard/asrock/h81m-hds/acpi_tables.c<br>A src/mainboard/asrock/h81m-hds/board_info.txt<br>A src/mainboard/asrock/h81m-hds/cmos.default<br>A src/mainboard/asrock/h81m-hds/cmos.layout<br>A src/mainboard/asrock/h81m-hds/data.vbt<br>A src/mainboard/asrock/h81m-hds/devicetree.cb<br>A src/mainboard/asrock/h81m-hds/dsdt.asl<br>A src/mainboard/asrock/h81m-hds/gma-mainboard.ads<br>A src/mainboard/asrock/h81m-hds/gpio.h<br>A src/mainboard/asrock/h81m-hds/hda_verb.c<br>A src/mainboard/asrock/h81m-hds/mainboard.c<br>A src/mainboard/asrock/h81m-hds/romstage.c<br>20 files changed, 1,043 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/29390/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md</span><br><span>new file mode 100644</span><br><span>index 0000000..65c7b61</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/asrock/h81m-hds.md</span><br><span>@@ -0,0 +1,147 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# ASRock H81M-HDS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This page describes how to run coreboot on the [ASRock H81M-HDS].</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Required proprietary blobs</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This board currently requires a proprietary blob in order to initialise</span><br><span style="color: hsl(120, 100%, 40%);">+the RAM and a few other components. The blob largely consists of Intel's</span><br><span style="color: hsl(120, 100%, 40%);">+Memory Reference Code (shortened to mrc), and is just under 200 KiB</span><br><span style="color: hsl(120, 100%, 40%);">+in size. It is also known as a system agent binary. Unfortunately,</span><br><span style="color: hsl(120, 100%, 40%);">+it is not currently possible to distribute this as part of coreboot.</span><br><span style="color: hsl(120, 100%, 40%);">+However, the mrc can be obtained from a Haswell Chromebook firmware</span><br><span style="color: hsl(120, 100%, 40%);">+image, and you might find one online. The mrc from a ChromeOS image can</span><br><span style="color: hsl(120, 100%, 40%);">+be extracted with the following command. If extracting from a "standard"</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot image, omit `-r RO_SECTION`.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```bash</span><br><span style="color: hsl(120, 100%, 40%);">+cbfstool coreboot.rom extract -f mrc.bin -n mrc.bin -r RO_SECTION</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Now, place mrc.bin in the root of the coreboot directory.</span><br><span style="color: hsl(120, 100%, 40%);">+Alternatively, place it anywhere you want, and set `MRC_FILE` to its</span><br><span style="color: hsl(120, 100%, 40%);">+location when building coreboot.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Building coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+A fully working image should be possible just by setting your MAC</span><br><span style="color: hsl(120, 100%, 40%);">+address and obtaining the Haswell mrc. You can set the basic config</span><br><span style="color: hsl(120, 100%, 40%);">+with the following commands. However, it is strongly advised to use</span><br><span style="color: hsl(120, 100%, 40%);">+`make menuconfig` afterwards (or instead), so that you can see all of</span><br><span style="color: hsl(120, 100%, 40%);">+the settings.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```bash</span><br><span style="color: hsl(120, 100%, 40%);">+make distclean # Note: this will remove your current config, if it exists.</span><br><span style="color: hsl(120, 100%, 40%);">+touch .config</span><br><span style="color: hsl(120, 100%, 40%);">+./util/scripts/config --enable VENDOR_ASROCK</span><br><span style="color: hsl(120, 100%, 40%);">+./util/scripts/config --enable BOARD_ASROCK_H81M_HDS</span><br><span style="color: hsl(120, 100%, 40%);">+./util/scripts/config --enable HAVE_MRC</span><br><span style="color: hsl(120, 100%, 40%);">+./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" # Fill this in!</span><br><span style="color: hsl(120, 100%, 40%);">+make olddefconfig</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+If you don't plan on using coreboot's serial console to collect logs,</span><br><span style="color: hsl(120, 100%, 40%);">+you might want to disable it at this point (`./util/scripts/config</span><br><span style="color: hsl(120, 100%, 40%);">+--disable CONSOLE_SERIAL`). It should reduce the boot time by several</span><br><span style="color: hsl(120, 100%, 40%);">+seconds. However, a more flexible method is to change the console log</span><br><span style="color: hsl(120, 100%, 40%);">+level from within an OS using `util/nvramtool`, or with the `nvramcui`</span><br><span style="color: hsl(120, 100%, 40%);">+payload.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Now, run `make` to build the coreboot image.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Flashing coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Internal programming</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The main SPI flash can be accessed using [flashrom]. By default, only</span><br><span style="color: hsl(120, 100%, 40%);">+the BIOS region of the flash is writable. If you wish to change any</span><br><span style="color: hsl(120, 100%, 40%);">+other region, such as the Management Engine or firmware descriptor, then</span><br><span style="color: hsl(120, 100%, 40%);">+an external programmer is required (unless you find a clever way around</span><br><span style="color: hsl(120, 100%, 40%);">+the flash protection).</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The following command may be used to flash coreboot:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```bash</span><br><span style="color: hsl(120, 100%, 40%);">+sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The use of `--noverify-all` is required since the Management Engine</span><br><span style="color: hsl(120, 100%, 40%);">+region is not readable even by the host.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### External programming</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The flash chip is a 4 MiB socketed DIP-8 chip. Specifically, it's a</span><br><span style="color: hsl(120, 100%, 40%);">+Winbond W25Q32FV, whose datasheet can be found [here][W25Q32FV].</span><br><span style="color: hsl(120, 100%, 40%);">+The chip is located to the bottom right-hand side of the board. For</span><br><span style="color: hsl(120, 100%, 40%);">+a precise location, refer to section 1.4 (Motherboard Layout) of the</span><br><span style="color: hsl(120, 100%, 40%);">+[board manual], where the chip is labelled "32Mb BIOS". Take note of</span><br><span style="color: hsl(120, 100%, 40%);">+the chip's orientation, remove it from its socket, and flash it with</span><br><span style="color: hsl(120, 100%, 40%);">+an external programmer. For reference, the notch in the chip should be</span><br><span style="color: hsl(120, 100%, 40%);">+facing towards the bottom of the board.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Known issues</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- PCIe graphics is non-functional. The PCIe 16x slot doesn't work</span><br><span style="color: hsl(120, 100%, 40%);">+ with other devices, either.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- The HDMI and VGA ports don't work until Linux reinitialises the</span><br><span style="color: hsl(120, 100%, 40%);">+ display. The DVI port works as soon as libgfxinit has run, however.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- There is no automatic, OS-independent fan control. This is because</span><br><span style="color: hsl(120, 100%, 40%);">+ the super I/O hardware monitor can only obtain valid CPU temperature</span><br><span style="color: hsl(120, 100%, 40%);">+ readings from the PECI agent, but the required driver doesn't exist</span><br><span style="color: hsl(120, 100%, 40%);">+ in coreboot. The `coretemp` driver can still be used for accurate CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ temperature readings from an OS.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Untested</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- parallel port</span><br><span style="color: hsl(120, 100%, 40%);">+- PS/2 keyboard</span><br><span style="color: hsl(120, 100%, 40%);">+- EHCI debug</span><br><span style="color: hsl(120, 100%, 40%);">+- TPM</span><br><span style="color: hsl(120, 100%, 40%);">+- infrared module</span><br><span style="color: hsl(120, 100%, 40%);">+- chassis intrusion header</span><br><span style="color: hsl(120, 100%, 40%);">+- chassis speaker header</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Working</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- USB</span><br><span style="color: hsl(120, 100%, 40%);">+- S3 suspend/resume</span><br><span style="color: hsl(120, 100%, 40%);">+- Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+- integrated graphics</span><br><span style="color: hsl(120, 100%, 40%);">+- PCIe (but not the 16x slot, see [Known issues](#known-issues))</span><br><span style="color: hsl(120, 100%, 40%);">+- SATA</span><br><span style="color: hsl(120, 100%, 40%);">+- PS/2 mouse</span><br><span style="color: hsl(120, 100%, 40%);">+- serial port</span><br><span style="color: hsl(120, 100%, 40%);">+- hardware monitor (see [Known issues](#known-issues))</span><br><span style="color: hsl(120, 100%, 40%);">+- onboard audio</span><br><span style="color: hsl(120, 100%, 40%);">+- front panel audio</span><br><span style="color: hsl(120, 100%, 40%);">+- initialisation with Haswell mrc version 1.6.1 build 2</span><br><span style="color: hsl(120, 100%, 40%);">+- graphics init with libgfxinit (see [Known issues](#known-issues))</span><br><span style="color: hsl(120, 100%, 40%);">+- flashrom under the vendor firmware</span><br><span style="color: hsl(120, 100%, 40%);">+- flashrom under coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+- Wake-on-LAN</span><br><span style="color: hsl(120, 100%, 40%);">+- Using `me_cleaner`</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Technology</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Northbridge | Intel Haswell |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Southbridge | Intel Lynx Point (H81) |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CPU | Intel Haswell (LGA1150) |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Super I/O | Nuvoton NCT6776 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| EC | None |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Coprocessor | Intel Management Engine |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[ASRock H81M-HDS]: https://www.asrock.com/mb/Intel/H81M-HDS/</span><br><span style="color: hsl(120, 100%, 40%);">+[W25Q32FV]: https://www.winbond.com/resource-files/w25q32fv%20revi%2010202015.pdf</span><br><span style="color: hsl(120, 100%, 40%);">+[flashrom]: https://flashrom.org/Flashrom</span><br><span style="color: hsl(120, 100%, 40%);">+[Board manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf</span><br><span>diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md</span><br><span>index c1e5262..4383582 100644</span><br><span>--- a/Documentation/mainboard/index.md</span><br><span>+++ b/Documentation/mainboard/index.md</span><br><span>@@ -6,6 +6,10 @@</span><br><span> </span><br><span> - [P8H61-M LX](asus/p8h61-m_lx.md)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+## ASRock</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- [H81M-HDS](asrock/h81m-hds.md)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> ## Cavium</span><br><span> </span><br><span> - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..f93fcdb</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/Kconfig</span><br><span>@@ -0,0 +1,89 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+## (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_ASROCK_H81M_HDS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_4096</span><br><span style="color: hsl(120, 100%, 40%);">+ select CPU_INTEL_HASWELL</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_SMI_HANDLER</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_GMA_HAVE_VBT</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_INT15</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_LIBGFXINIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select NORTHBRIDGE_INTEL_HASWELL</span><br><span style="color: hsl(120, 100%, 40%);">+ select REALTEK_8168_RESET</span><br><span style="color: hsl(120, 100%, 40%);">+ select RT8168_SET_LED_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SERIRQ_CONTINUOUS_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_LYNXPOINT</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_NUVOTON_NCT6776</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_NUVOTON_NCT6776_COM_A</span><br><span style="color: hsl(120, 100%, 40%);">+ select TSC_MONOTONIC_TIMER</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CBFS_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x200000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# The override of GFX_GMA_CPU_VARIANT should be removed once the patches</span><br><span style="color: hsl(120, 100%, 40%);">+# for dynamic CPU detection are merged in libgfxinit.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+config GFX_GMA_CPU_VARIANT</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Normal"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default asrock/h81m-hds</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "H81M-HDS"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x8c5c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x1849</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# This is overridden if CMOS is used for configuration values.</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_POWER_ON_AFTER_POWER_FAIL</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MMCONF_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xf0000000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Since this is a desktop board, the assumption is made that most users</span><br><span style="color: hsl(120, 100%, 40%);">+# would want CMOS configuration enabled by default.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+config USE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default y</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/Kconfig.name b/src/mainboard/asrock/h81m-hds/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..4e4de82</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_ASROCK_H81M_HDS</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "H81M-HDS"</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..94bd1cfe</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/Makefile.inc</span><br><span>@@ -0,0 +1,17 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+## (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/acpi/ec.asl b/src/mainboard/asrock/h81m-hds/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/acpi/ec.asl</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/acpi/platform.asl b/src/mainboard/asrock/h81m-hds/acpi/platform.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..adaf51a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/acpi/platform.asl</span><br><span>@@ -0,0 +1,24 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_WAK, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() { 0, 0 })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PTS, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/acpi/superio.asl b/src/mainboard/asrock/h81m-hds/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..b671e3c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/acpi/superio.asl</span><br><span>@@ -0,0 +1,26 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV SIO0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_PNP_BASE 0x2e</span><br><span style="color: hsl(120, 100%, 40%);">+#define NCT6776_SHOW_PP</span><br><span style="color: hsl(120, 100%, 40%);">+#define NCT6776_SHOW_SP1</span><br><span style="color: hsl(120, 100%, 40%);">+#define NCT6776_SHOW_KBC</span><br><span style="color: hsl(120, 100%, 40%);">+#define NCT6776_SHOW_HWM</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#undef NCT6776_SHOW_GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/nct6776/acpi/superio.asl></span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/acpi_tables.c b/src/mainboard/asrock/h81m-hds/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..a43b499</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/acpi_tables.c</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/lynxpoint/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/board_info.txt b/src/mainboard/asrock/h81m-hds/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..56ad1b4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/board_info.txt</span><br><span>@@ -0,0 +1,7 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: desktop</span><br><span style="color: hsl(120, 100%, 40%);">+Board URL: https://www.asrock.com/mb/Intel/H81M-HDS/</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: DIP-8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: y</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2013</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default</span><br><span>new file mode 100644</span><br><span>index 0000000..c51001c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/cmos.default</span><br><span>@@ -0,0 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+boot_option=Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+debug_level=Debug</span><br><span style="color: hsl(120, 100%, 40%);">+nmi=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+power_on_after_fail=Disable</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..c7947f7</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/cmos.layout</span><br><span>@@ -0,0 +1,90 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register A</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register B</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register C</span><br><span style="color: hsl(120, 100%, 40%);">+#96 4 r 0 status_c_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#100 1 r 0 uf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#101 1 r 0 af_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#102 1 r 0 pf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#103 1 r 0 irqf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register D</span><br><span style="color: hsl(120, 100%, 40%);">+#104 7 r 0 status_d_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#111 1 r 0 valid_cmos_ram</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Diagnostic Status Register</span><br><span style="color: hsl(120, 100%, 40%);">+#112 8 r 0 diag_rsvd1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+0 120 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+#120 264 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 3 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: console</span><br><span style="color: hsl(120, 100%, 40%);">+#392 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+395 4 e 4 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+#399 1 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#400 8 r 0 reserved for century byte</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+408 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+409 2 e 1 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: check sums</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+3 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+3 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+4 2 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+4 3 Error</span><br><span style="color: hsl(120, 100%, 40%);">+4 4 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+4 5 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+4 6 Info</span><br><span style="color: hsl(120, 100%, 40%);">+4 7 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+4 8 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 415 984</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/data.vbt b/src/mainboard/asrock/h81m-hds/data.vbt</span><br><span>new file mode 100644</span><br><span>index 0000000..7190093</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/data.vbt</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..32b5978</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/devicetree.cb</span><br><span>@@ -0,0 +1,173 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+## (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/haswell</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_ddi_e_connected" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/haswell</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_acpower" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_battery" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_acpower" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_battery" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_acpower" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_battery" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xacac off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on # Host bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x0c00</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.0 on # PCIe graphics</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x0c01</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on # VGA controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x0402</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.0 on # Mini-HD audio</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x0c0c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/lynxpoint</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "0x8b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "0x8b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "0x8a"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "0x8a"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_ahci" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x33"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00000295" # Super I/O HWM</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # xHCI controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x8c31</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on # Management Engine interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x8c3a</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 off end # Intel Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on # EHCI controller #2</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x8c2d</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on # HD audio controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x7662</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on # PCIe port #1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x8c10</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off end # PCIe port #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCIe port #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 on # Realtek Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x8c16</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/net</span><br><span style="color: hsl(120, 100%, 40%);">+ register "customized_leds" = "0x0824"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x8168</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on # ASMedia USB controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x8c18</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x1042</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 on # PCIe 1x slot</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x8c1a</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCIe port #7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCIe port #8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on # EHCI controller #1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x8c26</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x8c5c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/nuvoton/nct6776</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 off end # Floppy</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 on # Parallel</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x0378</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 4 # No DMA</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x3c # Printer mode</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 on # UART A</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x03f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 on # IR</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x02f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # PS/2 KBC</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x0060</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x0064</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 1 # Keyboard</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x72 = 12 # Mouse</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.6 off end # CIR</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 off end # GPIO8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.107 off end # GPIO9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.8 off end # WDT</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.108 off end # GPIO0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.208 off end # GPIOA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.308 off end # GPIO base</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.109 off end # GPIO1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.209 off end # GPIO2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.309 off end # GPIO3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.409 off end # GPIO4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.509 off end # GPIO5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.609 off end # GPIO6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.709 off end # GPIO7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.a off end # ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.b on # HWM, LED</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x0290</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.d off end # VID</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.e off end # CIR wake-up</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.f off end # GPIO PP/OD</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.14 off end # SVID</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.16 off end # Deep sleep</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.17 off end # GPIOA</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on # SATA controller 1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x8c02</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x8c22</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off end # SATA controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..7ef9253</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/dsdt.asl</span><br><span>@@ -0,0 +1,41 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x03, /* DSDT Revision: ACPI v3.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", /* OEM ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", /* OEM Table ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20181031 /* OEM Revision */</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/platform.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/lynxpoint/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <cpu/intel/haswell/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/intel/haswell/acpi/haswell.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/lynxpoint/acpi/pch.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/gma-mainboard.ads b/src/mainboard/asrock/h81m-hds/gma-mainboard.ads</span><br><span>new file mode 100644</span><br><span>index 0000000..acdc8f7</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/gma-mainboard.ads</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+-- it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+-- the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+-- (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+-- but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+-- GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+with HW.GFX.GMA;</span><br><span style="color: hsl(120, 100%, 40%);">+with HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+use HW.GFX.GMA;</span><br><span style="color: hsl(120, 100%, 40%);">+use HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+private package GMA.Mainboard is</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ports : constant Port_List :=</span><br><span style="color: hsl(120, 100%, 40%);">+ (HDMI1,</span><br><span style="color: hsl(120, 100%, 40%);">+ HDMI2,</span><br><span style="color: hsl(120, 100%, 40%);">+ Analog,</span><br><span style="color: hsl(120, 100%, 40%);">+ others => Disabled);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+end GMA.Mainboard;</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/gpio.h b/src/mainboard/asrock/h81m-hds/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..dde3e53</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/gpio.h</span><br><span>@@ -0,0 +1,168 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef ASROCK_H81M_HDS_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define ASROCK_H81M_HDS_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_RESET_RSMRST,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set1_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set2_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set3 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set3_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set3_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set3_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set3_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* ASROCK_H81M_HDS_GPIO_H */</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/hda_verb.c b/src/mainboard/asrock/h81m-hds/hda_verb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..187b7c4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/hda_verb.c</span><br><span>@@ -0,0 +1,39 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10ec0662, /* Realtek ALC662 rev1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x18497662, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 11, /* Number of entries */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_SUBVENDOR(1, 0x18497662),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(1, 0x14, 0x01014010),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(1, 0x15, 0x40000000),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(1, 0x16, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(1, 0x18, 0x01a19040),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(1, 0x19, 0x02a19050),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(1, 0x1a, 0x0181304f),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(1, 0x1b, 0x02214020),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(1, 0x1c, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(1, 0x1d, 0x40a4c601),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(1, 0x1e, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[] = {};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+AZALIA_ARRAY_SIZES;</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/mainboard.c b/src/mainboard/asrock/h81m-hds/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..54176c4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/mainboard.c</span><br><span>@@ -0,0 +1,29 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/intel/gma/int15.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ GMA_INT15_PANEL_FIT_DEFAULT,</span><br><span style="color: hsl(120, 100%, 40%);">+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..f3c2b3b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/romstage.c</span><br><span>@@ -0,0 +1,131 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2010 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/haswell/haswell.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/haswell/haswell.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/haswell/pei_data.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/lynxpoint/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/common/nuvoton.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/nct6776/nct6776.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "gpio.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct rcba_config_instruction rcba_config[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_END_CONFIG,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_config_superio(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1);</span><br><span style="color: hsl(120, 100%, 40%);">+ const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);</span><br><span style="color: hsl(120, 100%, 40%);">+ const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Select HWM/LED functions instead of floppy functions. */</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Power RAM in S3 and let the PCH handle power failure actions. */</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_set_logical_device(ACPI_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_write_config(ACPI_DEV, 0xe4, 0x70);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Don't know what's needed here, just set the same as the vendor</span><br><span style="color: hsl(120, 100%, 40%);">+ * firmware.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_set_logical_device(IR_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_write_config(IR_DEV, 0xf1, 0x5c);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_romstage_entry(unsigned long bist)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct pei_data pei_data = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .pei_version = PEI_VERSION,</span><br><span style="color: hsl(120, 100%, 40%);">+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .epbar = DEFAULT_EPBAR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pciexbar = DEFAULT_PCIEXBAR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .smbusbar = SMBUS_IO_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .wdbbar = 0x4000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .wdbsize = 0x1000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .hpet_address = HPET_ADDR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rcba = (uintptr_t)DEFAULT_RCBA,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pmbase = DEFAULT_PMBASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpiobase = DEFAULT_GPIOBASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .temp_mmio_base = 0xfed08000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .system_type = 1, /* desktop/server */</span><br><span style="color: hsl(120, 100%, 40%);">+ .tseg_size = CONFIG_SMM_TSEG_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },</span><br><span style="color: hsl(120, 100%, 40%);">+ .ec_present = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dimm_channel0_disabled = 2, /* Disable DIMM 1 on channel 0. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dimm_channel1_disabled = 2, /* Disable DIMM 1 on channel 1. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_ddr3_freq = 1600,</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb2_ports = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Length, Enable, OCn#, Location */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 1, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 1, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 2, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 2, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb3_ports = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable, OCn# */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, USB_OC_PIN_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, USB_OC_PIN_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, USB_OC_PIN_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, USB_OC_PIN_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ struct romstage_params romstage_params = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .pei_data = &pei_data,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio_map = &mainboard_gpio_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rcba_config = &rcba_config[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ .bist = bist,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ romstage_common(&romstage_params);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29390">change 29390</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29390"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a </div>
<div style="display:none"> Gerrit-Change-Number: 29390 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Corrick <tristan@corrick.kiwi> </div>