<p>John Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29363">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Improve cold boot and S3 resume<br><br>FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure<br>PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default<br>100ms to 10ms to improve cold boot and S3 resume performance.<br><br>BUG=b:118676361<br>CQ-DEPEND=CL:*703187<br>TEST=Verified booting to kernel.<br><br>Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409<br>Signed-off-by: John Zhao <john.zhao@intel.com><br>---<br>M src/soc/intel/apollolake/chip.c<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h<br>2 files changed, 17 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29363/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c</span><br><span>index 9ee6dbb..976c45a 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.c</span><br><span>+++ b/src/soc/intel/apollolake/chip.c</span><br><span>@@ -567,6 +567,15 @@</span><br><span> * has set up. Hence skipping in FSP.</span><br><span> */</span><br><span> silconfig->SkipSpiPCP = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * FSP provides UPD interface to execute IPC command. In order to improve boot</span><br><span style="color: hsl(120, 100%, 40%);">+ * performance, configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay</span><br><span style="color: hsl(120, 100%, 40%);">+ * from 100ms (default) to 10ms.</span><br><span style="color: hsl(120, 100%, 40%);">+ * PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms,</span><br><span style="color: hsl(120, 100%, 40%);">+ * 101=50ms, 110=75ms, 111=100ms (default)</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ silconfig->PmicPmcIpcCtrl = 2;</span><br><span> #endif</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>index cc194b2..e8d02c7 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>@@ -1715,9 +1715,15 @@</span><br><span> **/</span><br><span> UINT8 SkipSpiPCP;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03AB</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03AB - PMIC PCH_WROK delay configuration - IPC Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ Upd for changing PCH_WROK delay configuration : I2C_Slave_Address (31:23) + Register_Offset</span><br><span style="color: hsl(120, 100%, 40%);">+ (23:16) + OR Value (15:8) + AND Value (7:0)</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspsUpd[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PmicPmcIpcCtrl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03AF</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspsUpd[1];</span><br><span> } FSP_S_CONFIG;</span><br><span> </span><br><span> /** Fsp S SGX Configuration</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29363">change 29363</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29363"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409 </div>
<div style="display:none"> Gerrit-Change-Number: 29363 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: John Zhao <john.zhao@intel.com> </div>