<p>Jonathan Neuschäfer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29356">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/sifive/fu540: Refactor PLL programming<br><br>The different PLLs in the fu540 use the same register layout, so use one<br>function (configure_pll) to program a PLL and wait for it to lock. This<br>also makes it possible to dynamically calculate the PLL settings later.<br><br>TEST=Boot until "Payload not loaded" on HiFive Unleashed<br><br>Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab<br>Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net><br>---<br>M src/soc/sifive/fu540/clock.c<br>1 file changed, 72 insertions(+), 84 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/29356/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c</span><br><span>index 20dce23..42fe716 100644</span><br><span>--- a/src/soc/sifive/fu540/clock.c</span><br><span>+++ b/src/soc/sifive/fu540/clock.c</span><br><span>@@ -20,6 +20,9 @@</span><br><span> #include <stdlib.h></span><br><span> #include <stdint.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+// 33.33 Mhz after reset</span><br><span style="color: hsl(120, 100%, 40%);">+#define FU540_BASE_FQY 33330</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct prci_ctlr {</span><br><span> u32 hfxosccfg; /* offset 0x00 */</span><br><span> u32 corepllcfg0; /* offset 0x04 */</span><br><span>@@ -40,33 +43,19 @@</span><br><span> #define PRCI_CORECLK_CORE_PLL 0</span><br><span> #define PRCI_CORECLK_HFCLK 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_COREPLLCFG0_LOCK (1u << 31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_COREPLLCFG0_DIVR_SHIFT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_COREPLLCFG0_DIVF_SHIFT 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_COREPLLCFG0_RANGE_SHIFT 18</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_COREPLLCFG0_FSE_SHIFT 25</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_COREPLLCFG0_DIVR_MASK (0x03f << PRCI_COREPLLCFG0_DIVR_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_COREPLLCFG0_DIVQ_MASK (0x007 << PRCI_COREPLLCFG0_DIVQ_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_COREPLLCFG0_RANGE_MASK (0x07 << PRCI_COREPLLCFG0_RANGE_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRPLLCFG0_LOCK (1u << 31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRPLLCFG0_FSE_SHIFT 25</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRPLLCFG0_DIVR_MASK (0x03f << PRCI_DDRPLLCFG0_DIVR_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x007 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRPLLCFG0_RANGE_MASK (0x07 << PRCI_DDRPLLCFG0_RANGE_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_PLLCFG_LOCK (1u << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_PLLCFG_DIVR_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_PLLCFG_DIVF_SHIFT 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_PLLCFG_DIVQ_SHIFT 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_PLLCFG_RANGE_SHIFT 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_PLLCFG_BYPASS_SHIFT 24</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_PLLCFG_FSE_SHIFT 25</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_PLLCFG_DIVR_MASK (0x03f << PRCI_PLLCFG_DIVR_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_PLLCFG_DIVF_MASK (0x1ff << PRCI_PLLCFG_DIVF_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_PLLCFG_DIVQ_MASK (0x007 << PRCI_PLLCFG_DIVQ_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_PLLCFG_RANGE_MASK (0x07 << PRCI_PLLCFG_RANGE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_PLLCFG_BYPASS_MASK (0x1 << PRCI_PLLCFG_BYPASS_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_PLLCFG_FSE_MASK (0x1 << PRCI_PLLCFG_FSE_SHIFT)</span><br><span> </span><br><span> #define PRCI_DDRPLLCFG1_MASK (1u << 31)</span><br><span> </span><br><span>@@ -78,6 +67,38 @@</span><br><span> #define PRCI_DEVICESRESET_DDR_PHY_RST_N(x) (((x) & 0x1) << 3)</span><br><span> #define PRCI_DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Clock initialization should only be done in romstage. */</span><br><span style="color: hsl(120, 100%, 40%);">+#if ENV_ROMSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+struct pll_settings {</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int divr:6;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int divf:9;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int divq:3;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int range:3;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int bypass:1;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int fse:1;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void configure_pll(u32 *reg, struct pll_settings *s)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ // Write the settings to the register</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c = read32(reg);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&c, PRCI_PLLCFG_DIVR_MASK</span><br><span style="color: hsl(120, 100%, 40%);">+ | PRCI_PLLCFG_DIVF_MASK | PRCI_PLLCFG_DIVQ_MASK</span><br><span style="color: hsl(120, 100%, 40%);">+ | PRCI_PLLCFG_RANGE_MASK | PRCI_PLLCFG_BYPASS_MASK</span><br><span style="color: hsl(120, 100%, 40%);">+ | PRCI_PLLCFG_FSE_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (s->divr << PRCI_PLLCFG_DIVR_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ | (s->divf << PRCI_PLLCFG_DIVF_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ | (s->divq << PRCI_PLLCFG_DIVQ_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ | (s->range << PRCI_PLLCFG_RANGE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ | (s->bypass << PRCI_PLLCFG_BYPASS_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ | (s->fse << PRCI_PLLCFG_FSE_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(reg, c);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Wait for PLL lock</span><br><span style="color: hsl(120, 100%, 40%);">+ while (!(read32(reg) & PRCI_PLLCFG_LOCK))</span><br><span style="color: hsl(120, 100%, 40%);">+ ; /* TODO: implement a timeout */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * Set coreclk according to the SiFive FU540-C000 Manual</span><br><span> * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/</span><br><span>@@ -88,13 +109,14 @@</span><br><span> * For example, to setup COREPLL for 1 GHz operation, program divr = 0 (x1),</span><br><span> * divf = 59 (4000 MHz VCO), divq = 2 (/4 Output divider)</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_CORECLK_DIVR 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_CORECLK_DIVF 59</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_CORECLK_DIVQ 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_CORECLK_RANGE 4</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_CORECLK_BYPASS 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_CORECLK_FSE 1</span><br><span style="color: hsl(120, 100%, 40%);">+static struct pll_settings corepll_settings = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .divr = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .divf = 59,</span><br><span style="color: hsl(120, 100%, 40%);">+ .divq = 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ .range = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bypass = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fse = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span> </span><br><span> /*</span><br><span> * Section 7.4.3: DDR and Ethernet Subsystem Clocking and Reset</span><br><span>@@ -110,41 +132,22 @@</span><br><span> * GEMGXLPLL is set up for 125 MHz output frequency.</span><br><span> * divr = 0, divf = 59 (4000 MHz VCO), divq = 5</span><br><span> */</span><br><span style="color: hsl(120, 100%, 40%);">+static struct pll_settings ddrpll_settings = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .divr = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .divf = 55,</span><br><span style="color: hsl(120, 100%, 40%);">+ .divq = 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ .range = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bypass = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fse = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRCLK_DIVR 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRCLK_DIVF 55</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRCLK_DIVQ 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRCLK_RANGE 4</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRCLK_BYPASS 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRCI_DDRCLK_FSE 1</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-// 33.33 Mhz after reset</span><br><span style="color: hsl(0, 100%, 40%);">-#define FU540_BASE_FQY 33330</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Clock initialization should only be done in romstage. */</span><br><span style="color: hsl(0, 100%, 40%);">-#if ENV_ROMSTAGE</span><br><span> static void init_coreclk(void)</span><br><span> {</span><br><span> // switch coreclk to input reference frequency before modifying PLL</span><br><span> clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK,</span><br><span> PRCI_CORECLK_HFCLK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- u32 c = read32(&prci->corepllcfg0);</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&c, PRCI_COREPLLCFG0_DIVR_MASK</span><br><span style="color: hsl(0, 100%, 40%);">- | PRCI_COREPLLCFG0_DIVF_MASK | PRCI_COREPLLCFG0_DIVQ_MASK</span><br><span style="color: hsl(0, 100%, 40%);">- | PRCI_COREPLLCFG0_RANGE_MASK | PRCI_COREPLLCFG0_BYPASS_MASK</span><br><span style="color: hsl(0, 100%, 40%);">- | PRCI_COREPLLCFG0_FSE_MASK,</span><br><span style="color: hsl(0, 100%, 40%);">- (PRCI_CORECLK_DIVR << PRCI_COREPLLCFG0_DIVR_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">- | (PRCI_CORECLK_DIVF << PRCI_COREPLLCFG0_DIVF_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">- | (PRCI_CORECLK_DIVQ << PRCI_COREPLLCFG0_DIVQ_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">- | (PRCI_CORECLK_RANGE << PRCI_COREPLLCFG0_RANGE_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">- | (PRCI_CORECLK_BYPASS << PRCI_COREPLLCFG0_BYPASS_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">- | (PRCI_CORECLK_FSE << PRCI_COREPLLCFG0_FSE_SHIFT));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&prci->corepllcfg0, c);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // wait for PLL lock</span><br><span style="color: hsl(0, 100%, 40%);">- while (!(read32(&prci->corepllcfg0) & PRCI_COREPLLCFG0_LOCK))</span><br><span style="color: hsl(0, 100%, 40%);">- ; /* TODO: implement a timeout */</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_pll(&prci->corepllcfg0, &corepll_settings);</span><br><span> </span><br><span> // switch coreclk to use corepll</span><br><span> clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK,</span><br><span>@@ -158,22 +161,7 @@</span><br><span> clrbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK);</span><br><span> write32(&prci->ddrpllcfg1, cfg1);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- u32 c = read32(&prci->ddrpllcfg0);</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&c, PRCI_DDRPLLCFG0_DIVR_MASK</span><br><span style="color: hsl(0, 100%, 40%);">- | PRCI_DDRPLLCFG0_DIVF_MASK | PRCI_DDRPLLCFG0_DIVQ_MASK</span><br><span style="color: hsl(0, 100%, 40%);">- | PRCI_DDRPLLCFG0_RANGE_MASK | PRCI_DDRPLLCFG0_BYPASS_MASK</span><br><span style="color: hsl(0, 100%, 40%);">- | PRCI_DDRPLLCFG0_FSE_MASK,</span><br><span style="color: hsl(0, 100%, 40%);">- (PRCI_DDRCLK_DIVR << PRCI_DDRPLLCFG0_DIVR_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">- | (PRCI_DDRCLK_DIVF << PRCI_DDRPLLCFG0_DIVF_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">- | (PRCI_DDRCLK_DIVQ << PRCI_DDRPLLCFG0_DIVQ_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">- | (PRCI_DDRCLK_RANGE << PRCI_DDRPLLCFG0_RANGE_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">- | (PRCI_DDRCLK_BYPASS << PRCI_DDRPLLCFG0_BYPASS_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">- | (PRCI_DDRCLK_FSE << PRCI_DDRPLLCFG0_FSE_SHIFT));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&prci->ddrpllcfg0, c);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // wait for PLL lock</span><br><span style="color: hsl(0, 100%, 40%);">- while (!(read32(&prci->ddrpllcfg0) & PRCI_DDRPLLCFG0_LOCK))</span><br><span style="color: hsl(0, 100%, 40%);">- ; /* TODO: implement a timeout */</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_pll(&prci->ddrpllcfg0, &ddrpll_settings);</span><br><span> </span><br><span> // enable ddr clock output</span><br><span> setbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK);</span><br><span>@@ -248,12 +236,12 @@</span><br><span> return FU540_BASE_FQY;</span><br><span> </span><br><span> u32 cfg = read32(&prci->corepllcfg0);</span><br><span style="color: hsl(0, 100%, 40%);">- u32 divr = (cfg & PRCI_COREPLLCFG0_DIVR_MASK)</span><br><span style="color: hsl(0, 100%, 40%);">- >> PRCI_COREPLLCFG0_DIVR_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 divf = (cfg & PRCI_COREPLLCFG0_DIVF_MASK)</span><br><span style="color: hsl(0, 100%, 40%);">- >> PRCI_COREPLLCFG0_DIVF_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 divq = (cfg & PRCI_COREPLLCFG0_DIVQ_MASK)</span><br><span style="color: hsl(0, 100%, 40%);">- >> PRCI_COREPLLCFG0_DIVQ_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 divr = (cfg & PRCI_PLLCFG_DIVR_MASK)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> PRCI_PLLCFG_DIVR_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 divf = (cfg & PRCI_PLLCFG_DIVF_MASK)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> PRCI_PLLCFG_DIVF_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 divq = (cfg & PRCI_PLLCFG_DIVQ_MASK)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> PRCI_PLLCFG_DIVQ_SHIFT;</span><br><span> </span><br><span> printk(BIOS_SPEW, "clk: r=%d f=%d q=%d\n", divr, divf, divq);</span><br><span> return FU540_BASE_FQY</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29356">change 29356</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29356"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab </div>
<div style="display:none"> Gerrit-Change-Number: 29356 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>