<p>Kane Chen <strong>uploaded patch set #2</strong> to this change.</p><p><a href="https://review.coreboot.org/29354">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Interface for updating Tcc in mainboard<br><br>This change provides an interface for mainboard to set Tcc before<br>BIOS reset complete happens in romstage.<br><br>With this change, we can add code to update Tcc in mainboard or<br>variants.<br><br>BUG=b:117789732<br><br>Change-Id: I287ba2b0001f0bef0b7a0d85b33f7d2df127f2db<br>Signed-off-by: Kane Chen <kane.chen@intel.com><br>---<br>M src/soc/intel/apollolake/include/soc/romstage.h<br>M src/soc/intel/apollolake/romstage.c<br>2 files changed, 9 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29354/2</pre><p>To view, visit <a href="https://review.coreboot.org/29354">change 29354</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29354"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newpatchset </div>
<div style="display:none"> Gerrit-Change-Id: I287ba2b0001f0bef0b7a0d85b33f7d2df127f2db </div>
<div style="display:none"> Gerrit-Change-Number: 29354 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Kane Chen <kane.chen@intel.com> </div>