<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29353">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl3: Add new mainboard variant mc_apl3<br><br>This mainboard is based on mc_apl1. In a first step, it concerns a copy<br>of mc_apl1 directory with minimum changes. Special adaptations for<br>mc_apl3 mainboard will follow in separate commits.<br><br>Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/mainboard/siemens/mc_apl1/Kconfig<br>M src/mainboard/siemens/mc_apl1/Kconfig.name<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c<br>6 files changed, 240 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29353/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig</span><br><span>index 783207c..ee86a4d 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/Kconfig</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/Kconfig</span><br><span>@@ -18,11 +18,13 @@</span><br><span> string</span><br><span> default "mc_apl1" if BOARD_SIEMENS_MC_APL1</span><br><span> default "mc_apl2" if BOARD_SIEMENS_MC_APL2</span><br><span style="color: hsl(120, 100%, 40%);">+ default "mc_apl3" if BOARD_SIEMENS_MC_APL3</span><br><span> </span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span> default "MC APL1" if BOARD_SIEMENS_MC_APL1</span><br><span> default "MC APL2" if BOARD_SIEMENS_MC_APL2</span><br><span style="color: hsl(120, 100%, 40%);">+ default "MC APL3" if BOARD_SIEMENS_MC_APL3</span><br><span> </span><br><span> config MAX_CPUS</span><br><span> int</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name</span><br><span>index 7f5f263..e1c2aa1 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/Kconfig.name</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/Kconfig.name</span><br><span>@@ -5,3 +5,7 @@</span><br><span> config BOARD_SIEMENS_MC_APL2</span><br><span> bool "-> MC APL2"</span><br><span> select BOARD_SIEMENS_BASEBOARD_MC_APL1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SIEMENS_MC_APL3</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "-> MC APL3"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_SIEMENS_BASEBOARD_MC_APL1</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..3c5a9fa</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_SIEMENS_MC_APL3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SIEMENS_MC_APL3_VAR</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVER_INTEL_I210</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_RX6110SA</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVER_SIEMENS_NC_FPGA</span><br><span style="color: hsl(120, 100%, 40%);">+ select NC_FPGA_NOTIFY_CB_READY</span><br><span style="color: hsl(120, 100%, 40%);">+ select APL_SKIP_SET_POWER_LIMITS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/mc_apl3/devicetree.cb"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_SIEMENS_MC_APL3</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..f3c87b2</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += mainboard.c</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..f3e8a77</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb</span><br><span>@@ -0,0 +1,119 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/apollolake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sci_irq" = "SCIS_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Disable unused clkreq of PCIe root ports</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[1]" = "2" # FPGA</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC TX DATA Delay 1</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-22.3.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for HS400, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for SDR104/HS200, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_tx_data_cntl1" = "0x0C16"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC TX DATA Delay 2</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-22.3.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [30:24] steps of delay for SDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [22:16] steps of delay for DDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for SDR25/HS50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for SDR12, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_tx_data_cntl2" = "0x28162828"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC RX CMD/DATA Delay 1</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-22.3.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [30:24] steps of delay for SDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [22:16] steps of delay for DDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for SDR25/HS50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for SDR12, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_rx_cmd_data_cntl1" = "0x00181717"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC RX CMD/DATA Delay 2</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-22.3.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [17:16] stands for Rx Clock before Output Buffer</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for HS200, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_rx_cmd_data_cntl2" = "0x10008"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # 0:HS400(Default), 1:HS200, 2:DDR50</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_host_max_speed" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Intel Common SoC Config</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Field | Value |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| I2C0 | Proximity Sensor |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "common_soc_config" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .i2c[0] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_STANDARD</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # - Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.1 off end # - DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.2 off end # - NPK</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # - Gen - Display</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.0 off end # - Iunit</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.0 on end # - P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.1 off end # - PMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.2 on end # - SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.3 off end # - Shared SRAM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0e.0 off end # - Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 11.0 on end # - ISH</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # - SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.2 off end # - RP 4 - PCIe-A 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.3 off end # - RP 5 - PCIe-A 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # - XHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 off end # - XDCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on # - I2C 0</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable external RTC chip</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/rx6110sa</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pmon_sampling" = "PMON_SAMPL_256_MS"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "bks_on" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "bks_off" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "iocut_en" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "set_user_date" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "user_year" = "04"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "user_month" = "07"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "user_day" = "01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "user_weekday" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 0x32 on end # RTC RX6110 SA</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # - I2C 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # - I2C 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # - I2C 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 off end # - I2C 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.1 off end # - I2C 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.2 off end # - I2C 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.3 on end # - I2C 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.0 on end # - UART 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.1 on end # - UART 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.2 on end # - UART 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.3 on end # - UART 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 off end # - SPI 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 off end # - SPI 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 off end # - SPI 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 off end # - PWM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 off end # - SDCARD</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # - eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 off end # - UFS</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 off end # - SDIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on end # - LPC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # - SMBUS</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..ccf3ab8</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c</span><br><span>@@ -0,0 +1,98 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Siemens AG</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootstate.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ops.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <hwilib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TX_DWORD3 0xa8c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void variant_mainboard_final(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PIR6 register mapping for PCIe root ports</span><br><span style="color: hsl(120, 100%, 40%);">+ * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write16(PID_ITSS, 0x314c, 0x0321);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, 0xd8, 0x3e);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable CLKRUN_EN for power gating LPC */</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc_enable_pci_clk_cntl();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2</span><br><span style="color: hsl(120, 100%, 40%);">+ * offset 0x341D bit3 and bit0.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2</span><br><span style="color: hsl(120, 100%, 40%);">+ * offset 0x341C bit [3:0].</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Correct the SATA transmit signal via the High Speed I/O Transmit</span><br><span style="color: hsl(120, 100%, 40%);">+ * Control Register 3.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Bit [23:16] set the output voltage swing for TX line.</span><br><span style="color: hsl(120, 100%, 40%);">+ * The value 0x4a sets the swing level to 0.58 V.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void wait_for_legacy_dev(void *unused)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t legacy_delay, us_since_boot;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct stopwatch sw;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Open main hwinfo block. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get legacy delay parameter from hwinfo. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(legacy_delay)) != sizeof(legacy_delay))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ us_since_boot = get_us_since_boot();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* No need to wait if the time since boot is already long enough.*/</span><br><span style="color: hsl(120, 100%, 40%);">+ if (us_since_boot > legacy_delay)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...",</span><br><span style="color: hsl(120, 100%, 40%);">+ legacy_delay - us_since_boot, legacy_delay);</span><br><span style="color: hsl(120, 100%, 40%);">+ stopwatch_wait_until_expired(&sw);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_NOTICE, "done!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void finalize_boot(void *unused)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set coreboot ready LED. */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_output(CNV_RGI_DT, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29353">change 29353</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29353"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791 </div>
<div style="display:none"> Gerrit-Change-Number: 29353 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>