<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29337">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Get rid of void pointer math<br><br>Pointer math with void pointers is illegal in many compilers, though it<br>works with GCC because it assumes size of void to be 1. Change the pointers<br>or add parenthesis to force a proper order that will not cause compile<br>errors if compiled with a different compiler, and more importantly, don't<br>have unsuspected side effects.<br><br>BUG=b:118484178<br>TEST=Build and boot grunt.<br><br>Change-Id: Ibfeb83893f09cb897d459856aff2a4ab2a74e6e5<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/northbridge.c<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 17 insertions(+), 15 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/29337/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>index a2ae52c..8d2e99f 100644</span><br><span>--- a/src/soc/amd/stoneyridge/northbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>@@ -182,20 +182,22 @@</span><br><span> </span><br><span> static unsigned long acpi_fill_hest(acpi_hest_t *hest)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- void *addr, *current;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *addr, *current;</span><br><span> </span><br><span> /* Skip the HEST header. */</span><br><span style="color: hsl(0, 100%, 40%);">- current = (void *)(hest + 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ current = (u8 *)(hest + 1);</span><br><span> </span><br><span> addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);</span><br><span> if (addr != NULL)</span><br><span style="color: hsl(0, 100%, 40%);">- current += acpi_create_hest_error_source(hest, current, 0,</span><br><span style="color: hsl(0, 100%, 40%);">- (void *)((u32)addr + 2), *(UINT16 *)addr - 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_hest_error_source(hest,</span><br><span style="color: hsl(120, 100%, 40%);">+ (acpi_hest_esd_t *)current, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (u8 *)((u32)addr + 2), *(UINT16 *)addr - 2);</span><br><span> </span><br><span> addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);</span><br><span> if (addr != NULL)</span><br><span style="color: hsl(0, 100%, 40%);">- current += acpi_create_hest_error_source(hest, current, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- (void *)((u32)addr + 2), *(UINT16 *)addr - 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_hest_error_source(hest,</span><br><span style="color: hsl(120, 100%, 40%);">+ (acpi_hest_esd_t *)current, 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (u8 *)((u32)addr + 2), *(UINT16 *)addr - 2);</span><br><span> </span><br><span> return (unsigned long)current;</span><br><span> }</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 326ea61..40f9cbe 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -429,27 +429,27 @@</span><br><span> void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)</span><br><span> {</span><br><span> uintptr_t base = sb_spibase();</span><br><span style="color: hsl(0, 100%, 40%);">- write16((void *)base + SPI100_SPEED_CONFIG,</span><br><span style="color: hsl(120, 100%, 40%);">+ write16((u16 *)((u8 *)base + SPI100_SPEED_CONFIG),</span><br><span> (norm << SPI_NORM_SPEED_NEW_SH) |</span><br><span> (fast << SPI_FAST_SPEED_NEW_SH) |</span><br><span> (alt << SPI_ALT_SPEED_NEW_SH) |</span><br><span> (tpm << SPI_TPM_SPEED_NEW_SH));</span><br><span style="color: hsl(0, 100%, 40%);">- write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100);</span><br><span style="color: hsl(120, 100%, 40%);">+ write16((u16 *)((u8 *)base + SPI100_ENABLE), SPI_USE_SPI100);</span><br><span> }</span><br><span> </span><br><span> void sb_disable_4dw_burst(void)</span><br><span> {</span><br><span> uintptr_t base = sb_spibase();</span><br><span style="color: hsl(0, 100%, 40%);">- write16((void *)base + SPI100_HOST_PREF_CONFIG,</span><br><span style="color: hsl(0, 100%, 40%);">- read16((void *)base + SPI100_HOST_PREF_CONFIG)</span><br><span style="color: hsl(120, 100%, 40%);">+ write16((u16 *)((u8 *)base + SPI100_HOST_PREF_CONFIG),</span><br><span style="color: hsl(120, 100%, 40%);">+ read16((u16 *)((u8 *)base + SPI100_HOST_PREF_CONFIG))</span><br><span> & ~SPI_RD4DW_EN_HOST);</span><br><span> }</span><br><span> </span><br><span> void sb_read_mode(u32 mode)</span><br><span> {</span><br><span> uintptr_t base = sb_spibase();</span><br><span style="color: hsl(0, 100%, 40%);">- write32((void *)base + SPI_CNTRL0,</span><br><span style="color: hsl(0, 100%, 40%);">- (read32((void *)base + SPI_CNTRL0)</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((u32 *)((u8 *)base + SPI_CNTRL0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (read32((u32 *)((u8 *)base + SPI_CNTRL0))</span><br><span> & ~SPI_READ_MODE_MASK) | mode);</span><br><span> }</span><br><span> </span><br><span>@@ -914,11 +914,11 @@</span><br><span> gnvs->aoac.espi = 1;</span><br><span> </span><br><span> amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX);</span><br><span style="color: hsl(0, 100%, 40%);">- xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET));</span><br><span style="color: hsl(120, 100%, 40%);">+ xhci_fw = read32((u32 *)((u8 *)amdfw_rom + XHCI_FW_SIG_OFFSET));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET</span><br><span style="color: hsl(120, 100%, 40%);">+ fwaddr = 2 + read16((u16 *)((u8 *)xhci_fw + XHCI_FW_ADDR_OFFSET</span><br><span> + XHCI_FW_BOOTRAM_SIZE));</span><br><span style="color: hsl(0, 100%, 40%);">- fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET</span><br><span style="color: hsl(120, 100%, 40%);">+ fwsize = read16((u16 *)((u8 *)xhci_fw + XHCI_FW_SIZE_OFFSET</span><br><span> + XHCI_FW_BOOTRAM_SIZE));</span><br><span> gnvs->fw00 = 0;</span><br><span> gnvs->fw01 = ((32 * KiB) << 16) + 0;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29337">change 29337</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibfeb83893f09cb897d459856aff2a4ab2a74e6e5 </div>
<div style="display:none"> Gerrit-Change-Number: 29337 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>