<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29301">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Remove unneeded include <reset.h><br><br>Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/arch/x86/cf9_reset.c<br>M src/cpu/amd/family_10h-family_15h/init_cpus.c<br>M src/cpu/amd/family_10h-family_15h/init_cpus.h<br>M src/cpu/intel/fsp_model_406dx/bootblock.c<br>M src/drivers/intel/fsp2_0/stage_cache.c<br>M src/ec/google/chromeec/ec.c<br>M src/lib/hardwaremain.c<br>M src/mainboard/google/foster/pmic.c<br>M src/mainboard/google/smaug/pmic.c<br>M src/mainboard/google/veyron/bootblock.c<br>M src/mainboard/google/veyron_mickey/bootblock.c<br>M src/mainboard/google/veyron_rialto/bootblock.c<br>M src/mainboard/intel/stargo2/romstage.c<br>M src/security/tpm/tspi/tspi.c<br>M src/security/vboot/common.c<br>M src/soc/cavium/common/bdk-coreboot.c<br>M src/soc/intel/braswell/romstage/romstage.c<br>M src/soc/intel/common/block/cpu/cpulib.c<br>M src/soc/intel/fsp_baytrail/bootblock/bootblock.c<br>M src/soc/intel/skylake/romstage/romstage.c<br>M src/southbridge/amd/agesa/hudson/early_setup.c<br>M src/southbridge/amd/pi/hudson/early_setup.c<br>M src/southbridge/amd/sb700/early_setup.c<br>23 files changed, 3 insertions(+), 20 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/29301/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c</span><br><span>index c28e448..d1e5704 100644</span><br><span>--- a/src/arch/x86/cf9_reset.c</span><br><span>+++ b/src/arch/x86/cf9_reset.c</span><br><span>@@ -18,7 +18,6 @@</span><br><span> #include <cf9_reset.h></span><br><span> #include <console/console.h></span><br><span> #include <halt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> </span><br><span> /*</span><br><span> * A system reset in terms of the CF9 register asserts the INIT#</span><br><span>diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c</span><br><span>index 1247e60..7f441c0 100644</span><br><span>--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c</span><br><span>+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <cpu/amd/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <reset.h></span><br><span> #include "init_cpus.h"</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)</span><br><span>diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h</span><br><span>index d4bff0b..ddae9a6 100644</span><br><span>--- a/src/cpu/amd/family_10h-family_15h/init_cpus.h</span><br><span>+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h</span><br><span>@@ -23,7 +23,6 @@</span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/amd/msr.h></span><br><span> #include <cpu/amd/multicore.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span> #include "defaults.h"</span><br><span> </span><br><span>diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c</span><br><span>index 327c4a4..e7b017f 100644</span><br><span>--- a/src/cpu/intel/fsp_model_406dx/bootblock.c</span><br><span>+++ b/src/cpu/intel/fsp_model_406dx/bootblock.c</span><br><span>@@ -21,7 +21,6 @@</span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <southbridge/intel/fsp_rangeley/soc.h></span><br><span> </span><br><span> #include "model_406dx.h"</span><br><span>diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c</span><br><span>index 434eae9..a9ec154 100644</span><br><span>--- a/src/drivers/intel/fsp2_0/stage_cache.c</span><br><span>+++ b/src/drivers/intel/fsp2_0/stage_cache.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #include <console/console.h></span><br><span> #include <fsp/memmap.h></span><br><span> #include <stage_cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <program_loading.h></span><br><span> </span><br><span> void stage_cache_external_region(void **base, size_t *size)</span><br><span>diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c</span><br><span>index 75d9da1..6efe139 100644</span><br><span>--- a/src/ec/google/chromeec/ec.c</span><br><span>+++ b/src/ec/google/chromeec/ec.c</span><br><span>@@ -25,7 +25,6 @@</span><br><span> #include <delay.h></span><br><span> #include <elog.h></span><br><span> #include <halt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <rtc.h></span><br><span> #include <stdlib.h></span><br><span> #include <security/vboot/vboot_common.h></span><br><span>diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c</span><br><span>index a26d678..05164b0 100644</span><br><span>--- a/src/lib/hardwaremain.c</span><br><span>+++ b/src/lib/hardwaremain.c</span><br><span>@@ -29,7 +29,6 @@</span><br><span> #include <device/pci.h></span><br><span> #include <delay.h></span><br><span> #include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <boot/tables.h></span><br><span> #include <program_loading.h></span><br><span> #include <lib.h></span><br><span>diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c</span><br><span>index 8d4f855..d8b1fa0 100644</span><br><span>--- a/src/mainboard/google/foster/pmic.c</span><br><span>+++ b/src/mainboard/google/foster/pmic.c</span><br><span>@@ -20,6 +20,7 @@</span><br><span> #include <device/i2c_simple.h></span><br><span> #include <stdint.h></span><br><span> #include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <reset.h></span><br><span> </span><br><span> #include "pmic.h"</span><br><span> #include "reset.h"</span><br><span>diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c</span><br><span>index 75075ad..a6e4574 100644</span><br><span>--- a/src/mainboard/google/smaug/pmic.c</span><br><span>+++ b/src/mainboard/google/smaug/pmic.c</span><br><span>@@ -20,6 +20,7 @@</span><br><span> #include <device/i2c_simple.h></span><br><span> #include <stdint.h></span><br><span> #include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <reset.h></span><br><span> </span><br><span> #include "pmic.h"</span><br><span> #include "reset.h"</span><br><span>diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c</span><br><span>index 1f4eec20..a36d9b0 100644</span><br><span>--- a/src/mainboard/google/veyron/bootblock.c</span><br><span>+++ b/src/mainboard/google/veyron/bootblock.c</span><br><span>@@ -19,7 +19,6 @@</span><br><span> #include <bootblock_common.h></span><br><span> #include <console/console.h></span><br><span> #include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <soc/clock.h></span><br><span> #include <soc/i2c.h></span><br><span> #include <soc/grf.h></span><br><span>diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c</span><br><span>index b95a265..73fd544 100644</span><br><span>--- a/src/mainboard/google/veyron_mickey/bootblock.c</span><br><span>+++ b/src/mainboard/google/veyron_mickey/bootblock.c</span><br><span>@@ -19,7 +19,6 @@</span><br><span> #include <bootblock_common.h></span><br><span> #include <console/console.h></span><br><span> #include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <soc/clock.h></span><br><span> #include <soc/i2c.h></span><br><span> #include <soc/grf.h></span><br><span>diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c</span><br><span>index dae046b..474f6ec 100644</span><br><span>--- a/src/mainboard/google/veyron_rialto/bootblock.c</span><br><span>+++ b/src/mainboard/google/veyron_rialto/bootblock.c</span><br><span>@@ -19,7 +19,6 @@</span><br><span> #include <bootblock_common.h></span><br><span> #include <console/console.h></span><br><span> #include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <soc/clock.h></span><br><span> #include <soc/i2c.h></span><br><span> #include <soc/grf.h></span><br><span>diff --git a/src/mainboard/intel/stargo2/romstage.c b/src/mainboard/intel/stargo2/romstage.c</span><br><span>index cdf087a..f5b84fd 100644</span><br><span>--- a/src/mainboard/intel/stargo2/romstage.c</span><br><span>+++ b/src/mainboard/intel/stargo2/romstage.c</span><br><span>@@ -25,7 +25,6 @@</span><br><span> #include <device/pnp_def.h></span><br><span> #include <cpu/x86/lapic.h></span><br><span> #include <halt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <fsp_util.h></span><br><span> #include <northbridge/intel/fsp_sandybridge/northbridge.h></span><br><span> #include <northbridge/intel/fsp_sandybridge/raminit.h></span><br><span>diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c</span><br><span>index d9cade9..33eaa06 100644</span><br><span>--- a/src/security/tpm/tspi/tspi.c</span><br><span>+++ b/src/security/tpm/tspi/tspi.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> </span><br><span> #include <console/cbmem_console.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <security/tpm/tspi.h></span><br><span> #include <security/tpm/tss.h></span><br><span> #include <stdlib.h></span><br><span>diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c</span><br><span>index 72228e4..a909312 100644</span><br><span>--- a/src/security/vboot/common.c</span><br><span>+++ b/src/security/vboot/common.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #include <cbfs.h></span><br><span> #include <cbmem.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <string.h></span><br><span> #include <vb2_api.h></span><br><span> #include <security/vboot/misc.h></span><br><span>diff --git a/src/soc/cavium/common/bdk-coreboot.c b/src/soc/cavium/common/bdk-coreboot.c</span><br><span>index ff30edf..b322a0c 100644</span><br><span>--- a/src/soc/cavium/common/bdk-coreboot.c</span><br><span>+++ b/src/soc/cavium/common/bdk-coreboot.c</span><br><span>@@ -23,7 +23,6 @@</span><br><span> #include <endian.h></span><br><span> #include <arch/io.h></span><br><span> #include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <soc/timer.h></span><br><span> </span><br><span> // BDK</span><br><span>diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c</span><br><span>index f485dfd..17d4074 100644</span><br><span>--- a/src/soc/intel/braswell/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/braswell/romstage/romstage.c</span><br><span>@@ -32,7 +32,6 @@</span><br><span> #include <romstage_handoff.h></span><br><span> #include <string.h></span><br><span> #include <timestamp.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span> #include <fsp/util.h></span><br><span> #include <soc/gpio.h></span><br><span>diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>index ebbdabd..8496536 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>+++ b/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #include <intelblocks/cpulib.h></span><br><span> #include <intelblocks/fast_spi.h></span><br><span> #include <lib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <soc/cpu.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/pm.h></span><br><span>diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c</span><br><span>index 8ce0a1d..81f5dfb 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c</span><br><span>@@ -25,7 +25,6 @@</span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/lpc.h></span><br><span> #include <soc/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> </span><br><span> /*</span><br><span> * check for a warm reset and do a hard reset instead.</span><br><span>diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c</span><br><span>index 215b07c..99a8957 100644</span><br><span>--- a/src/soc/intel/skylake/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/skylake/romstage/romstage.c</span><br><span>@@ -30,7 +30,6 @@</span><br><span> #include <elog.h></span><br><span> #include <intelblocks/fast_spi.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <romstage_handoff.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pei_wrapper.h></span><br><span>diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c</span><br><span>index 75da9dd..cfd6d0e 100644</span><br><span>--- a/src/southbridge/amd/agesa/hudson/early_setup.c</span><br><span>+++ b/src/southbridge/amd/agesa/hudson/early_setup.c</span><br><span>@@ -20,7 +20,6 @@</span><br><span> #include <arch/io.h></span><br><span> #include <arch/acpi.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <arch/cpu.h></span><br><span> #include <cbmem.h></span><br><span> #include "hudson.h"</span><br><span>diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c</span><br><span>index 47d20af..cd1ff85 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/early_setup.c</span><br><span>+++ b/src/southbridge/amd/pi/hudson/early_setup.c</span><br><span>@@ -21,7 +21,6 @@</span><br><span> #include <arch/io.h></span><br><span> #include <arch/acpi.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <arch/cpu.h></span><br><span> #include <cbmem.h></span><br><span> #include "hudson.h"</span><br><span>diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c</span><br><span>index a656921..011a056 100644</span><br><span>--- a/src/southbridge/amd/sb700/early_setup.c</span><br><span>+++ b/src/southbridge/amd/sb700/early_setup.c</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #include <console/console.h></span><br><span> #include <cpu/x86/msr.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include "sb700.h"</span><br><span> #include "smbus.h"</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29301">change 29301</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 </div>
<div style="display:none"> Gerrit-Change-Number: 29301 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>