<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29260">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Remove depreciated UPD selection<br><br>Sevel FSP silicon init UPD have been moved to memory init stage, modify<br>the coreboot accordingly. Those UPD is the following:<br>    SkipMpInit<br>    VtdBaseAddress<br>    VtdDisable<br>    X2ApicOptOut<br><br>BUG=N/A<br>TEST=Build pass with FSP revision 7.0.47.50.<br><br>Change-Id: Ic0416dcd9ea1fe063cdd0c2f27257cd4cb4ba7e8<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/fsp_params.c<br>1 file changed, 0 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/29260/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c</span><br><span>index 6167346..3314f6d 100644</span><br><span>--- a/src/soc/intel/cannonlake/fsp_params.c</span><br><span>+++ b/src/soc/intel/cannonlake/fsp_params.c</span><br><span>@@ -67,7 +67,6 @@</span><br><span> {</span><br><span>       int i;</span><br><span>       FSP_S_CONFIG *params = &supd->FspsConfig;</span><br><span style="color: hsl(0, 100%, 40%);">-        FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;</span><br><span>   struct device *dev = SA_DEV_ROOT;</span><br><span>    config_t *config = dev->chip_info;</span><br><span> </span><br><span>@@ -203,16 +202,12 @@</span><br><span> </span><br><span>        params->Heci3Enabled = config->Heci3Enabled;</span><br><span>   params->Device4Enable = config->Device4Enable;</span><br><span style="color: hsl(0, 100%, 40%);">-    params->SkipMpInit = !chip_get_fsp_mp_init();</span><br><span> </span><br><span>         /* VrConfig Settings for 5 domains</span><br><span>    * 0 = System Agent, 1 = IA Core, 2 = Ring,</span><br><span>   * 3 = GT unsliced,  4 = GT sliced */</span><br><span>        for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)</span><br><span>             fill_vr_domain_config(params, i, &config->domain_vr_config[i]);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-  /* Vt-D config */</span><br><span style="color: hsl(0, 100%, 40%);">-       tconfig->VtdDisable = config->VtdDisable;</span><br><span> }</span><br><span> </span><br><span> /* Mainboard GPIO Configuration */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29260">change 29260</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29260"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic0416dcd9ea1fe063cdd0c2f27257cd4cb4ba7e8 </div>
<div style="display:none"> Gerrit-Change-Number: 29260 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>