<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29251">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: Refine structure definitions of DDR driver<br><br>Remove unused members in emi_mpu_regs and sdram_params. Refine<br>mpu_ctrl_d as an array and fix the misuse.<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Kukui, and inits DRAM successfully with related<br>patches.<br><br>Change-Id: I95c002058dc5e1cba868334fecf8f42bd3e497e6<br>Signed-off-by: Huayang Duan <huayang.duan@mediatek.com><br>---<br>M src/soc/mediatek/mt8183/emi.c<br>M src/soc/mediatek/mt8183/include/soc/dramc_register.h<br>M src/soc/mediatek/mt8183/include/soc/emi.h<br>3 files changed, 10 insertions(+), 25 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29251/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c</span><br><span>index 78e0b28..286c872 100644</span><br><span>--- a/src/soc/mediatek/mt8183/emi.c</span><br><span>+++ b/src/soc/mediatek/mt8183/emi.c</span><br><span>@@ -54,7 +54,7 @@</span><br><span> row_bit = ((((emi_cona >> (24 - chn * 20 + rank)) & 0x01) << 2) +</span><br><span> ((emi_cona >> (12 + chn * 16 + rank * 2)) & 0x03)) + 13;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* data width (bytes) * 8 banks */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Data width (bytes) * 8 banks */</span><br><span> return ((u64)(1 << (row_bit + col_bit))) *</span><br><span> ((u64)(4 >> shift_for_16bit) * 8);</span><br><span> }</span><br><span>@@ -80,7 +80,7 @@</span><br><span> else</span><br><span> ch_rank0_size = (ch0_rank0_size * 256 << 20);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* dual rank enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Dual rank enable */</span><br><span> if ((emi_cona & (1 << 17)) != 0) {</span><br><span> if (ch0_rank1_size == 0)</span><br><span> ch_rank1_size = get_ch_rank_size(CHANNEL_A, RANK_1);</span><br><span>@@ -115,7 +115,7 @@</span><br><span> </span><br><span> for (int i = 0; i < RANK_MAX; i++) {</span><br><span> dram_size += rank_size[i];</span><br><span style="color: hsl(0, 100%, 40%);">- dramc_show("rank%d size:0x%llx\n", i, rank_size[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("Rank%d size:0x%llx\n", i, rank_size[i]);</span><br><span> }</span><br><span> </span><br><span> return dram_size;</span><br><span>@@ -126,7 +126,7 @@</span><br><span> u8 u4value = 0;</span><br><span> </span><br><span> /* CONA 17th bit 0: Disable dual rank mode</span><br><span style="color: hsl(0, 100%, 40%);">- * 1: Enable dual rank mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: Enable dual rank mode */</span><br><span> u4value = ((params->emi_cona_val & (0x1 << 17)) >> 17) ? 0 : 1;</span><br><span> clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 12, u4value << 12);</span><br><span> }</span><br><span>@@ -249,8 +249,8 @@</span><br><span> {</span><br><span> emi_esl_setting2();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 1, 0x1 << 4);</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 7, 0x1 << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4);</span><br><span> </span><br><span> write32(&emi_regs->bwct0, 0x0a000705);</span><br><span> write32(&emi_regs->bwct0_3rd, 0x0);</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h</span><br><span>index ac76e51..c88eaa0 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h</span><br><span>@@ -936,25 +936,12 @@</span><br><span> </span><br><span> struct emi_mpu_regs {</span><br><span> uint32_t mpu_ctrl;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t mpu_dbg;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t rsvd_2[62];</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t mpu_sa0;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t rsvd_3[63];</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t mpu_ea0;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t rsvd_4[63];</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t mpu_apc0;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t rsvd_5[319];</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t mpu_ctrl_d0;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t rsvd_6[63];</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t rg_mask_d0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd[511];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mpu_ctrl_d[16];</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-check_member(emi_mpu_regs, mpu_dbg, 0x0004);</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(emi_mpu_regs, mpu_sa0, 0x0100);</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(emi_mpu_regs, mpu_ea0, 0x0200);</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(emi_mpu_regs, mpu_apc0, 0x0300);</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(emi_mpu_regs, mpu_ctrl_d0, 0x0800);</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(emi_mpu_regs, rg_mask_d0, 0x0900);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_mpu_regs, mpu_ctrl, 0x0000);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800);</span><br><span> </span><br><span> enum {</span><br><span> TESTCHIP_DMA1_DMA_LP4MATAB_OPT_SHIFT = 12,</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h</span><br><span>index c3c8e81..22331ae 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/emi.h</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/emi.h</span><br><span>@@ -25,8 +25,6 @@</span><br><span> u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];</span><br><span> u8 cbt_cs[CHANNEL_MAX][RANK_MAX];</span><br><span> u8 cbt_mr12[CHANNEL_MAX][RANK_MAX];</span><br><span style="color: hsl(0, 100%, 40%);">- s8 clk_delay;</span><br><span style="color: hsl(0, 100%, 40%);">- s8 dqs_delay[CHANNEL_MAX];</span><br><span> u32 emi_cona_val;</span><br><span> u32 emi_conh_val;</span><br><span> u32 emi_conf_val;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29251">change 29251</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I95c002058dc5e1cba868334fecf8f42bd3e497e6 </div>
<div style="display:none"> Gerrit-Change-Number: 29251 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>