<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29252">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Replace common MSR addresses with macros<br><br>Change-Id: I9fba67be12483ea5e12ccd34c648735d409bc8b0<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/amd/family_10h-family_15h/fidvid.c<br>M src/cpu/amd/microcode/microcode.c<br>M src/cpu/x86/lapic/boot_cpu.c<br>M src/cpu/x86/smm/smmhandler.S<br>M src/include/cpu/x86/msr.h<br>M src/northbridge/amd/amdht/AsPsDefs.h<br>M src/northbridge/amd/amdht/h3finit.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c<br>9 files changed, 12 insertions(+), 21 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29252/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c</span><br><span>index 428924d..4846825 100644</span><br><span>--- a/src/cpu/amd/family_10h-family_15h/fidvid.c</span><br><span>+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c</span><br><span>@@ -89,6 +89,7 @@</span><br><span> </span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span> #include <cpu/amd/msr.h></span><br><span> #include <inttypes.h></span><br><span> #include <northbridge/amd/amdht/AsPsDefs.h></span><br><span>diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c</span><br><span>index 68b6953..8ee9006 100644</span><br><span>--- a/src/cpu/amd/microcode/microcode.c</span><br><span>+++ b/src/cpu/amd/microcode/microcode.c</span><br><span>@@ -126,7 +126,7 @@</span><br><span> UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);</span><br><span> </span><br><span> /* read the patch_id again */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(0x8b);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_BIOS_SIGN_ID);</span><br><span> new_patch_id = msr.lo;</span><br><span> </span><br><span> UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id,</span><br><span>diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c</span><br><span>index 7ba21fe..4654086 100644</span><br><span>--- a/src/cpu/x86/lapic/boot_cpu.c</span><br><span>+++ b/src/cpu/x86/lapic/boot_cpu.c</span><br><span>@@ -13,13 +13,14 @@</span><br><span> </span><br><span> #include <smp/node.h></span><br><span> #include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/lapic_def.h></span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_SMP)</span><br><span> int boot_cpu(void)</span><br><span> {</span><br><span> int bsp;</span><br><span> msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(0x1b);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(LAPIC_BASE_MSR);</span><br><span> bsp = !!(msr.lo & (1 << 8));</span><br><span> return bsp;</span><br><span> }</span><br><span>diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S</span><br><span>index 98d67d3..8f42acd 100644</span><br><span>--- a/src/cpu/x86/smm/smmhandler.S</span><br><span>+++ b/src/cpu/x86/smm/smmhandler.S</span><br><span>@@ -21,7 +21,7 @@</span><br><span> * to 64k if we can though.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define LAPIC_BASE_MSR 0x1b</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/lapic_def.h></span><br><span> </span><br><span> /*</span><br><span> * +--------------------------------+ 0xaffff</span><br><span>diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h</span><br><span>index 032ce4e..8a524dc 100644</span><br><span>--- a/src/include/cpu/x86/msr.h</span><br><span>+++ b/src/include/cpu/x86/msr.h</span><br><span>@@ -11,6 +11,7 @@</span><br><span> #define EFER_SCE (1 << 0)</span><br><span> </span><br><span> /* Page attribute type MSR */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TSC_MSR 0x10</span><br><span> #define IA32_PLATFORM_ID 0x17</span><br><span> #define IA32_FEATURE_CONTROL 0x3a</span><br><span> #define FEATURE_CONTROL_LOCK_BIT (1 << 0)</span><br><span>diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h</span><br><span>index 7e6a63d..30f4d75 100644</span><br><span>--- a/src/northbridge/amd/amdht/AsPsDefs.h</span><br><span>+++ b/src/northbridge/amd/amdht/AsPsDefs.h</span><br><span>@@ -18,9 +18,6 @@</span><br><span> #ifndef ASPSDEFS_H</span><br><span> #define ASPSDEFS_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define APIC_BAR 0x1b /* APIC_BAR register */</span><br><span style="color: hsl(0, 100%, 40%);">-#define APIC_BAR_BP 0x100 /* APIC_BAR BSP bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* P-state register offset */</span><br><span> #define PS_REG0 0 /* offset for P0 */</span><br><span> #define PS_REG1 1 /* offset for P1 */</span><br><span>@@ -237,7 +234,6 @@</span><br><span> #define DUAL_PLANE_NB_VID_OFF_MASK 0x3e0000/* for CPU rev <= C */</span><br><span> #define DUAL_PLANE_NB_VID_SHIFT 17/* for CPU rev <= C */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define NM_PS_REG (is_fam15h()?8:5) /* number of P-state MSR registers */</span><br><span> </span><br><span> /* sFidVidInit.outFlags defines */</span><br><span>@@ -259,7 +255,6 @@</span><br><span> #define VID_1_100V 0x12 /* 1.100V */</span><br><span> #define VID_1_175V 0x1E /* 1.175V */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Nb Fid Code */</span><br><span> #define NB_FID_800M 0x00 /* 800MHz */</span><br><span> </span><br><span>@@ -268,13 +263,9 @@</span><br><span> #define NB_DID_1 1</span><br><span> </span><br><span> /* GH Logical ID */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define GH_REV_A2 0x4 /* GH Rev A2 logical ID, Upper half */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define TSC_MSR 0x10</span><br><span> #define TSC_FREQ_SEL_SHIFT 24</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT)</span><br><span> </span><br><span> #define WAIT_PSTATE_TIMEOUT 80000000 /* 0.1 s , unit : 1.25 ns */</span><br><span>diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c</span><br><span>index 1e2d1a0..8a85734 100644</span><br><span>--- a/src/northbridge/amd/amdht/h3finit.c</span><br><span>+++ b/src/northbridge/amd/amdht/h3finit.c</span><br><span>@@ -29,6 +29,7 @@</span><br><span> </span><br><span> #include <device/pci.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/lapic_def.h></span><br><span> #include <cpu/amd/msr.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <device/pci_ids.h></span><br><span>@@ -42,10 +43,6 @@</span><br><span> *----------------------------------------------------------------------------</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* APIC defines from amdgesa.inc, which can't be included in to c code. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define APIC_Base_BSP 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define APIC_Base 0x1b</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define NVRAM_LIMIT_HT_SPEED_200 0x12</span><br><span> #define NVRAM_LIMIT_HT_SPEED_300 0x11</span><br><span> #define NVRAM_LIMIT_HT_SPEED_400 0x10</span><br><span>@@ -1831,9 +1828,9 @@</span><br><span> {</span><br><span> uint64 qValue;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- AmdMSRRead(APIC_Base, &qValue);</span><br><span style="color: hsl(120, 100%, 40%);">+ AmdMSRRead(LAPIC_BASE_MSR, &qValue);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- return ((qValue.lo & ((u32)1 << APIC_Base_BSP)) != 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ return ((qValue.lo & LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR) != 0);</span><br><span> }</span><br><span> </span><br><span> /***************************************************************************</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c</span><br><span>index b94c68c..b4d1241 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c</span><br><span>@@ -2364,10 +2364,10 @@</span><br><span> uint64_t start_timestamp;</span><br><span> uint64_t current_timestamp;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- tsc_msr = rdmsr(0x00000010);</span><br><span style="color: hsl(120, 100%, 40%);">+ tsc_msr = rdmsr(TSC_MSR);</span><br><span> start_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo;</span><br><span> do {</span><br><span style="color: hsl(0, 100%, 40%);">- tsc_msr = rdmsr(0x00000010);</span><br><span style="color: hsl(120, 100%, 40%);">+ tsc_msr = rdmsr(TSC_MSR);</span><br><span> current_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo;</span><br><span> } while ((current_timestamp - start_timestamp) < cycle_count);</span><br><span> }</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c</span><br><span>index 1db1b54..42627e8 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c</span><br><span>@@ -2427,7 +2427,7 @@</span><br><span> </span><br><span> cycles <<= 3; /* x8 (number of 1.25ns ticks) */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = 0x10; /* TSC */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = TSC_MSR; /* TSC */</span><br><span> _RDMSR(msr, &lo, &hi);</span><br><span> saved = lo;</span><br><span> do {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29252">change 29252</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9fba67be12483ea5e12ccd34c648735d409bc8b0 </div>
<div style="display:none"> Gerrit-Change-Number: 29252 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>