<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29258">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: SMBUS access through MMIO<br><br>Currently SMBUS registers are accessed through IO, but with stoneyridge<br>they can be accessed through MMIO. This reduces the time of execution by<br>a tiny amount (MMIO write is faster than IO write, though MMIO read is about<br>as fast as IO read) as most of the time consumed is actually transaction<br>time. Create a CONFIG parameter, so user can decide if they want to use IO<br>(default) or MMIO when accessing SMBUS.<br><br>BUG=b:117754784<br>TEST=<br><br>Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/Kconfig<br>M src/soc/amd/stoneyridge/include/soc/iomap.h<br>M src/soc/amd/stoneyridge/include/soc/smbus.h<br>M src/soc/amd/stoneyridge/smbus.c<br>4 files changed, 39 insertions(+), 22 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29258/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig</span><br><span>index 4411984..44295d4 100644</span><br><span>--- a/src/soc/amd/stoneyridge/Kconfig</span><br><span>+++ b/src/soc/amd/stoneyridge/Kconfig</span><br><span>@@ -385,4 +385,11 @@</span><br><span> return to S0. Otherwise the system will remain in S5 once power</span><br><span> is restored.</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config STONEYRIDGE_MMIO_SMBUS</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Set this option to y to access SMBUS registers through MMIO.</span><br><span style="color: hsl(120, 100%, 40%);">+ Otherwise it'll use standard IO access.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h</span><br><span>index 3e86564..0503052 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/iomap.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h</span><br><span>@@ -37,6 +37,7 @@</span><br><span> #define APU_SMI_BASE 0xfed80200</span><br><span> #define PM_MMIO_BASE 0xfed80300</span><br><span> #define BIOSRAM_MMIO_BASE 0xfed80500</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMBUS_MMIO_BASE 0xfed80a00</span><br><span> #define GPIO_IOMUX_MMIO_BASE 0xfed80d00</span><br><span> #define MISC_MMIO_BASE 0xfed80e00</span><br><span> #define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h</span><br><span>index 1bb4346..58ee1c7 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/smbus.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/smbus.h</span><br><span>@@ -19,6 +19,15 @@</span><br><span> #include <stdint.h></span><br><span> #include <soc/iomap.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_STONEYRIDGE_MMIO_SMBUS)</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SMB_RD(base, reg) read8((void *)SMBUS_MMIO_BASE + reg)</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SMB_WR(value, base, reg) write8((void *)SMBUS_MMIO_BASE + reg, \</span><br><span style="color: hsl(120, 100%, 40%);">+ value)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SMB_RD(base, reg) inb(base + reg)</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SMB_WR(value, base, reg) outb(value, base + reg)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define SMBHSTSTAT 0x0</span><br><span> #define SMBHST_STAT_FAILED 0x10</span><br><span> #define SMBHST_STAT_COLLISION 0x08</span><br><span>diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c</span><br><span>index 919a52e..9d1b899 100644</span><br><span>--- a/src/soc/amd/stoneyridge/smbus.c</span><br><span>+++ b/src/soc/amd/stoneyridge/smbus.c</span><br><span>@@ -23,12 +23,12 @@</span><br><span> loops = SMBUS_TIMEOUT;</span><br><span> do {</span><br><span> u8 val;</span><br><span style="color: hsl(0, 100%, 40%);">- val = inb(smbus_io_base + SMBHSTSTAT);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = SMB_RD(smbus_io_base, SMBHSTSTAT);</span><br><span> val &= SMBHST_STAT_VAL_BITS;</span><br><span> if (val == 0) { /* ready now */</span><br><span> return 0;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- outb(val, smbus_io_base + SMBHSTSTAT);</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(val, smbus_io_base, SMBHSTSTAT);</span><br><span> } while (--loops);</span><br><span> return -2; /* time out */</span><br><span> }</span><br><span>@@ -40,12 +40,12 @@</span><br><span> do {</span><br><span> u8 val;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- val = inb(smbus_io_base + SMBHSTSTAT);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = SMB_RD(smbus_io_base, SMBHSTSTAT);</span><br><span> val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */</span><br><span> if (val & SMBHST_STAT_ERROR_BITS)</span><br><span> return -5; /* error */</span><br><span> if (val == SMBHST_STAT_NOERROR) {</span><br><span style="color: hsl(0, 100%, 40%);">- outb(val, smbus_io_base + SMBHSTSTAT); /* clear sts */</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(val, smbus_io_base, SMBHSTSTAT); /* clear sts */</span><br><span> return 0;</span><br><span> }</span><br><span> } while (--loops);</span><br><span>@@ -60,19 +60,19 @@</span><br><span> return -2; /* not ready */</span><br><span> </span><br><span> /* set the device I'm talking to */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(((device & 0x7f) << 1) | 1, smbus_io_base, SMBHSTADDR);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- byte = inb(smbus_io_base + SMBHSTCTRL);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = SMB_RD(smbus_io_base, SMBHSTCTRL);</span><br><span> byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */</span><br><span> byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(byte, smbus_io_base + SMBHSTCTRL);</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(byte, smbus_io_base, SMBHSTCTRL);</span><br><span> </span><br><span> /* poll for transaction completion */</span><br><span> if (smbus_wait_until_done(smbus_io_base) < 0)</span><br><span> return -3; /* timeout or error */</span><br><span> </span><br><span> /* read results of transaction */</span><br><span style="color: hsl(0, 100%, 40%);">- byte = inb(smbus_io_base + SMBHSTDAT0);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = SMB_RD(smbus_io_base, SMBHSTDAT0);</span><br><span> </span><br><span> return byte;</span><br><span> }</span><br><span>@@ -85,15 +85,15 @@</span><br><span> return -2; /* not ready */</span><br><span> </span><br><span> /* set the command... */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(val, smbus_io_base + SMBHSTDAT0);</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(val, smbus_io_base, SMBHSTDAT0);</span><br><span> </span><br><span> /* set the device I'm talking to */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(((device & 0x7f) << 1) | 0, smbus_io_base, SMBHSTADDR);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- byte = inb(smbus_io_base + SMBHSTCTRL);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = SMB_RD(smbus_io_base, SMBHSTCTRL);</span><br><span> byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */</span><br><span> byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(byte, smbus_io_base + SMBHSTCTRL);</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(byte, smbus_io_base, SMBHSTCTRL);</span><br><span> </span><br><span> /* poll for transaction completion */</span><br><span> if (smbus_wait_until_done(smbus_io_base) < 0)</span><br><span>@@ -110,22 +110,22 @@</span><br><span> return -2; /* not ready */</span><br><span> </span><br><span> /* set the command/address... */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(address & 0xff, smbus_io_base + SMBHSTCMD);</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(address & 0xff, smbus_io_base, SMBHSTCMD);</span><br><span> </span><br><span> /* set the device I'm talking to */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(((device & 0x7f) << 1) | 1, smbus_io_base, SMBHSTADDR);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- byte = inb(smbus_io_base + SMBHSTCTRL);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = SMB_RD(smbus_io_base, SMBHSTCTRL);</span><br><span> byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */</span><br><span> byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(byte, smbus_io_base + SMBHSTCTRL);</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(byte, smbus_io_base, SMBHSTCTRL);</span><br><span> </span><br><span> /* poll for transaction completion */</span><br><span> if (smbus_wait_until_done(smbus_io_base) < 0)</span><br><span> return -3; /* timeout or error */</span><br><span> </span><br><span> /* read results of transaction */</span><br><span style="color: hsl(0, 100%, 40%);">- byte = inb(smbus_io_base + SMBHSTDAT0);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = SMB_RD(smbus_io_base, SMBHSTDAT0);</span><br><span> </span><br><span> return byte;</span><br><span> }</span><br><span>@@ -138,18 +138,18 @@</span><br><span> return -2; /* not ready */</span><br><span> </span><br><span> /* set the command/address... */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(address & 0xff, smbus_io_base + SMBHSTCMD);</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(address & 0xff, smbus_io_base, SMBHSTCMD);</span><br><span> </span><br><span> /* set the device I'm talking to */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(((device & 0x7f) << 1) | 0, smbus_io_base, SMBHSTADDR);</span><br><span> </span><br><span> /* output value */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(val, smbus_io_base + SMBHSTDAT0);</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(val, smbus_io_base, SMBHSTDAT0);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- byte = inb(smbus_io_base + SMBHSTCTRL);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = SMB_RD(smbus_io_base, SMBHSTCTRL);</span><br><span> byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */</span><br><span> byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(byte, smbus_io_base + SMBHSTCTRL);</span><br><span style="color: hsl(120, 100%, 40%);">+ SMB_WR(byte, smbus_io_base, SMBHSTCTRL);</span><br><span> </span><br><span> /* poll for transaction completion */</span><br><span> if (smbus_wait_until_done(smbus_io_base) < 0)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29258">change 29258</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29258"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8 </div>
<div style="display:none"> Gerrit-Change-Number: 29258 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>