<p>Philipp Deppenwiese <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/29060">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Aaron Durbin: Looks good to me, approved
Philipp Deppenwiese: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic<br><br>- should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag<br>- implement vboot_platform_is_resuming on platforms missing it<br>- add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges<br><br>[ originally https://review.coreboot.org/c/coreboot/+/28750 ]<br><br>BUG=b:114018226<br>TEST=compile coreboot<br><br>Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9<br>Signed-off-by: Joel Kitching <kitching@google.com><br>Reviewed-on: https://review.coreboot.org/29060<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Aaron Durbin <adurbin@chromium.org><br>Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com><br>---<br>M src/security/vboot/vboot_logic.c<br>M src/soc/intel/baytrail/pmutil.c<br>M src/soc/intel/braswell/pmutil.c<br>M src/soc/intel/broadwell/pmutil.c<br>M src/soc/intel/fsp_baytrail/romstage/romstage.c<br>M src/southbridge/intel/common/pmbase.c<br>M src/southbridge/intel/common/pmutil.h<br>M src/southbridge/intel/i82371eb/Kconfig<br>M src/southbridge/intel/i82801jx/Kconfig<br>9 files changed, 53 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c</span><br><span>index f3a6b41..1b24160 100644</span><br><span>--- a/src/security/vboot/vboot_logic.c</span><br><span>+++ b/src/security/vboot/vboot_logic.c</span><br><span>@@ -309,7 +309,6 @@</span><br><span> * does verification of memory init and thus must ensure it resumes with</span><br><span> * the same slot that it booted from. */</span><br><span> if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&</span><br><span style="color: hsl(0, 100%, 40%);">- IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) &&</span><br><span> vboot_platform_is_resuming())</span><br><span> ctx.flags |= VB2_CONTEXT_S3_RESUME;</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c</span><br><span>index 51c3ea0..06751f1 100644</span><br><span>--- a/src/soc/intel/baytrail/pmutil.c</span><br><span>+++ b/src/soc/intel/baytrail/pmutil.c</span><br><span>@@ -14,6 +14,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <cbmem.h></span><br><span> #include <console/console.h></span><br><span>@@ -23,6 +24,7 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pmc.h></span><br><span> #include <security/vboot/vbnv.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> </span><br><span> #if defined(__SIMPLE_DEVICE__)</span><br><span> </span><br><span>@@ -384,3 +386,11 @@</span><br><span> {</span><br><span> return rtc_failure();</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c</span><br><span>index 00284d1..85384a61 100644</span><br><span>--- a/src/soc/intel/braswell/pmutil.c</span><br><span>+++ b/src/soc/intel/braswell/pmutil.c</span><br><span>@@ -14,6 +14,7 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <cbmem.h></span><br><span> #include <console/console.h></span><br><span>@@ -24,6 +25,7 @@</span><br><span> #include <soc/pm.h></span><br><span> #include <stdint.h></span><br><span> #include <security/vboot/vbnv.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> </span><br><span> #if defined(__SIMPLE_DEVICE__)</span><br><span> </span><br><span>@@ -380,3 +382,11 @@</span><br><span> {</span><br><span> return rtc_failure();</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c</span><br><span>index 3899130..e19025b 100644</span><br><span>--- a/src/soc/intel/broadwell/pmutil.c</span><br><span>+++ b/src/soc/intel/broadwell/pmutil.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> * and the differences between PCH variants.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span>@@ -29,6 +30,7 @@</span><br><span> #include <soc/pm.h></span><br><span> #include <soc/gpio.h></span><br><span> #include <security/vboot/vbnv.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> </span><br><span> /* Print status bits with descriptive names */</span><br><span> static void print_status_bits(u32 status, const char *bit_names[])</span><br><span>@@ -473,3 +475,11 @@</span><br><span> {</span><br><span> return rtc_failure();</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c</span><br><span>index f8d985e..fb5962e 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c</span><br><span>@@ -39,6 +39,7 @@</span><br><span> #include <version.h></span><br><span> #include <pc80/mc146818rtc.h></span><br><span> #include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> </span><br><span> /* Return 0, 3, 4 or 5 to indicate the previous sleep state. */</span><br><span> uint32_t chipset_prev_sleep_state(uint32_t clear)</span><br><span>@@ -271,3 +272,8 @@</span><br><span> {</span><br><span> return 0;</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!romstage_handoff_is_resume();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c</span><br><span>index 360b63d..2de57d6 100644</span><br><span>--- a/src/southbridge/intel/common/pmbase.c</span><br><span>+++ b/src/southbridge/intel/common/pmbase.c</span><br><span>@@ -14,13 +14,16 @@</span><br><span> */</span><br><span> </span><br><span> #include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <arch/early_variables.h></span><br><span> #include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> </span><br><span> #include "pmbase.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "pmutil.h"</span><br><span> </span><br><span> /* LPC PM Base Address Register */</span><br><span> #define PMBASE 0x40</span><br><span>@@ -91,3 +94,13 @@</span><br><span> </span><br><span> return inb(lpc_get_pmbase() + addr);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 reg16 = read_pmbase16(PM1_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(reg16 & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(reg16) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h</span><br><span>index 273e0f8..26134d9 100644</span><br><span>--- a/src/southbridge/intel/common/pmutil.h</span><br><span>+++ b/src/southbridge/intel/common/pmutil.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef INTEL_COMMON_PMUTIL_H</span><br><span> #define INTEL_COMMON_PMUTIL_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define D31F0_PMBASE 0x40</span><br><span> #define D31F0_GEN_PMCON_3 0xa4</span><br><span> #define D31F0_GPIO_ROUT 0xb8</span><br><span>diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig</span><br><span>index f22c6e9..6552099 100644</span><br><span>--- a/src/southbridge/intel/i82371eb/Kconfig</span><br><span>+++ b/src/southbridge/intel/i82371eb/Kconfig</span><br><span>@@ -1,4 +1,5 @@</span><br><span> config SOUTHBRIDGE_INTEL_I82371EB</span><br><span style="color: hsl(120, 100%, 40%);">+ select ACPI_INTEL_HARDWARE_SLEEP_VALUES</span><br><span> select SOUTHBRIDGE_INTEL_COMMON</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_SMBUS</span><br><span> bool</span><br><span>diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig</span><br><span>index e56d692..4308e29 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/Kconfig</span><br><span>+++ b/src/southbridge/intel/i82801jx/Kconfig</span><br><span>@@ -28,6 +28,7 @@</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_GPIO</span><br><span> select INTEL_DESCRIPTOR_MODE_CAPABLE</span><br><span> select COMMON_FADT</span><br><span style="color: hsl(120, 100%, 40%);">+ select ACPI_INTEL_HARDWARE_SLEEP_VALUES</span><br><span> </span><br><span> if SOUTHBRIDGE_INTEL_I82801JX</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29060">change 29060</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 </div>
<div style="display:none"> Gerrit-Change-Number: 29060 </div>
<div style="display:none"> Gerrit-PatchSet: 8 </div>
<div style="display:none"> Gerrit-Owner: Joel Kitching <kitching@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Joel Kitching <kitching@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>