<p>Peter Lemenkov has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29236">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel: Use common RCBA MACROs<br><br>This commit is a followup to commit 2e464cf3 with Change-Id<br>I61fb3b01ff15ba2da2ee938addfa630c282c9870.<br><br>Also it adds RCBA64 macro.<br><br>Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba<br>Signed-off-by: Peter Lemenkov <lemenkov@gmail.com><br>---<br>M src/southbridge/intel/bd82x6x/pch.h<br>M src/southbridge/intel/common/rcba.h<br>M src/southbridge/intel/fsp_bd82x6x/pch.h<br>M src/southbridge/intel/fsp_i89xx/pch.h<br>M src/southbridge/intel/fsp_rangeley/soc.h<br>M src/southbridge/intel/i82801gx/i82801gx.h<br>M src/southbridge/intel/i82801ix/early_init.c<br>M src/southbridge/intel/i82801ix/i82801ix.h<br>M src/southbridge/intel/i82801jx/bootblock.c<br>M src/southbridge/intel/i82801jx/i82801jx.h<br>M src/southbridge/intel/ibexpeak/pch.h<br>M src/southbridge/intel/lynxpoint/pch.h<br>12 files changed, 11 insertions(+), 92 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29236/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>index e234ca0..112c0b2 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>@@ -265,9 +265,6 @@</span><br><span> </span><br><span> #define PMBASE 0x40</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Root Complex Register Block */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA 0xf0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define VCH 0x0000 /* 32bit */</span><br><span> #define VCAP1 0x0004 /* 32bit */</span><br><span> #define VCAP2 0x0008 /* 32bit */</span><br><span>diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h</span><br><span>index b6cba8e..ef5e489 100644</span><br><span>--- a/src/southbridge/intel/common/rcba.h</span><br><span>+++ b/src/southbridge/intel/common/rcba.h</span><br><span>@@ -25,9 +25,14 @@</span><br><span> </span><br><span> #ifndef __ACPI__</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Root Complex Register Block */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA 0xf0</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA_ENABLE 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x)))</span><br><span> #define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x)))</span><br><span> #define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x)))</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA64(x) (*((volatile u64 *)(DEFAULT_RCBA + x)))</span><br><span> </span><br><span> #define RCBA_AND_OR(bits, x, and, or) \</span><br><span> (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)))</span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h</span><br><span>index 1f1c18a..20a4318 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/pch.h</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/pch.h</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #define SOUTHBRIDGE_INTEL_FSP_BD82X6X_PCH_H</span><br><span> </span><br><span> #include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> /* PCH types */</span><br><span> #define PCH_TYPE_CPT 0x1c /* CougarPoint */</span><br><span>@@ -47,12 +48,6 @@</span><br><span> #define DEFAULT_PMBASE 0x0400</span><br><span> </span><br><span> #ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA ((u8 *)0xfed1c000)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span> #define DEBUG_PERIODIC_SMIS 0</span><br><span> </span><br><span> #if defined(__SMM__) && !defined(__ASSEMBLER__)</span><br><span>@@ -263,20 +258,6 @@</span><br><span> </span><br><span> #define PMBASE 0x40</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Root Complex Register Block */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA 0xf0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA_AND_OR(bits, x, and, or) \</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define VCH 0x0000 /* 32bit */</span><br><span> #define VCAP1 0x0004 /* 32bit */</span><br><span> #define VCAP2 0x0008 /* 32bit */</span><br><span>diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h</span><br><span>index 3382cbd..2757f7d 100644</span><br><span>--- a/src/southbridge/intel/fsp_i89xx/pch.h</span><br><span>+++ b/src/southbridge/intel/fsp_i89xx/pch.h</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #define SOUTHBRIDGE_INTEL_I89XX_PCH_H</span><br><span> </span><br><span> #include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> /* PCH types */</span><br><span> #define PCH_TYPE_CC 0x23 /* CaveCreek */</span><br><span>@@ -46,12 +47,6 @@</span><br><span> #define DEFAULT_PMBASE 0x0400</span><br><span> </span><br><span> #ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA ((u8 *)0xfed1c000)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span> #define DEBUG_PERIODIC_SMIS 0</span><br><span> </span><br><span> #if defined(__SMM__) && !defined(__ASSEMBLER__)</span><br><span>@@ -180,20 +175,6 @@</span><br><span> </span><br><span> #define PMBASE 0x40</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Root Complex Register Block */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA 0xf0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA_AND_OR(bits, x, and, or) \</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define V0CTL 0x0014 /* 32bit */</span><br><span> #define V0STS 0x001a /* 16bit */</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h</span><br><span>index 0917201..cad5d57 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/soc.h</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/soc.h</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #define SOUTHBRIDGE_INTEL_RANGELEY_SOC_H</span><br><span> </span><br><span> #include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> /* SOC types */</span><br><span> #define SOC_TYPE_RANGELEY 0x1F</span><br><span>@@ -41,11 +42,6 @@</span><br><span> /* Southbridge internal device MEM BARs (Set to match FSP settings) */</span><br><span> #define DEFAULT_IBASE 0xfed08000</span><br><span> #define DEFAULT_PBASE 0xfed03000</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA ((u8 *)0xfed1c000)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> </span><br><span> #ifndef __ACPI__</span><br><span> #define DEBUG_PERIODIC_SMIS 0</span><br><span>@@ -176,21 +172,6 @@</span><br><span> #define SMB_SMI_EN (1 << 1)</span><br><span> #define HST_EN (1 << 0)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Root Complex Register Block */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA 0xf0</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA_ENABLE 0x01</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA_AND_OR(bits, x, and, or) \</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Root Port configuration space hide */</span><br><span> #define RPFN_HIDE(port) (1 << (((port) * 4) + 3))</span><br><span> /* Get the function number assigned to a Root Port */</span><br><span>diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>index d14a809..c0b6637 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>+++ b/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>@@ -187,9 +187,6 @@</span><br><span> </span><br><span> #define PMBASE 0x40</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Root Complex Register Block */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA 0xf0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define VCH 0x0000 /* 32bit */</span><br><span> #define VCAP1 0x0004 /* 32bit */</span><br><span> #define VCAP2 0x0008 /* 32bit */</span><br><span>diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c</span><br><span>index 7c4dafa..96c34c1 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/early_init.c</span><br><span>+++ b/src/southbridge/intel/i82801ix/early_init.c</span><br><span>@@ -33,7 +33,7 @@</span><br><span> const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);</span><br><span> </span><br><span> /* Set up RCBA. */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1);</span><br><span> </span><br><span> /* Set up PMBASE. */</span><br><span> pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);</span><br><span>diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h</span><br><span>index aed1999..456ac8a 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/i82801ix.h</span><br><span>+++ b/src/southbridge/intel/i82801ix/i82801ix.h</span><br><span>@@ -116,7 +116,6 @@</span><br><span> #define D31F0_CxSTATE_CNF 0xa9</span><br><span> #define D31F0_C4TIMING_CNT 0xaa</span><br><span> #define D31F0_GPIO_ROUT 0xb8</span><br><span style="color: hsl(0, 100%, 40%);">-#define D31F0_RCBA 0xf0</span><br><span> </span><br><span> /* GEN_PMCON_3 bits */</span><br><span> #define RTC_BATTERY_DEAD (1 << 2)</span><br><span>diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c</span><br><span>index 115555c..6380e4f 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/bootblock.c</span><br><span>+++ b/src/southbridge/intel/i82801jx/bootblock.c</span><br><span>@@ -48,6 +48,6 @@</span><br><span> enable_spi_prefetch();</span><br><span> </span><br><span> /* Enable RCBA */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA,</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA,</span><br><span> (uintptr_t)DEFAULT_RCBA | 1);</span><br><span> }</span><br><span>diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h</span><br><span>index 3c09746..8d98db1 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/i82801jx.h</span><br><span>+++ b/src/southbridge/intel/i82801jx/i82801jx.h</span><br><span>@@ -119,7 +119,6 @@</span><br><span> #define D31F0_CxSTATE_CNF 0xa9</span><br><span> #define D31F0_C4TIMING_CNT 0xaa</span><br><span> #define D31F0_GPIO_ROUT 0xb8</span><br><span style="color: hsl(0, 100%, 40%);">-#define D31F0_RCBA 0xf0</span><br><span> </span><br><span> /* GEN_PMCON_3 bits */</span><br><span> #define RTC_BATTERY_DEAD (1 << 2)</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>index 55478b9..216955a 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/pch.h</span><br><span>+++ b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>@@ -235,9 +235,6 @@</span><br><span> </span><br><span> #define PMBASE 0x40</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Root Complex Register Block */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA 0xf0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define VCH 0x0000 /* 32bit */</span><br><span> #define VCAP1 0x0004 /* 32bit */</span><br><span> #define VCAP2 0x0008 /* 32bit */</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h</span><br><span>index 489b565..0b673fa 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pch.h</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pch.h</span><br><span>@@ -18,6 +18,7 @@</span><br><span> #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H</span><br><span> </span><br><span> #include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #define CROS_GPIO_DEVICE_NAME "LynxPoint"</span><br><span> </span><br><span>@@ -83,11 +84,6 @@</span><br><span> #endif</span><br><span> </span><br><span> #define HPET_ADDR 0xfed00000</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA ((u8 *)0xfed1c000)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> </span><br><span> #ifndef __ACPI__</span><br><span> </span><br><span>@@ -484,20 +480,6 @@</span><br><span> </span><br><span> #define PMBASE 0x40</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Root Complex Register Block */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA 0xf0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA_AND_OR(bits, x, and, or) \</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define VCH 0x0000 /* 32bit */</span><br><span> #define VCAP1 0x0004 /* 32bit */</span><br><span> #define VCAP2 0x0008 /* 32bit */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29236">change 29236</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba </div>
<div style="display:none"> Gerrit-Change-Number: 29236 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Peter Lemenkov <lemenkov@gmail.com> </div>