<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29228">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Fix 80+ characters lines<br><br>There some files that do have at least 1 line over the 80 characters limit.<br>Find and fix them.<br><br>BUG=b:117950052<br>TEST=Build grunt.<br><br>Change-Id: I1083a7559919e05a3e3a2dac99f571c161bb4c27<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/common/block/pci/amd_pci_util.c<br>M src/soc/amd/stoneyridge/include/soc/nvs.h<br>M src/soc/amd/stoneyridge/northbridge.c<br>3 files changed, 9 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/29228/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/common/block/pci/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c</span><br><span>index 8127601..e0b3c3d 100644</span><br><span>--- a/src/soc/amd/common/block/pci/amd_pci_util.c</span><br><span>+++ b/src/soc/amd/common/block/pci/amd_pci_util.c</span><br><span>@@ -98,7 +98,9 @@</span><br><span> void write_pci_cfg_irqs(void)</span><br><span> {</span><br><span> struct device *dev = NULL; /* Our current device to route IRQs */</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *target_dev = NULL; /* to bridge a device may be connected to */</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *target_dev = NULL; /* the bridge a device may be</span><br><span style="color: hsl(120, 100%, 40%);">+ *connected to</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> u16 int_pin = 0; /* Value of the INT_PIN register 0x3D */</span><br><span> u16 target_pin = 0; /* Pin we will search our tables for */</span><br><span> u16 int_line = 0; /* IRQ # read from PCI_INTR tbl and write to 3C */</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h</span><br><span>index 3e6ef30..7578f9d 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/nvs.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h</span><br><span>@@ -43,7 +43,9 @@</span><br><span> uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */</span><br><span> uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */</span><br><span> uint8_t scdp; /* 0x29 - SD_CD GPIO portid */</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t scdo; /* 0x2A - GPIO pad offset relative to the community */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t scdo; /* 0x2A - GPIO pad offset relative</span><br><span style="color: hsl(120, 100%, 40%);">+ * to the community</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> uint8_t tmps; /* 0x2B - Temperature Sensor ID */</span><br><span> uint8_t tlvl; /* 0x2C - Throttle Level Limit */</span><br><span> uint8_t flvl; /* 0x2D - Current FAN Level */</span><br><span>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>index d17d855..88a74b0 100644</span><br><span>--- a/src/soc/amd/stoneyridge/northbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>@@ -86,7 +86,9 @@</span><br><span> res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_resource(struct device *dev,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct resource *resource,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 nodeid)</span><br><span> {</span><br><span> resource_t rbase, rend;</span><br><span> unsigned int reg, link_num;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29228">change 29228</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29228"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1083a7559919e05a3e3a2dac99f571c161bb4c27 </div>
<div style="display:none"> Gerrit-Change-Number: 29228 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>