<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29184">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Replace public magic numbers<br><br>Some "magic" numbers became public available registers/bits after the code<br>was originally written. Find all magic numbers, and if available in a public<br>BKDG than replace them with literals.<br><br>BUG=b:117648026<br>TEST=Build and boot grunt.<br><br>Change-Id: I9a241150917b290feeeee9d91e5f0fb01d030225<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/northbridge.h<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/northbridge.c<br>M src/soc/amd/stoneyridge/southbridge.c<br>4 files changed, 13 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29184/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>index 7f7ac5d..689e9c1 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>@@ -62,6 +62,10 @@</span><br><span> # define MMIO_RE (1 << 0)</span><br><span> #define D18F1_MMIO_LIMIT0_LO 0x84</span><br><span> # define MMIO_NP (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define D18F1_IO_BASE0_LO 0xc0</span><br><span style="color: hsl(120, 100%, 40%);">+#define D18F1_IO_BASE1_LO 0xc8</span><br><span style="color: hsl(120, 100%, 40%);">+#define D18F1_IO_BASE2_LO 0xd0</span><br><span style="color: hsl(120, 100%, 40%);">+#define D18F1_IO_BASE3_LO 0xd8</span><br><span> #define D18F1_MMIO_BASELIM0_HI 0x180</span><br><span> #define D18F1_MMIO_BASE8_LO 0x1a0</span><br><span> #define D18F1_MMIO_LIMIT8_LO 0x1a4</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 681f149..7355f72 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -304,6 +304,7 @@</span><br><span> #define LPC_WIDEIO2_GENERIC_PORT 0x90</span><br><span> </span><br><span> #define SPIROM_BASE_ADDRESS_REGISTER 0xa0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_BASE_RESERVED (BIT(5) | BIT(6))</span><br><span> #define ROUTE_TPM_2_SPI BIT(3)</span><br><span> #define SPI_ABORT_ENABLE BIT(2)</span><br><span> #define SPI_ROM_ENABLE BIT(1)</span><br><span>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>index 95c2a07..04e18a6 100644</span><br><span>--- a/src/soc/amd/stoneyridge/northbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>@@ -381,8 +381,10 @@</span><br><span> struct device *dev;</span><br><span> u32 value;</span><br><span> dev = dev_find_slot(0, GNB_DEVFN); /* clear IoapicSbFeatureEn */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, 0xf8, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, 0xfc, 5); /* TODO: move it to dsdt.asl */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, NB_IOAPIC_INDEX, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, NB_IOAPIC_DATA, 5); /* TODO: move it to</span><br><span style="color: hsl(120, 100%, 40%);">+ * dsdt.asl</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> </span><br><span> /* disable No Snoop */</span><br><span> dev = dev_find_slot(0, HDA0_DEVFN);</span><br><span>@@ -397,7 +399,8 @@</span><br><span> struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);</span><br><span> </span><br><span> /* Find the already assigned resource pairs */</span><br><span style="color: hsl(0, 100%, 40%);">- for (reg = 0x80 ; reg <= 0xd8 ; reg += 0x08) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (reg = D18F1_MMIO_BASE0_LO ; reg <= D18F1_IO_BASE3_LO ;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg += 0x08) {</span><br><span> u32 base, limit;</span><br><span> base = pci_read_config32(addr_map, reg);</span><br><span> limit = pci_read_config32(addr_map, reg + 4);</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 37ebdc1..b188b76 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -414,8 +414,8 @@</span><br><span> </span><br><span> /* Make sure the base address is predictable */</span><br><span> base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER);</span><br><span style="color: hsl(0, 100%, 40%);">- enables = base & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- base &= ~0x3f;</span><br><span style="color: hsl(120, 100%, 40%);">+ enables = base & SPI_PRESERVE_BITS;</span><br><span style="color: hsl(120, 100%, 40%);">+ base &= ~(SPI_PRESERVE_BITS | SPI_BASE_RESERVED);</span><br><span> </span><br><span> if (!base) {</span><br><span> base = SPI_BASE_ADDRESS;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29184">change 29184</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29184"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9a241150917b290feeeee9d91e5f0fb01d030225 </div>
<div style="display:none"> Gerrit-Change-Number: 29184 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>