<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29177">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Move common amd64 MSRs to <cpu/x86/msr.h><br><br>Change-Id: Ic9022a98878a2fcc85868a64aa9c2ca3eb2e2c4e<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>D src/include/cpu/amd/amdfam15.h<br>M src/include/cpu/x86/msr.h<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>M src/soc/amd/stoneyridge/mca.c<br>M src/soc/amd/stoneyridge/northbridge.c<br>5 files changed, 171 insertions(+), 192 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/29177/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h</span><br><span>deleted file mode 100644</span><br><span>index 18feaff..0000000</span><br><span>--- a/src/include/cpu/amd/amdfam15.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,189 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef CPU_AMD_FAM15_H</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_AMD_FAM15_H</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <types.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MC0_STATUS 0x00000401</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_VAL BIT(63 - 32)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_OVERFLOW BIT(62 - 32)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_UC BIT(61 - 32)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_EN BIT(60 - 32)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_MISCV BIT(59 - 32)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_ADDRV BIT(58 - 32)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_PCC BIT(57 - 32)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_COREID_VAL BIT(56 - 32)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_CECC BIT(46 - 32)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_UECC BIT(45 - 32)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_DEFERRED BIT(44 - 32)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_POISON BIT(43 - 32)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_SUBLINK BIT(41 - 32)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_HI_ERRCOREID_MASK (0xf << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_LO_ERRCODE_EXT_SH 16</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)</span><br><span style="color: hsl(0, 100%, 40%);">-# define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MC0_ADDR 0x00000402</span><br><span style="color: hsl(0, 100%, 40%);">-#define MC0_MISC 0x00000403</span><br><span style="color: hsl(0, 100%, 40%);">-#define MC0_CTL_MASK 0xC0010044</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Helpers for interpreting MC[i]_STATUS */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int mca_valid(msr_t msr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(msr.hi & MCA_STATUS_HI_VAL);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int mca_over(msr_t msr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(msr.hi & MCA_STATUS_HI_OVERFLOW);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int mca_uc(msr_t msr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(msr.hi & MCA_STATUS_HI_UC);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int mca_en(msr_t msr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(msr.hi & MCA_STATUS_HI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int mca_miscv(msr_t msr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(msr.hi & MCA_STATUS_HI_MISCV);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int mca_addrv(msr_t msr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(msr.hi & MCA_STATUS_HI_ADDRV);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int mca_pcc(msr_t msr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(msr.hi & MCA_STATUS_HI_PCC);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int mca_idv(msr_t msr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(msr.hi & MCA_STATUS_HI_COREID_VAL);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int mca_cecc(msr_t msr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(msr.hi & MCA_STATUS_HI_CECC);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int mca_uecc(msr_t msr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(msr.hi & MCA_STATUS_HI_UECC);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int mca_defd(msr_t msr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(msr.hi & MCA_STATUS_HI_DEFERRED);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int mca_poison(msr_t msr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(msr.hi & MCA_STATUS_HI_POISON);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int mca_sublink(msr_t msr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(msr.hi & MCA_STATUS_HI_SUBLINK);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline uint16_t mca_err_code(msr_t reg)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return reg.lo & MCA_STATUS_LO_ERRCODE_MASK;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline uint16_t mca_err_extcode(msr_t reg)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return reg.lo & MCA_STATUS_LO_ERRCODE_EXT_MASK;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Machine Check errors may be categorized by type, as determined by the</span><br><span style="color: hsl(0, 100%, 40%);">- * Error Code field of MC[i]_STATUS. The definitions below can typically</span><br><span style="color: hsl(0, 100%, 40%);">- * be found by searching the BKDG for a table called "Error Code Types".</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-/* TLB Errors 0000 0000 0001 TTLL */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_TLB_DETECT 0xfff0</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_TLB_TT_SH 2 /* Transaction Type */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_TLB_TT_MASK (0x3 << MCA_ERRCODE_TLB_TT_SH)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_TLB_LL_SH 0 /* Cache Level */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_TLB_LL_MASK (0x3 << MCA_ERRCODE_TLB_LL_SH)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Memory Errors 0000 0001 RRRR TTLL */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_MEM_DETECT 0xff00</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_MEM_RRRR_SH 4 /* Memory Transaction Type */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_MEM_RRRR_MASK (0xf << MCA_ERRCODE_MEM_RRRR_MASK)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_MEM_TT_SH 2 /* Transaction Type */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_MEM_TT_MASK (0x3 << MCA_ERRCODE_MEM_TT_SH)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_MEM_LL_SH 0 /* Cache Level */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_MEM_LL_MASK (0x3 << MCA_ERRCODE_MEM_LL_SH)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Bus Errors 0000 1PPT RRRR IILL */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_BUS_DETECT 0xf800</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_BUS_PP_SH 9 /* Participation Processor */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_BUS_PP_MASK (0x3 << MCA_ERRCODE_BUS_PP_SH)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_BUS_T_SH 8 /* Timeout */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_BUS_T_MASK (0x1 << MCA_ERRCODE_BUS_T_SH)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_BUS_RRRR_SH 4 /* Memory Transaction Type */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_BUS_RRRR_MASK (0xf << MCA_ERRCODE_BUS_RRRR_SH)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_BUS_II_SH 2 /* Memory or IO */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_BUS_II_MASK (0x3 << MCA_ERRCODE_BUS_II_SH)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_BUS_LL_SH 0 /* Cache Level */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_BUS_LL_MASK (0x3 << MCA_ERRCODE_BUS_LL_SH)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Int. Unclassified Errors 0000 01UU 0000 0000 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_INT_DETECT 0xfc00</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_INT_UU_SH 8 /* Internal Error Type */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_ERRCODE_INT_UU_MASK (0x3 << MCA_ERRCODE_INT_UU_SH)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_BANK_LS 0 /* Load-store, including DC */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_BANK_IF 1 /* Instruction Fetch, including IC */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_BANK_CU 2 /* Combined Unit, including L2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* bank 3 reserved */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_BANK_NB 4 /* Northbridge, including IO link */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_BANK_EX 5 /* Execution Unit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCA_BANK_FP 6 /* Floating Point */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-enum mca_err_code_types {</span><br><span style="color: hsl(0, 100%, 40%);">- MCA_ERRTYPE_UNKNOWN,</span><br><span style="color: hsl(0, 100%, 40%);">- MCA_ERRTYPE_TLB,</span><br><span style="color: hsl(0, 100%, 40%);">- MCA_ERRTYPE_MEM,</span><br><span style="color: hsl(0, 100%, 40%);">- MCA_ERRTYPE_BUS,</span><br><span style="color: hsl(0, 100%, 40%);">- MCA_ERRTYPE_INT</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline enum mca_err_code_types mca_err_type(msr_t reg)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t error = mca_err_code(reg);</span><br><span style="color: hsl(0, 100%, 40%);">- if (error & MCA_ERRCODE_BUS_DETECT) /* this order must be maintained */</span><br><span style="color: hsl(0, 100%, 40%);">- return MCA_ERRTYPE_BUS;</span><br><span style="color: hsl(0, 100%, 40%);">- if (error & MCA_ERRCODE_INT_DETECT)</span><br><span style="color: hsl(0, 100%, 40%);">- return MCA_ERRTYPE_INT;</span><br><span style="color: hsl(0, 100%, 40%);">- if (error & MCA_ERRCODE_MEM_DETECT)</span><br><span style="color: hsl(0, 100%, 40%);">- return MCA_ERRTYPE_MEM;</span><br><span style="color: hsl(0, 100%, 40%);">- if (error & MCA_ERRCODE_TLB_DETECT)</span><br><span style="color: hsl(0, 100%, 40%);">- return MCA_ERRTYPE_TLB;</span><br><span style="color: hsl(0, 100%, 40%);">- return MCA_ERRTYPE_UNKNOWN;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* CPU_AMD_FAM15_H */</span><br><span>diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h</span><br><span>index 032ce4e..beab906 100644</span><br><span>--- a/src/include/cpu/x86/msr.h</span><br><span>+++ b/src/include/cpu/x86/msr.h</span><br><span>@@ -1,9 +1,14 @@</span><br><span> #ifndef CPU_X86_MSR_H</span><br><span> #define CPU_X86_MSR_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Intel SDM: Table 2-1</span><br><span> * IA-32 architectural MSR: Extended Feature Enable Register</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * AMD64 Programmers Manual vol2 Revision 3.30 and/or the device's BKDG</span><br><span> */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define IA32_EFER 0xC0000080</span><br><span> #define EFER_NXE (1 << 11)</span><br><span> #define EFER_LMA (1 << 10)</span><br><span>@@ -40,6 +45,27 @@</span><br><span> #define IA32_PAT 0x277</span><br><span> #define IA32_MC0_CTL 0x400</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_VAL BIT(63 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_OVERFLOW BIT(62 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_UC BIT(61 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_EN BIT(60 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_MISCV BIT(59 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_ADDRV BIT(58 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_PCC BIT(57 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_COREID_VAL BIT(56 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_CECC BIT(46 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_UECC BIT(45 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_DEFERRED BIT(44 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_POISON BIT(43 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_SUBLINK BIT(41 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_HI_ERRCOREID_MASK (0xf << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_LO_ERRCODE_EXT_SH 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MC0_ADDR 0x402</span><br><span style="color: hsl(120, 100%, 40%);">+#define MC0_MISC 0x403</span><br><span style="color: hsl(120, 100%, 40%);">+#define MC0_CTL_MASK 0xC0010044</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define IA32_PM_ENABLE 0x770</span><br><span> #define IA32_HWP_CAPABILITIES 0x771</span><br><span> #define IA32_HWP_REQUEST 0x774</span><br><span>@@ -51,6 +77,151 @@</span><br><span> #define IA32_L3_MASK_2 0xc92</span><br><span> </span><br><span> #ifndef __ASSEMBLER__</span><br><span style="color: hsl(120, 100%, 40%);">+/* Helpers for interpreting MC[i]_STATUS */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_valid(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_VAL);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_over(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_OVERFLOW);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_uc(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_UC);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_en(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_miscv(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_MISCV);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_addrv(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_ADDRV);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_pcc(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_PCC);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_idv(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_COREID_VAL);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_cecc(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_CECC);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_uecc(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_UECC);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_defd(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_DEFERRED);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_poison(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_POISON);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_sublink(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_SUBLINK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline uint16_t mca_err_code(msr_t reg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return reg.lo & MCA_STATUS_LO_ERRCODE_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline uint16_t mca_err_extcode(msr_t reg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return reg.lo & MCA_STATUS_LO_ERRCODE_EXT_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Machine Check errors may be categorized by type, as determined by the</span><br><span style="color: hsl(120, 100%, 40%);">+ * Error Code field of MC[i]_STATUS. The definitions below can typically</span><br><span style="color: hsl(120, 100%, 40%);">+ * be found by searching the BKDG for a table called "Error Code Types".</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+/* TLB Errors 0000 0000 0001 TTLL */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_TLB_DETECT 0xfff0</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_TLB_TT_SH 2 /* Transaction Type */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_TLB_TT_MASK (0x3 << MCA_ERRCODE_TLB_TT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_TLB_LL_SH 0 /* Cache Level */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_TLB_LL_MASK (0x3 << MCA_ERRCODE_TLB_LL_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Memory Errors 0000 0001 RRRR TTLL */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_DETECT 0xff00</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_RRRR_SH 4 /* Memory Transaction Type */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_RRRR_MASK (0xf << MCA_ERRCODE_MEM_RRRR_MASK)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_TT_SH 2 /* Transaction Type */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_TT_MASK (0x3 << MCA_ERRCODE_MEM_TT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_LL_SH 0 /* Cache Level */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_LL_MASK (0x3 << MCA_ERRCODE_MEM_LL_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bus Errors 0000 1PPT RRRR IILL */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_DETECT 0xf800</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_PP_SH 9 /* Participation Processor */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_PP_MASK (0x3 << MCA_ERRCODE_BUS_PP_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_T_SH 8 /* Timeout */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_T_MASK (0x1 << MCA_ERRCODE_BUS_T_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_RRRR_SH 4 /* Memory Transaction Type */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_RRRR_MASK (0xf << MCA_ERRCODE_BUS_RRRR_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_II_SH 2 /* Memory or IO */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_II_MASK (0x3 << MCA_ERRCODE_BUS_II_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_LL_SH 0 /* Cache Level */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_LL_MASK (0x3 << MCA_ERRCODE_BUS_LL_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Int. Unclassified Errors 0000 01UU 0000 0000 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_INT_DETECT 0xfc00</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_INT_UU_SH 8 /* Internal Error Type */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_INT_UU_MASK (0x3 << MCA_ERRCODE_INT_UU_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_BANK_LS 0 /* Load-store, including DC */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_BANK_IF 1 /* Instruction Fetch, including IC */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_BANK_CU 2 /* Combined Unit, including L2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* bank 3 reserved */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_BANK_NB 4 /* Northbridge, including IO link */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_BANK_EX 5 /* Execution Unit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_BANK_FP 6 /* Floating Point */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum mca_err_code_types {</span><br><span style="color: hsl(120, 100%, 40%);">+ MCA_ERRTYPE_UNKNOWN,</span><br><span style="color: hsl(120, 100%, 40%);">+ MCA_ERRTYPE_TLB,</span><br><span style="color: hsl(120, 100%, 40%);">+ MCA_ERRTYPE_MEM,</span><br><span style="color: hsl(120, 100%, 40%);">+ MCA_ERRTYPE_BUS,</span><br><span style="color: hsl(120, 100%, 40%);">+ MCA_ERRTYPE_INT</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline enum mca_err_code_types mca_err_type(msr_t reg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t error = mca_err_code(reg);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (error & MCA_ERRCODE_BUS_DETECT) /* this order must be maintained */</span><br><span style="color: hsl(120, 100%, 40%);">+ return MCA_ERRTYPE_BUS;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (error & MCA_ERRCODE_INT_DETECT)</span><br><span style="color: hsl(120, 100%, 40%);">+ return MCA_ERRTYPE_INT;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (error & MCA_ERRCODE_MEM_DETECT)</span><br><span style="color: hsl(120, 100%, 40%);">+ return MCA_ERRTYPE_MEM;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (error & MCA_ERRCODE_TLB_DETECT)</span><br><span style="color: hsl(120, 100%, 40%);">+ return MCA_ERRTYPE_TLB;</span><br><span style="color: hsl(120, 100%, 40%);">+ return MCA_ERRTYPE_UNKNOWN;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #if defined(__ROMCC__)</span><br><span> </span><br><span> typedef __builtin_msr_t msr_t;</span><br><span>diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>index e9a5bd6..37e22ac 100644</span><br><span>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>@@ -20,7 +20,6 @@</span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <cpu/amd/msr.h></span><br><span> #include <cpu/x86/mtrr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/amdfam15.h></span><br><span> #include <smp/node.h></span><br><span> #include <bootblock_common.h></span><br><span> #include <amdblocks/agesawrapper.h></span><br><span>diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c</span><br><span>index 13e626e..eddaba4 100644</span><br><span>--- a/src/soc/amd/stoneyridge/mca.c</span><br><span>+++ b/src/soc/amd/stoneyridge/mca.c</span><br><span>@@ -15,7 +15,6 @@</span><br><span> </span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/amdfam15.h></span><br><span> #include <soc/cpu.h></span><br><span> #include <soc/northbridge.h></span><br><span> #include <console/console.h></span><br><span>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>index a2ae52c..2deaf53 100644</span><br><span>--- a/src/soc/amd/stoneyridge/northbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>@@ -22,7 +22,6 @@</span><br><span> #include <chip.h></span><br><span> #include <console/console.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/amdfam15.h></span><br><span> #include <cpu/cpu.h></span><br><span> #include <cpu/x86/lapic_def.h></span><br><span> #include <cpu/x86/msr.h></span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29177">change 29177</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic9022a98878a2fcc85868a64aa9c2ca3eb2e2c4e </div>
<div style="display:none"> Gerrit-Change-Number: 29177 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>