<p>Aamir Bohra would like Rizwan Qureshi to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/29163">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/intel/fsp/icelake: Add icelake FSP header file template<br><br>icelake FSP is still under development and hence the FSP header files<br>and binaries are not available on github. Meanwhile add basic header<br>files required to compile the SoC and mainboard with FSP2.0.<br><br>BUG=None<br>BRANCH=None<br>TEST=Build for icelake_rvp board successfull.<br><br>Change-Id: I9ab8f180b572ec553e7531f7483d091f6897c462<br>Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com><br>---<br>A src/vendorcode/intel/fsp/fsp2_0/icelake/FirmwareVersionInfoHob.h<br>A src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h<br>A src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h<br>A src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h<br>A src/vendorcode/intel/fsp/fsp2_0/icelake/FsptUpd.h<br>A src/vendorcode/intel/fsp/fsp2_0/icelake/MemInfoHob.h<br>6 files changed, 626 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29163/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/FirmwareVersionInfoHob.h</span><br><span>new file mode 100644</span><br><span>index 0000000..0dbafff</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/icelake/FirmwareVersionInfoHob.h</span><br><span>@@ -0,0 +1,67 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file</span><br><span style="color: hsl(120, 100%, 40%);">+ Header file for Firmware Version Information</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ This program and the accompanying materials are licensed and made available under</span><br><span style="color: hsl(120, 100%, 40%);">+ the terms and conditions of the BSD License which accompanies this distribution.</span><br><span style="color: hsl(120, 100%, 40%);">+ The full text of the license may be found at</span><br><span style="color: hsl(120, 100%, 40%);">+ http://opensource.org/licenses/bsd-license.php</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,</span><br><span style="color: hsl(120, 100%, 40%);">+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _FIRMWARE_VERSION_INFO_HOB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _FIRMWARE_VERSION_INFO_HOB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Uefi/UefiMultiPhase.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiBootMode.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiHob.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack(1)</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+/// Firmware Version Structure</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MajorVersion;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MinorVersion;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Revision;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 BuildNumber;</span><br><span style="color: hsl(120, 100%, 40%);">+} FIRMWARE_VERSION;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+/// Firmware Version Information Structure</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 VersionStringIndex; ///< Offset 1 Index of Version String</span><br><span style="color: hsl(120, 100%, 40%);">+ FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version</span><br><span style="color: hsl(120, 100%, 40%);">+} FIRMWARE_VERSION_INFO;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __SMBIOS_STANDARD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+/// The Smbios structure header.</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Type;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Length;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Handle;</span><br><span style="color: hsl(120, 100%, 40%);">+} SMBIOS_STRUCTURE;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+/// Firmware Version Information HOB Structure</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB</span><br><span style="color: hsl(120, 100%, 40%);">+ SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Count; ///< Offset 28 Number of FVI elements included.</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+} FIRMWARE_VERSION_INFO_HOB;</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif // _FIRMWARE_VERSION_INFO_HOB_H_</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h</span><br><span>new file mode 100644</span><br><span>index 0000000..decbb99</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h</span><br><span>@@ -0,0 +1,48 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Redistribution and use in source and binary forms, with or without modification,</span><br><span style="color: hsl(120, 100%, 40%);">+are permitted provided that the following conditions are met:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions of source code must retain the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer.</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions in binary form must reproduce the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer in the documentation and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ other materials provided with the distribution.</span><br><span style="color: hsl(120, 100%, 40%);">+* Neither the name of Intel Corporation nor the names of its contributors may</span><br><span style="color: hsl(120, 100%, 40%);">+ be used to endorse or promote products derived from this software without</span><br><span style="color: hsl(120, 100%, 40%);">+ specific prior written permission.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"</span><br><span style="color: hsl(120, 100%, 40%);">+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span><br><span style="color: hsl(120, 100%, 40%);">+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE</span><br><span style="color: hsl(120, 100%, 40%);">+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span><br><span style="color: hsl(120, 100%, 40%);">+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF</span><br><span style="color: hsl(120, 100%, 40%);">+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS</span><br><span style="color: hsl(120, 100%, 40%);">+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)</span><br><span style="color: hsl(120, 100%, 40%);">+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF</span><br><span style="color: hsl(120, 100%, 40%);">+ THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ This file is automatically generated. Please do NOT modify !!!</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __FSPUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __FSPUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <FspEas.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack(1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define FSPT_UPD_SIGNATURE 0x545F4450554C4349 /* 'ICLUPD_T' */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4349 /* 'ICLUPD_M' */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define FSPS_UPD_SIGNATURE 0x535F4450554C4349 /* 'ICLUPD_S' */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h</span><br><span>new file mode 100644</span><br><span>index 0000000..cbe2d3c</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h</span><br><span>@@ -0,0 +1,84 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Redistribution and use in source and binary forms, with or without modification,</span><br><span style="color: hsl(120, 100%, 40%);">+are permitted provided that the following conditions are met:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions of source code must retain the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer.</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions in binary form must reproduce the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer in the documentation and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ other materials provided with the distribution.</span><br><span style="color: hsl(120, 100%, 40%);">+* Neither the name of Intel Corporation nor the names of its contributors may</span><br><span style="color: hsl(120, 100%, 40%);">+ be used to endorse or promote products derived from this software without</span><br><span style="color: hsl(120, 100%, 40%);">+ specific prior written permission.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"</span><br><span style="color: hsl(120, 100%, 40%);">+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span><br><span style="color: hsl(120, 100%, 40%);">+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE</span><br><span style="color: hsl(120, 100%, 40%);">+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span><br><span style="color: hsl(120, 100%, 40%);">+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF</span><br><span style="color: hsl(120, 100%, 40%);">+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS</span><br><span style="color: hsl(120, 100%, 40%);">+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)</span><br><span style="color: hsl(120, 100%, 40%);">+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF</span><br><span style="color: hsl(120, 100%, 40%);">+ THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ This file is automatically generated. Please do NOT modify !!!</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __FSPMUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __FSPMUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <FspUpd.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack(1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <MemInfoHob.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp M Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_M_CONFIG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp M Test Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_M_TEST_CONFIG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp M UPD Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_UPD_HEADER FspUpdHeader;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0020</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSPM_ARCH_UPD FspmArchUpd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0040</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_M_CONFIG FspmConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x051F</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace8;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0520</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_M_TEST_CONFIG FspmTestConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05BC</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 UpdTerminator;</span><br><span style="color: hsl(120, 100%, 40%);">+} FSPM_UPD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h</span><br><span>new file mode 100644</span><br><span>index 0000000..37356a1</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h</span><br><span>@@ -0,0 +1,73 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Redistribution and use in source and binary forms, with or without modification,</span><br><span style="color: hsl(120, 100%, 40%);">+are permitted provided that the following conditions are met:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions of source code must retain the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer.</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions in binary form must reproduce the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer in the documentation and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ other materials provided with the distribution.</span><br><span style="color: hsl(120, 100%, 40%);">+* Neither the name of Intel Corporation nor the names of its contributors may</span><br><span style="color: hsl(120, 100%, 40%);">+ be used to endorse or promote products derived from this software without</span><br><span style="color: hsl(120, 100%, 40%);">+ specific prior written permission.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"</span><br><span style="color: hsl(120, 100%, 40%);">+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span><br><span style="color: hsl(120, 100%, 40%);">+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE</span><br><span style="color: hsl(120, 100%, 40%);">+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span><br><span style="color: hsl(120, 100%, 40%);">+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF</span><br><span style="color: hsl(120, 100%, 40%);">+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS</span><br><span style="color: hsl(120, 100%, 40%);">+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)</span><br><span style="color: hsl(120, 100%, 40%);">+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF</span><br><span style="color: hsl(120, 100%, 40%);">+ THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ This file is automatically generated. Please do NOT modify !!!</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __FSPSUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __FSPSUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <FspUpd.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack(1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp S Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_S_CONFIG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp S Test Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_S_TEST_CONFIG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp S UPD Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_UPD_HEADER FspUpdHeader;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0020</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_S_CONFIG FspsConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07AD</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_S_TEST_CONFIG FspsTestConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A80</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 UpdTerminator;</span><br><span style="color: hsl(120, 100%, 40%);">+} FSPS_UPD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/FsptUpd.h</span><br><span>new file mode 100644</span><br><span>index 0000000..022acaf</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/icelake/FsptUpd.h</span><br><span>@@ -0,0 +1,74 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Redistribution and use in source and binary forms, with or without modification,</span><br><span style="color: hsl(120, 100%, 40%);">+are permitted provided that the following conditions are met:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions of source code must retain the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer.</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions in binary form must reproduce the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer in the documentation and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ other materials provided with the distribution.</span><br><span style="color: hsl(120, 100%, 40%);">+* Neither the name of Intel Corporation nor the names of its contributors may</span><br><span style="color: hsl(120, 100%, 40%);">+ be used to endorse or promote products derived from this software without</span><br><span style="color: hsl(120, 100%, 40%);">+ specific prior written permission.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"</span><br><span style="color: hsl(120, 100%, 40%);">+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span><br><span style="color: hsl(120, 100%, 40%);">+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE</span><br><span style="color: hsl(120, 100%, 40%);">+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span><br><span style="color: hsl(120, 100%, 40%);">+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF</span><br><span style="color: hsl(120, 100%, 40%);">+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS</span><br><span style="color: hsl(120, 100%, 40%);">+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)</span><br><span style="color: hsl(120, 100%, 40%);">+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF</span><br><span style="color: hsl(120, 100%, 40%);">+ THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ This file is automatically generated. Please do NOT modify !!!</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __FSPTUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __FSPTUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <FspUpd.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack(1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp T Core UPD</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+} FSPT_CORE_UPD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp T Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_T_CONFIG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp T UPD Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_UPD_HEADER FspUpdHeader;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0020</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSPT_CORE_UPD FsptCoreUpd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0040</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_T_CONFIG FsptConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0080</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 UpdTerminator;</span><br><span style="color: hsl(120, 100%, 40%);">+} FSPT_UPD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/MemInfoHob.h</span><br><span>new file mode 100644</span><br><span>index 0000000..aa711a1</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/icelake/MemInfoHob.h</span><br><span>@@ -0,0 +1,280 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file</span><br><span style="color: hsl(120, 100%, 40%);">+ This file contains definitions required for creation of</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory S3 Save data, Memory Info data and Memory Platform</span><br><span style="color: hsl(120, 100%, 40%);">+ data hobs.</span><br><span style="color: hsl(120, 100%, 40%);">+ @copyright</span><br><span style="color: hsl(120, 100%, 40%);">+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+Redistribution and use in source and binary forms, with or without modification,</span><br><span style="color: hsl(120, 100%, 40%);">+are permitted provided that the following conditions are met:</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions of source code must retain the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer.</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions in binary form must reproduce the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer in the documentation and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ other materials provided with the distribution.</span><br><span style="color: hsl(120, 100%, 40%);">+* Neither the name of Intel Corporation nor the names of its contributors may</span><br><span style="color: hsl(120, 100%, 40%);">+ be used to endorse or promote products derived from this software without</span><br><span style="color: hsl(120, 100%, 40%);">+ specific prior written permission.</span><br><span style="color: hsl(120, 100%, 40%);">+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"</span><br><span style="color: hsl(120, 100%, 40%);">+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span><br><span style="color: hsl(120, 100%, 40%);">+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE</span><br><span style="color: hsl(120, 100%, 40%);">+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span><br><span style="color: hsl(120, 100%, 40%);">+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF</span><br><span style="color: hsl(120, 100%, 40%);">+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS</span><br><span style="color: hsl(120, 100%, 40%);">+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)</span><br><span style="color: hsl(120, 100%, 40%);">+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF</span><br><span style="color: hsl(120, 100%, 40%);">+ THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _MEM_INFO_HOB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _MEM_INFO_HOB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Uefi/UefiMultiPhase.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiBootMode.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiHob.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack (push, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern EFI_GUID gSiMemoryS3DataGuid;</span><br><span style="color: hsl(120, 100%, 40%);">+extern EFI_GUID gSiMemoryInfoDataGuid;</span><br><span style="color: hsl(120, 100%, 40%);">+extern EFI_GUID gSiMemoryPlatformDataGuid;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_NODE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_CH 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_DIMM 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+/// Host reset states from MRC.</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+#define WARM_BOOT 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define R_MC_CHNL_RANK_PRESENT 0x7C</span><br><span style="color: hsl(120, 100%, 40%);">+#define B_RANK0_PRS BIT0</span><br><span style="color: hsl(120, 100%, 40%);">+#define B_RANK1_PRS BIT1</span><br><span style="color: hsl(120, 100%, 40%);">+#define B_RANK2_PRS BIT4</span><br><span style="color: hsl(120, 100%, 40%);">+#define B_RANK3_PRS BIT5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+/// Defines taken from MRC so avoid having to include MrcInterface.h</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MAX_SPD_SAVE define in MRC</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MAX_SPD_SAVE</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_SPD_SAVE 29</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+// MRC version description.</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Major; ///< Major version number</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Minor; ///< Minor version number</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Rev; ///< Revision number</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Build; ///< Build number</span><br><span style="color: hsl(120, 100%, 40%);">+} SiMrcVersion;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MrcChannelSts enum in MRC</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CHANNEL_NOT_PRESENT</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CHANNEL_DISABLED</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CHANNEL_PRESENT</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MrcDimmSts enum in MRC</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DIMM_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DIMM_DISABLED</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DIMM_PRESENT</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DIMM_NOT_PRESENT</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MrcBootMode enum in MRC</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef bmCold</span><br><span style="color: hsl(120, 100%, 40%);">+#define bmCold 0 // Cold boot</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef bmWarm</span><br><span style="color: hsl(120, 100%, 40%);">+#define bmWarm 1 // Warm boot</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef bmS3</span><br><span style="color: hsl(120, 100%, 40%);">+#define bmS3 2 // S3 resume</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef bmFast</span><br><span style="color: hsl(120, 100%, 40%);">+#define bmFast 3 // Fast boot</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MrcDdrType enum in MRC</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_DDR4</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_DDR4 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_DDR3</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_DDR3 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_LPDDR3</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_LPDDR3 2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CPU_CFL//CNL</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_LPDDR4</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_LPDDR4 3</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#else//CFL</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_UNKNOWN</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_UNKNOWN 3</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#endif//CPU_CFL-endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_PROFILE_NUM 4 // number of memory profiles supported</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+// DIMM timings</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.</span><br><span style="color: hsl(120, 100%, 40%);">+} MRC_CH_TIMING;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.</span><br><span style="color: hsl(120, 100%, 40%);">+} MRC_TA_TIMING;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+/// Memory SMBIOS & OC Memory Data Hob</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DimmId;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 DimmCapacity; ///< DIMM size in MBytes.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 MfgId;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.</span><br><span style="color: hsl(120, 100%, 40%);">+} DIMM_INFO;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Status; ///< Indicates whether this channel should be used.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ChannelId;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.</span><br><span style="color: hsl(120, 100%, 40%);">+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.</span><br><span style="color: hsl(120, 100%, 40%);">+} CHANNEL_INFO;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Status; ///< Indicates whether this controller should be used.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DeviceId; ///< The PCI device id of this memory controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings</span><br><span style="color: hsl(120, 100%, 40%);">+} CONTROLLER_INFO;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Revision;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DataWidth; ///< Data width, in bits, of this memory device</span><br><span style="color: hsl(120, 100%, 40%);">+ /** As defined in SMBIOS 3.0 spec</span><br><span style="color: hsl(120, 100%, 40%);">+ Section 7.18.2 and Table 75</span><br><span style="color: hsl(120, 100%, 40%);">+ **/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)</span><br><span style="color: hsl(120, 100%, 40%);">+ /** As defined in SMBIOS 3.0 spec</span><br><span style="color: hsl(120, 100%, 40%);">+ Section 7.17.3 and Table 72</span><br><span style="color: hsl(120, 100%, 40%);">+ **/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ErrorCorrectionType;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ SiMrcVersion Version;</span><br><span style="color: hsl(120, 100%, 40%);">+ BOOLEAN EccSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MemoryProfile;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TotalPhysicalMemorySize;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Ratio;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RefClk;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 VddVoltage[MAX_PROFILE_NUM];</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTROLLER_INFO Controller[MAX_NODE];</span><br><span style="color: hsl(120, 100%, 40%);">+} MEMORY_INFO_DATA_HOB;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory Platform Data Hob</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>Revision 1:</b></span><br><span style="color: hsl(120, 100%, 40%);">+ - Initial version.</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>Revision 2:</b></span><br><span style="color: hsl(120, 100%, 40%);">+ - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Revision;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Reserved[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 BootMode;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TsegSize;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TsegBase;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PrmrrSize;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PrmrrBase;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GttBase;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MmioSize;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PciEBaseAddress;</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef CPU_CFL</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GdxcIotBase;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GdxcIotSize;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GdxcMotBase;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GdxcMotSize;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif //CPU_CFL</span><br><span style="color: hsl(120, 100%, 40%);">+} MEMORY_PLATFORM_DATA;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ EFI_HOB_GUID_TYPE EfiHobGuidType;</span><br><span style="color: hsl(120, 100%, 40%);">+ MEMORY_PLATFORM_DATA Data;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 *Buffer;</span><br><span style="color: hsl(120, 100%, 40%);">+} MEMORY_PLATFORM_DATA_HOB;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack (pop)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif // _MEM_INFO_HOB_H_</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29163">change 29163</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29163"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9ab8f180b572ec553e7531f7483d091f6897c462 </div>
<div style="display:none"> Gerrit-Change-Number: 29163 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>