<p>Roland Fehér has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29167">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">util/inteltool: Fix LynxPoint (non-LP) GPIO register map<br><br>The GPIO register dumper code for the LynxPoint family PCH chips<br>(Intel 8 Series and C220 Series) was incorreclty using a<br>shortened version of the LynxPoint-LP (Intel 9 Series) GPIO<br>register map.<br>Added the correct register map for the affected chipsets.<br><br>Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f<br>Signed-off-by: Fehér Roland Ádám <feherneoh@gmail.com><br>---<br>M util/inteltool/gpio.c<br>1 file changed, 38 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29167/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c</span><br><span>index c38051c..38ce8fa 100644</span><br><span>--- a/util/inteltool/gpio.c</span><br><span>+++ b/util/inteltool/gpio.c</span><br><span>@@ -344,6 +344,42 @@</span><br><span> </span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static const io_register_t lynxpoint_gpio_registers[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x00, 4, "GPIO_USE_SEL" }, // GPIO Use Select</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x04, 4, "GP_IO_SEL" }, // GPIO Input/Output Select</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x08, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0C, 4, "GP_LVL" }, // GPIO Level for Input or Output</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x10, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x14, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x18, 4, "GPO_BLINK" }, // GPIO Blink Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x1C, 4, "GP_SER_BLINK" }, // GP Serial Blink</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x20, 4, "GP_SB_CMDSTS" }, // GP Serial Blink Command Status</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x24, 4, "GP_SB_DATA" }, // GP Serial Blink Data</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x28, 2, "GPI_NMI_EN" }, // GPI NMI Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x2A, 2, "GPI_NMI_STS" }, // GPI NMI Status</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x2C, 4, "GPI_INV" }, // GPIO Signal Invert</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x30, 4, "GPIO_USE_SEL2" }, // GPIO Use Select 2</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x34, 4, "GP_IO_SEL2" }, // GPIO Input/Output Select 2</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x38, 4, "GP_LVL2" }, // GPIO Level for Input or Output 2</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x3C, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x40, 4, "GPIO_USE_SEL3" }, // GPIO Use Select 3</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x44, 4, "GP_IO_SEL3" }, // GPIO Input/Output Select 3</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x48, 4, "GP_LVL3" }, // GPIO Level for Input or Output 3</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x4C, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x50, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x54, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x58, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x5C, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x60, 4, "GP_RST_SEL1" }, // GPIO Reset Select 1</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x64, 4, "GP_RST_SEL2" }, // GPIO Reset Select 2</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x68, 4, "GP_RST_SEL3" }, // GPIO Reset Select 3</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x6C, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x70, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x74, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x78, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x7C, 4, "RESERVED" }, // Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Default values for Cougar Point desktop chipsets */</span><br><span> static const gpio_default_t cp_pch_desktop_defaults[] = {</span><br><span> { 0x00, 0xb96ba1ff },</span><br><span>@@ -869,9 +905,8 @@</span><br><span> case PCI_DEVICE_ID_INTEL_C226:</span><br><span> case PCI_DEVICE_ID_INTEL_H81:</span><br><span> gpiobase = pci_read_word(sb, 0x48) & 0xfffc;</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_registers = lynxpoint_lp_gpio_registers;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Shares register locations but has less of them */</span><br><span style="color: hsl(0, 100%, 40%);">- size = 29;</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_registers = lynxpoint_gpio_registers;</span><br><span style="color: hsl(120, 100%, 40%);">+ size = ARRAY_SIZE(lynxpoint_gpio_registers);</span><br><span> break;</span><br><span> case PCI_DEVICE_ID_INTEL_3400:</span><br><span> case PCI_DEVICE_ID_INTEL_3420:</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29167">change 29167</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29167"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f </div>
<div style="display:none"> Gerrit-Change-Number: 29167 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Roland Fehér <feherneoh@gmail.com> </div>