<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29172">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Remove double defined SPI100_SPEED_CONFIG<br><br>SPI100_SPEED_CONFIG is double defined. Bits and shift definitions on the<br>first definition are unused. Remove first definition and its associated<br>bits and shifts.<br><br>BUG=b:117818430<br>TEST=Build grunt.<br><br>Change-Id: I8175b9a2f379b47475a71f93096f682bc56d051c<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>1 file changed, 1 insertion(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29172/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 9f940c0..3d0df68 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -351,15 +351,10 @@</span><br><span> #define SPI_FIFO                    0x80</span><br><span> #define   SPI_FIFO_DEPTH                (0xc7 - SPI_FIFO)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI100_SPEED_CONFIG                0x22</span><br><span style="color: hsl(0, 100%, 40%);">-/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */</span><br><span style="color: hsl(0, 100%, 40%);">-#define   SPI_CNTRL1_SPEED_MASK              (BIT(15) | BIT(14) | BIT(13) | BIT(12))</span><br><span style="color: hsl(0, 100%, 40%);">-#define   SPI_NORM_SPEED_SH              12</span><br><span style="color: hsl(0, 100%, 40%);">-#define   SPI_FAST_SPEED_SH           8</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define SPI100_ENABLE                      0x20</span><br><span> #define   SPI_USE_SPI100                BIT(0)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */</span><br><span> #define SPI100_SPEED_CONFIG              0x22</span><br><span> #define   SPI_SPEED_66M                 (0x0)</span><br><span> #define   SPI_SPEED_33M                        (                  BIT(0))</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29172">change 29172</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29172"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8175b9a2f379b47475a71f93096f682bc56d051c </div>
<div style="display:none"> Gerrit-Change-Number: 29172 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>