<p><a href="https://review.coreboot.org/29161">View Change</a></p><p>110 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/fidvid.c">File src/cpu/amd/family_10h-family_15h/fidvid.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/fidvid.c@499">Patch Set #6, Line 499:</a> <code style="font-family:monospace,monospace"> if (cpuRev & (AMD_DA_Cx | AMD_RB_C3)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/fidvid.c@504">Patch Set #6, Line 504:</a> <code style="font-family:monospace,monospace"> if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/fidvid.c@667">Patch Set #6, Line 667:</a> <code style="font-family:monospace,monospace"> if ((((u32)0xffffffff) - initial_msr.lo) < corrected_timeout) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/fidvid.c@676">Patch Set #6, Line 676:</a> <code style="font-family:monospace,monospace"> || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/fidvid.c@843">Patch Set #6, Line 843:</a> <code style="font-family:monospace,monospace"> vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK) >> SINGLE_PLANE_NB_VID_SHIFT;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/fidvid.c@844">Patch Set #6, Line 844:</a> <code style="font-family:monospace,monospace"> fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK) >> SINGLE_PLANE_NB_FID_SHIFT;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/fidvid.c@847">Patch Set #6, Line 847:</a> <code style="font-family:monospace,monospace"> vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK) >> DUAL_PLANE_NB_VID_SHIFT);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/fidvid.c@848">Patch Set #6, Line 848:</a> <code style="font-family:monospace,monospace"> fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK) >> DUAL_PLANE_NB_FID_SHIFT);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/powernow_acpi.c">File src/cpu/amd/family_10h-family_15h/powernow_acpi.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/powernow_acpi.c@229">Patch Set #6, Line 229:</a> <code style="font-family:monospace,monospace"> * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit.</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/cpu/via/nano/nano_init.c">File src/cpu/via/nano/nano_init.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/cpu/via/nano/nano_init.c@125">Patch Set #6, Line 125:</a> <code style="font-family:monospace,monospace"> msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c">File src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c@145">Patch Set #6, Line 145:</a> <code style="font-family:monospace,monospace"> FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/lamar/BiosCallOuts.c">File src/mainboard/amd/lamar/BiosCallOuts.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/lamar/BiosCallOuts.c@162">Patch Set #6, Line 162:</a> <code style="font-family:monospace,monospace"> FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/olivehill/BiosCallOuts.c">File src/mainboard/amd/olivehill/BiosCallOuts.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/olivehill/BiosCallOuts.c@114">Patch Set #6, Line 114:</a> <code style="font-family:monospace,monospace"> FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/olivehillplus/BiosCallOuts.c">File src/mainboard/amd/olivehillplus/BiosCallOuts.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/olivehillplus/BiosCallOuts.c@128">Patch Set #6, Line 128:</a> <code style="font-family:monospace,monospace"> FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/parmer/BiosCallOuts.c">File src/mainboard/amd/parmer/BiosCallOuts.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/parmer/BiosCallOuts.c@114">Patch Set #6, Line 114:</a> <code style="font-family:monospace,monospace"> FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c">File src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c@109">Patch Set #6, Line 109:</a> <code style="font-family:monospace,monospace"> current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c">File src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c@147">Patch Set #6, Line 147:</a> <code style="font-family:monospace,monospace"> for (i = 1; i< sysconf.hc_possible_num; i++) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">spaces required around that '<' (ctx:VxW)</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c">File src/mainboard/amd/serengeti_cheetah_fam10/mptable.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@110">Patch Set #6, Line 110:</a> <code style="font-family:monospace,monospace"> for (i = 0; i < 4; i++) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@116">Patch Set #6, Line 116:</a> <code style="font-family:monospace,monospace"> for (i = 0; i < 4; i++) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@122">Patch Set #6, Line 122:</a> <code style="font-family:monospace,monospace"> for (i = 0; i < 4; i++) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@128">Patch Set #6, Line 128:</a> <code style="font-family:monospace,monospace"> for (i = 0; i < 4; i++) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@150">Patch Set #6, Line 150:</a> <code style="font-family:monospace,monospace"> for (ii = 0; ii < 4; ii++) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Too many leading tabs - consider code refactoring</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@150">Patch Set #6, Line 150:</a> <code style="font-family:monospace,monospace"> for (ii = 0; ii < 4; ii++) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@163">Patch Set #6, Line 163:</a> <code style="font-family:monospace,monospace"> for (ii = 0; ii < 4; ii++) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Too many leading tabs - consider code refactoring</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@163">Patch Set #6, Line 163:</a> <code style="font-family:monospace,monospace"> for (ii = 0; ii < 4; ii++) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/thatcher/BiosCallOuts.c">File src/mainboard/amd/thatcher/BiosCallOuts.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/thatcher/BiosCallOuts.c@114">Patch Set #6, Line 114:</a> <code style="font-family:monospace,monospace"> FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/torpedo/gpio.c">File src/mainboard/amd/torpedo/gpio.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/torpedo/gpio.c@94">Patch Set #6, Line 94:</a> <code style="font-family:monospace,monospace"> if (BoardType == 0) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/bap/ode_e20XX/BiosCallOuts.c">File src/mainboard/bap/ode_e20XX/BiosCallOuts.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/bap/ode_e20XX/BiosCallOuts.c@117">Patch Set #6, Line 117:</a> <code style="font-family:monospace,monospace"> FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/bap/ode_e21XX/BiosCallOuts.c">File src/mainboard/bap/ode_e21XX/BiosCallOuts.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/bap/ode_e21XX/BiosCallOuts.c@130">Patch Set #6, Line 130:</a> <code style="font-family:monospace,monospace"> FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/biostar/a68n_5200/BiosCallOuts.c">File src/mainboard/biostar/a68n_5200/BiosCallOuts.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/biostar/a68n_5200/BiosCallOuts.c@114">Patch Set #6, Line 114:</a> <code style="font-family:monospace,monospace"> FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/gizmosphere/gizmo/OemCustomize.c">File src/mainboard/gizmosphere/gizmo/OemCustomize.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/gizmosphere/gizmo/OemCustomize.c@126">Patch Set #6, Line 126:</a> <code style="font-family:monospace,monospace"> HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c">File src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c@114">Patch Set #6, Line 114:</a> <code style="font-family:monospace,monospace"> FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c">File src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c@115">Patch Set #6, Line 115:</a> <code style="font-family:monospace,monospace"> FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lenovo/g505s/BiosCallOuts.c">File src/mainboard/lenovo/g505s/BiosCallOuts.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lenovo/g505s/BiosCallOuts.c@115">Patch Set #6, Line 115:</a> <code style="font-family:monospace,monospace"> FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lenovo/t60/smihandler.c">File src/mainboard/lenovo/t60/smihandler.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lenovo/t60/smihandler.c@52">Patch Set #6, Line 52:</a> <code style="font-family:monospace,monospace"> printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lenovo/z61t/smihandler.c">File src/mainboard/lenovo/z61t/smihandler.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lenovo/z61t/smihandler.c@53">Patch Set #6, Line 53:</a> <code style="font-family:monospace,monospace"> printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar,</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-af/mainboard.c">File src/mainboard/lippert/frontrunner-af/mainboard.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-af/mainboard.c@68">Patch Set #6, Line 68:</a> <code style="font-family:monospace,monospace"> FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-af/mainboard.c@69">Patch Set #6, Line 69:</a> <code style="font-family:monospace,monospace"> FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited between function name and open parenthesis '('</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-af/mainboard.c@72">Patch Set #6, Line 72:</a> <code style="font-family:monospace,monospace"> FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited between function name and open parenthesis '('</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-af/mainboard.c@74">Patch Set #6, Line 74:</a> <code style="font-family:monospace,monospace"> FCH_GPIO (57) = 0x28;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited between function name and open parenthesis '('</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-af/mainboard.c@76">Patch Set #6, Line 76:</a> <code style="font-family:monospace,monospace"> FCH_GPIO (58) = 0x28;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited between function name and open parenthesis '('</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-af/mainboard.c@77">Patch Set #6, Line 77:</a> <code style="font-family:monospace,monospace"> FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-af/mainboard.c@78">Patch Set #6, Line 78:</a> <code style="font-family:monospace,monospace"> FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/toucan-af/mainboard.c">File src/mainboard/lippert/toucan-af/mainboard.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/toucan-af/mainboard.c@36">Patch Set #6, Line 36:</a> <code style="font-family:monospace,monospace"> FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/toucan-af/mainboard.c@37">Patch Set #6, Line 37:</a> <code style="font-family:monospace,monospace"> FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited between function name and open parenthesis '('</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/toucan-af/mainboard.c@41">Patch Set #6, Line 41:</a> <code style="font-family:monospace,monospace"> FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited between function name and open parenthesis '('</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/toucan-af/mainboard.c@43">Patch Set #6, Line 43:</a> <code style="font-family:monospace,monospace"> FCH_GPIO (57) = 0x28;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited between function name and open parenthesis '('</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/toucan-af/mainboard.c@45">Patch Set #6, Line 45:</a> <code style="font-family:monospace,monospace"> FCH_GPIO (58) = 0x28;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited between function name and open parenthesis '('</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/msi/ms9652_fam10/get_bus_conf.c">File src/mainboard/msi/ms9652_fam10/get_bus_conf.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/msi/ms9652_fam10/get_bus_conf.c@104">Patch Set #6, Line 104:</a> <code style="font-family:monospace,monospace"> dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/msi/ms9652_fam10/get_bus_conf.c@109">Patch Set #6, Line 109:</a> <code style="font-family:monospace,monospace"> printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/pcengines/apu1/OemCustomize.c">File src/mainboard/pcengines/apu1/OemCustomize.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/pcengines/apu1/OemCustomize.c@111">Patch Set #6, Line 111:</a> <code style="font-family:monospace,monospace"> HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/pcengines/apu2/mainboard.c">File src/mainboard/pcengines/apu2/mainboard.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/pcengines/apu2/mainboard.c@175">Patch Set #6, Line 175:</a> <code style="font-family:monospace,monospace"> pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c">File src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c@102">Patch Set #6, Line 102:</a> <code style="font-family:monospace,monospace"> dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c@107">Patch Set #6, Line 107:</a> <code style="font-family:monospace,monospace"> printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c">File src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c@108">Patch Set #6, Line 108:</a> <code style="font-family:monospace,monospace"> dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c@113">Patch Set #6, Line 113:</a> <code style="font-family:monospace,monospace"> printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/tyan/s2912_fam10/get_bus_conf.c">File src/mainboard/tyan/s2912_fam10/get_bus_conf.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/tyan/s2912_fam10/get_bus_conf.c@101">Patch Set #6, Line 101:</a> <code style="font-family:monospace,monospace"> dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/mainboard/tyan/s2912_fam10/get_bus_conf.c@106">Patch Set #6, Line 106:</a> <code style="font-family:monospace,monospace"> printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/northbridge/amd/agesa/family12/dimmSpd.c">File src/northbridge/amd/agesa/family12/dimmSpd.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/northbridge/amd/agesa/family12/dimmSpd.c@58">Patch Set #6, Line 58:</a> <code style="font-family:monospace,monospace"> )</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">please, no spaces at the start of a line</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/northbridge/intel/fsp_rangeley/northbridge.c">File src/northbridge/intel/fsp_rangeley/northbridge.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/northbridge/intel/fsp_rangeley/northbridge.c@134">Patch Set #6, Line 134:</a> <code style="font-family:monospace,monospace"> ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c">File src/soc/broadcom/cygnus/ddr_init.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@73">Patch Set #6, Line 73:</a> <code style="font-family:monospace,monospace"> readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@75">Patch Set #6, Line 75:</a> <code style="font-family:monospace,monospace"> (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R)));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@78">Patch Set #6, Line 78:</a> <code style="font-family:monospace,monospace"> readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@83">Patch Set #6, Line 83:</a> <code style="font-family:monospace,monospace"> readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@85">Patch Set #6, Line 85:</a> <code style="font-family:monospace,monospace"> (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE)));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@87">Patch Set #6, Line 87:</a> <code style="font-family:monospace,monospace"> readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@91">Patch Set #6, Line 91:</a> <code style="font-family:monospace,monospace"> readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@93">Patch Set #6, Line 93:</a> <code style="font-family:monospace,monospace"> (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ)));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@96">Patch Set #6, Line 96:</a> <code style="font-family:monospace,monospace"> readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@98">Patch Set #6, Line 98:</a> <code style="font-family:monospace,monospace"> (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE)));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@100">Patch Set #6, Line 100:</a> <code style="font-family:monospace,monospace"> readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@104">Patch Set #6, Line 104:</a> <code style="font-family:monospace,monospace"> readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@106">Patch Set #6, Line 106:</a> <code style="font-family:monospace,monospace"> (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ)));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@113">Patch Set #6, Line 113:</a> <code style="font-family:monospace,monospace"> (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@118">Patch Set #6, Line 118:</a> <code style="font-family:monospace,monospace"> (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@131">Patch Set #6, Line 131:</a> <code style="font-family:monospace,monospace"> (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@137">Patch Set #6, Line 137:</a> <code style="font-family:monospace,monospace"> (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@143">Patch Set #6, Line 143:</a> <code style="font-family:monospace,monospace"> (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@149">Patch Set #6, Line 149:</a> <code style="font-family:monospace,monospace"> (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) &</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@156">Patch Set #6, Line 156:</a> <code style="font-family:monospace,monospace"> (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) &</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@167">Patch Set #6, Line 167:</a> <code style="font-family:monospace,monospace">#define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@473">Patch Set #6, Line 473:</a> <code style="font-family:monospace,monospace"> reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@479">Patch Set #6, Line 479:</a> <code style="font-family:monospace,monospace"> if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@479">Patch Set #6, Line 479:</a> <code style="font-family:monospace,monospace"> if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@485">Patch Set #6, Line 485:</a> <code style="font-family:monospace,monospace"> if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@989">Patch Set #6, Line 989:</a> <code style="font-family:monospace,monospace"> if ((((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114)))</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@1007">Patch Set #6, Line 1007:</a> <code style="font-family:monospace,monospace"> if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">please, no spaces at the start of a line</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@1142">Patch Set #6, Line 1142:</a> <code style="font-family:monospace,monospace"> for (i = 0; i < 1000; i++);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">please, no spaces at the start of a line</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@1142">Patch Set #6, Line 1142:</a> <code style="font-family:monospace,monospace"> for (i = 0; i < 1000; i++);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">trailing statements should be on next line</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@1402">Patch Set #6, Line 1402:</a> <code style="font-family:monospace,monospace"> printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/phy_reg_access.c">File src/soc/broadcom/cygnus/phy_reg_access.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/phy_reg_access.c@20">Patch Set #6, Line 20:</a> <code style="font-family:monospace,monospace"> data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address)));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/phy_reg_access.c@27">Patch Set #6, Line 27:</a> <code style="font-family:monospace,monospace"> ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/soc/intel/baytrail/perf_power.c">File src/soc/intel/baytrail/perf_power.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/intel/baytrail/perf_power.c@224">Patch Set #6, Line 224:</a> <code style="font-family:monospace,monospace">E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/soc/intel/fsp_baytrail/northcluster.c">File src/soc/intel/fsp_baytrail/northcluster.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/soc/intel/fsp_baytrail/northcluster.c@161">Patch Set #6, Line 161:</a> <code style="font-family:monospace,monospace"> ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.c">File src/southbridge/amd/cimx/sb800/fan.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.c@234">Patch Set #6, Line 234:</a> <code style="font-family:monospace,monospace"> sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.c@238">Patch Set #6, Line 238:</a> <code style="font-family:monospace,monospace"> sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.c@252">Patch Set #6, Line 252:</a> <code style="font-family:monospace,monospace"> sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.c@256">Patch Set #6, Line 256:</a> <code style="font-family:monospace,monospace"> sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.c@270">Patch Set #6, Line 270:</a> <code style="font-family:monospace,monospace"> sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.c@274">Patch Set #6, Line 274:</a> <code style="font-family:monospace,monospace"> sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.c@288">Patch Set #6, Line 288:</a> <code style="font-family:monospace,monospace"> sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.c@292">Patch Set #6, Line 292:</a> <code style="font-family:monospace,monospace"> sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/rs780/gfx.c">File src/southbridge/amd/rs780/gfx.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/rs780/gfx.c@250">Patch Set #6, Line 250:</a> <code style="font-family:monospace,monospace"> if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/rs780/gfx.c@250">Patch Set #6, Line 250:</a> <code style="font-family:monospace,monospace"> if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/sb700/sata.c">File src/southbridge/amd/sb700/sata.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/sb700/sata.c@473">Patch Set #6, Line 473:</a> <code style="font-family:monospace,monospace"> (i % 2) ? "Slave" : "Master", i);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/sr5650/pcie.c">File src/southbridge/amd/sr5650/pcie.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/sr5650/pcie.c@809">Patch Set #6, Line 809:</a> <code style="font-family:monospace,monospace"> if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/intel/bd82x6x/early_usb.c">File src/southbridge/intel/bd82x6x/early_usb.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/intel/bd82x6x/early_usb.c@38">Patch Set #6, Line 38:</a> <code style="font-family:monospace,monospace"> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/intel/fsp_bd82x6x/early_init.c">File src/southbridge/intel/fsp_bd82x6x/early_init.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/intel/fsp_bd82x6x/early_init.c@145">Patch Set #6, Line 145:</a> <code style="font-family:monospace,monospace"> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/intel/fsp_i89xx/early_init.c">File src/southbridge/intel/fsp_i89xx/early_init.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/intel/fsp_i89xx/early_init.c@32">Patch Set #6, Line 32:</a> <code style="font-family:monospace,monospace"> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/nvidia/ck804/early_setup.c">File src/southbridge/nvidia/ck804/early_setup.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29161/6/src/southbridge/nvidia/ck804/early_setup.c@258">Patch Set #6, Line 258:</a> <code style="font-family:monospace,monospace"> RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23),</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/29161">change 29161</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29161"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: comment </div>
<div style="display:none"> Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d </div>
<div style="display:none"> Gerrit-Change-Number: 29161 </div>
<div style="display:none"> Gerrit-PatchSet: 6 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-Comment-Date: Wed, 17 Oct 2018 11:03:40 +0000 </div>
<div style="display:none"> Gerrit-HasComments: Yes </div>
<div style="display:none"> Gerrit-HasLabels: No </div>