<p>Aamir Bohra would like Subrata Banik to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/29162">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/icelake: Initial SoC commit<br><br>Clone entirely from Cannonlake<br>commit id: af89f49b83260a04dece84b34e97560fb85d29ae<br><br>List of changes on top off initial cannonlake clone<br>1. Replace "Cannonlake" with "Icelake"<br>2. Replace "cnl" with "icl"<br>3. Replace "cnp" with "icp"<br>4. Rename structrue based on Cannonlake with Icelake<br>5. Remove and clean below files<br> 5.a. All NHLT blobs and related files.<br> 5.b. remove cnl_memcfg_init.c file, will be added later.<br> 5.c. Remove vr_config.c, this is WIP.<br> 5.d. Clean up upd override in fsp_params.c, will be added once FSP available.<br><br>Ice Lake specific changes will follow in subsequent patches.<br><br>Change-Id: I756fa7275c4190aebc0695f14484498aaf5662a5<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>---<br>M src/soc/intel/Kconfig<br>A src/soc/intel/icelake/Kconfig<br>A src/soc/intel/icelake/Makefile.inc<br>A src/soc/intel/icelake/acpi.c<br>A src/soc/intel/icelake/acpi/cnvi.asl<br>A src/soc/intel/icelake/acpi/cpu.asl<br>A src/soc/intel/icelake/acpi/globalnvs.asl<br>A src/soc/intel/icelake/acpi/gpio.asl<br>A src/soc/intel/icelake/acpi/ipu.asl<br>A src/soc/intel/icelake/acpi/irqlinks.asl<br>A src/soc/intel/icelake/acpi/lpc.asl<br>A src/soc/intel/icelake/acpi/northbridge.asl<br>A src/soc/intel/icelake/acpi/pch_glan.asl<br>A src/soc/intel/icelake/acpi/pch_hda.asl<br>A src/soc/intel/icelake/acpi/pci_irqs.asl<br>A src/soc/intel/icelake/acpi/pcie.asl<br>A src/soc/intel/icelake/acpi/platform.asl<br>A src/soc/intel/icelake/acpi/scs.asl<br>A src/soc/intel/icelake/acpi/serialio.asl<br>A src/soc/intel/icelake/acpi/sleepstates.asl<br>A src/soc/intel/icelake/acpi/smbus.asl<br>A src/soc/intel/icelake/acpi/southbridge.asl<br>A src/soc/intel/icelake/acpi/xhci.asl<br>A src/soc/intel/icelake/bootblock/bootblock.c<br>A src/soc/intel/icelake/bootblock/cpu.c<br>A src/soc/intel/icelake/bootblock/pch.c<br>A src/soc/intel/icelake/bootblock/report_platform.c<br>A src/soc/intel/icelake/cbmem.c<br>A src/soc/intel/icelake/chip.c<br>A src/soc/intel/icelake/chip.h<br>A src/soc/intel/icelake/cpu.c<br>A src/soc/intel/icelake/finalize.c<br>A src/soc/intel/icelake/fsp_params.c<br>A src/soc/intel/icelake/gpio.c<br>A src/soc/intel/icelake/graphics.c<br>A src/soc/intel/icelake/gspi.c<br>A src/soc/intel/icelake/i2c.c<br>A src/soc/intel/icelake/include/soc/bootblock.h<br>A src/soc/intel/icelake/include/soc/cpu.h<br>A src/soc/intel/icelake/include/soc/ebda.h<br>A src/soc/intel/icelake/include/soc/gpe.h<br>A src/soc/intel/icelake/include/soc/gpio.h<br>A src/soc/intel/icelake/include/soc/gpio_defs.h<br>A src/soc/intel/icelake/include/soc/gpio_soc_defs.h<br>A src/soc/intel/icelake/include/soc/iomap.h<br>A src/soc/intel/icelake/include/soc/irq.h<br>A src/soc/intel/icelake/include/soc/itss.h<br>A src/soc/intel/icelake/include/soc/lpc.h<br>A src/soc/intel/icelake/include/soc/msr.h<br>A src/soc/intel/icelake/include/soc/nvs.h<br>A src/soc/intel/icelake/include/soc/p2sb.h<br>A src/soc/intel/icelake/include/soc/pch.h<br>A src/soc/intel/icelake/include/soc/pci_devs.h<br>A src/soc/intel/icelake/include/soc/pcr_ids.h<br>A src/soc/intel/icelake/include/soc/pm.h<br>A src/soc/intel/icelake/include/soc/pmc.h<br>A src/soc/intel/icelake/include/soc/ramstage.h<br>A src/soc/intel/icelake/include/soc/romstage.h<br>A src/soc/intel/icelake/include/soc/serialio.h<br>A src/soc/intel/icelake/include/soc/smbus.h<br>A src/soc/intel/icelake/include/soc/smm.h<br>A src/soc/intel/icelake/include/soc/soc_chip.h<br>A src/soc/intel/icelake/include/soc/systemagent.h<br>A src/soc/intel/icelake/include/soc/usb.h<br>A src/soc/intel/icelake/lockdown.c<br>A src/soc/intel/icelake/lpc.c<br>A src/soc/intel/icelake/memmap.c<br>A src/soc/intel/icelake/p2sb.c<br>A src/soc/intel/icelake/pmc.c<br>A src/soc/intel/icelake/pmutil.c<br>A src/soc/intel/icelake/reset.c<br>A src/soc/intel/icelake/romstage/Makefile.inc<br>A src/soc/intel/icelake/romstage/fsp_params.c<br>A src/soc/intel/icelake/romstage/power_state.c<br>A src/soc/intel/icelake/romstage/romstage.c<br>A src/soc/intel/icelake/romstage/systemagent.c<br>A src/soc/intel/icelake/sd.c<br>A src/soc/intel/icelake/smihandler.c<br>A src/soc/intel/icelake/smmrelocate.c<br>A src/soc/intel/icelake/spi.c<br>A src/soc/intel/icelake/systemagent.c<br>A src/soc/intel/icelake/uart.c<br>82 files changed, 8,713 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29162/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig</span><br><span>index 5b4a9a2..2c24596 100644</span><br><span>--- a/src/soc/intel/Kconfig</span><br><span>+++ b/src/soc/intel/Kconfig</span><br><span>@@ -10,6 +10,7 @@</span><br><span> source "src/soc/intel/quark/Kconfig"</span><br><span> source "src/soc/intel/sch/Kconfig"</span><br><span> source "src/soc/intel/skylake/Kconfig"</span><br><span style="color: hsl(120, 100%, 40%);">+source "src/soc/intel/icelake/Kconfig"</span><br><span> </span><br><span> # Load common config</span><br><span> source "src/soc/intel/common/Kconfig"</span><br><span>diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig</span><br><span>new file mode 100755</span><br><span>index 0000000..02f41bf</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/Kconfig</span><br><span>@@ -0,0 +1,211 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_ICELAKE</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel Icelake support</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if SOC_INTEL_ICELAKE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CPU_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select ACPI_INTEL_HARDWARE_SLEEP_VALUES</span><br><span style="color: hsl(120, 100%, 40%);">+ select ARCH_BOOTBLOCK_X86_32</span><br><span style="color: hsl(120, 100%, 40%);">+ select ARCH_RAMSTAGE_X86_32</span><br><span style="color: hsl(120, 100%, 40%);">+ select ARCH_ROMSTAGE_X86_32</span><br><span style="color: hsl(120, 100%, 40%);">+ select ARCH_VERSTAGE_X86_32</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOOT_DEVICE_SUPPORTS_WRITES</span><br><span style="color: hsl(120, 100%, 40%);">+ select C_ENVIRONMENT_BOOTBLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ select CACHE_MRC_SETTINGS</span><br><span style="color: hsl(120, 100%, 40%);">+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM</span><br><span style="color: hsl(120, 100%, 40%);">+ select COMMON_FADT</span><br><span style="color: hsl(120, 100%, 40%);">+ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select GENERIC_GPIO_LIB</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_FSP_GOP</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_HARD_RESET</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_DESCRIPTOR_MODE_CAPABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_MONOTONIC_TIMER</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_SMI_HANDLER</span><br><span style="color: hsl(120, 100%, 40%);">+ select IDT_IN_EVERY_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_GMA_ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_GMA_ADD_VBT if RUN_FSP_GOP</span><br><span style="color: hsl(120, 100%, 40%);">+ select IOAPIC</span><br><span style="color: hsl(120, 100%, 40%);">+ select MRC_SETTINGS_PROTECT</span><br><span style="color: hsl(120, 100%, 40%);">+ select PARALLEL_MP</span><br><span style="color: hsl(120, 100%, 40%);">+ select PARALLEL_MP_AP_WORK</span><br><span style="color: hsl(120, 100%, 40%);">+ select PLATFORM_USES_FSP2_0</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_CONSOLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select REG_SCRIPT</span><br><span style="color: hsl(120, 100%, 40%);">+ select SMM_TSEG</span><br><span style="color: hsl(120, 100%, 40%);">+ select SMP</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_AHCI_PORT_IMPLEMENTED_INVERT</span><br><span style="color: hsl(120, 100%, 40%);">+ select PMC_GLOBAL_RESET_ENABLE_LOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_SA</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_SMM</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_PCH_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_RESET</span><br><span style="color: hsl(120, 100%, 40%);">+ select SSE2</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPPORT_CPU_UCODE_IN_CBFS</span><br><span style="color: hsl(120, 100%, 40%);">+ select TSC_CONSTANT_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+ select TSC_MONOTONIC_TIMER</span><br><span style="color: hsl(120, 100%, 40%);">+ select UDELAY_TSC</span><br><span style="color: hsl(120, 100%, 40%);">+ select UDK_2017_BINDING</span><br><span style="color: hsl(120, 100%, 40%);">+ select DISPLAY_FSP_VERSION_INFO</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config UART_DEBUG</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Enable UART debug port."</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ select CONSOLE_SERIAL</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOOTBLOCK_CONSOLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_UART</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_UART_8250MEM_32</span><br><span style="color: hsl(120, 100%, 40%);">+ select NO_UART_ON_SUPERIO</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config UART_FOR_CONSOLE</span><br><span style="color: hsl(120, 100%, 40%);">+ int "Index for LPSS UART port to use for console"</span><br><span style="color: hsl(120, 100%, 40%);">+ default 2 if DRIVERS_UART_8250MEM_32</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Index for LPSS UART port to use for console:</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DCACHE_RAM_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xfef00000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DCACHE_RAM_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x40000</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ The size of the cache-as-ram region required during bootblock</span><br><span style="color: hsl(120, 100%, 40%);">+ and/or romstage.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DCACHE_BSP_STACK_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x4000</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ The amount of anticipated stack usage in CAR by bootblock and</span><br><span style="color: hsl(120, 100%, 40%);">+ other stages.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config IFD_CHIPSET</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "icl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config IED_REGION_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x400000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config HEAP_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x8000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_ROOT_PORTS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SMM_TSEG_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x800000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SMM_RESERVED_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x200000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config PCR_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xfd000000</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ This option allows you to select MMIO Base Address of sideband bus.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CPU_BCLK_MHZ</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 100</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 120</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 133</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BLOCK_GSPI_MAX</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_I2C_DEV_MAX</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# Clock divider parameters for 115200 baud rate</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xc35</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+ select CHROMEOS_RAMOOPS_DYNAMIC</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_SEPARATE_VERSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_OPROM_MATTERS</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_STARTS_IN_BOOTBLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_VBNV_CMOS</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config C_ENV_BOOTBLOCK_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x8000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CBFS_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x200000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+choice</span><br><span style="color: hsl(120, 100%, 40%);">+ prompt "Cache-as-ram implementation"</span><br><span style="color: hsl(120, 100%, 40%);">+ default USE_ICELAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+ default USE_ICELAKE_FSP_CAR</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ This option allows you to select how cache-as-ram (CAR) is set up.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config USE_ICELAKE_CAR_NEM_ENHANCED</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Enhanced Non-evict mode"</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_CAR</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_CAR_NEM_ENHANCED</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ A current limitation of NEM (Non-Evict mode) is that code and data</span><br><span style="color: hsl(120, 100%, 40%);">+ sizes are derived from the requirement to not write out any modified</span><br><span style="color: hsl(120, 100%, 40%);">+ cache line. With NEM, if there is no physical memory behind the</span><br><span style="color: hsl(120, 100%, 40%);">+ cached area, the modified data will be lost and NEM results will be</span><br><span style="color: hsl(120, 100%, 40%);">+ inconsistent. ENHANCED NEM guarantees that modified data is always</span><br><span style="color: hsl(120, 100%, 40%);">+ kept in cache while clean data is replaced.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config USE_ICELAKE_FSP_CAR</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Use FSP CAR"</span><br><span style="color: hsl(120, 100%, 40%);">+ select FSP_CAR</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Use FSP APIs to initialize and tear down the Cache-As-Ram.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endchoice</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config FSP_HEADER_PATH</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "src/vendorcode/intel/fsp/fsp2_0/icelake/" if SOC_INTEL_ICELAKE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config FSP_FD_PATH</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on FSP_USE_REPO</span><br><span style="color: hsl(120, 100%, 40%);">+ default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" if SOC_INTEL_ICELAKE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc</span><br><span>new file mode 100755</span><br><span>index 0000000..a81edd4</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/Makefile.inc</span><br><span>@@ -0,0 +1,80 @@</span><br><span style="color: hsl(120, 100%, 40%);">+ifeq ($(CONFIG_SOC_INTEL_ICELAKE),y)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += romstage</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += ../../../cpu/intel/microcode</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += ../../../cpu/intel/turbo</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += ../../../cpu/x86/lapic</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += ../../../cpu/x86/mtrr</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += ../../../cpu/x86/smm</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += ../../../cpu/x86/tsc</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock/bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock/cpu.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock/pch.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += pmutil.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock/report_platform.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += memmap.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += lpc.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += p2sb.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_UART_DEBUG) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += lpc.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += memmap.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += pmutil.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += reset.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_UART_DEBUG) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += acpi.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += chip.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += cpu.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += finalize.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += fsp_params.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += graphics.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += lockdown.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += lpc.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += memmap.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += p2sb.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += pmc.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += pmutil.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += smmrelocate.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += systemagent.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_UART_DEBUG) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += sd.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+smm-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-y += p2sb.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-y += pmutil.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-y += smihandler.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-$(CONFIG_UART_DEBUG) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += memmap.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += pmutil.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_UART_DEBUG) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += pmutil.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_UART_DEBUG) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CPPFLAGS_common += -I$(src)/soc/intel/icelake</span><br><span style="color: hsl(120, 100%, 40%);">+CPPFLAGS_common += -I$(src)/soc/intel/icelake/include</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c</span><br><span>new file mode 100755</span><br><span>index 0000000..2c4ed09</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi.c</span><br><span>@@ -0,0 +1,251 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpigen.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/ioapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/smp/mpspec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/google/chromeec/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/cpulib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pmclib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <vendorcode/google/chromeos/gnvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <wrdd.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * List of supported C-states in this processor.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C0, /* 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C1, /* 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C1E, /* 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C6_SHORT_LAT, /* 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C6_LONG_LAT, /* 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C7_SHORT_LAT, /* 5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C7_LONG_LAT, /* 6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C7S_SHORT_LAT, /* 7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C7S_LONG_LAT, /* 8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C8, /* 9 */</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C9, /* 10 */</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C10, /* 11 */</span><br><span style="color: hsl(120, 100%, 40%);">+ NUM_C_STATES</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MWAIT_RES(state, sub_state) \</span><br><span style="color: hsl(120, 100%, 40%);">+ { \</span><br><span style="color: hsl(120, 100%, 40%);">+ .addrl = (((state) << 4) | (sub_state)), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .space_id = ACPI_ADDRESS_SPACE_FIXED, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const acpi_cstate_t cstate_map[NUM_C_STATES] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ [C_STATE_C0] = {},</span><br><span style="color: hsl(120, 100%, 40%);">+ [C_STATE_C1] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .latency = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .power = C1_POWER,</span><br><span style="color: hsl(120, 100%, 40%);">+ .resource = MWAIT_RES(0, 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [C_STATE_C1E] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .latency = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .power = C1_POWER,</span><br><span style="color: hsl(120, 100%, 40%);">+ .resource = MWAIT_RES(0, 1),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [C_STATE_C6_SHORT_LAT] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ .power = C6_POWER,</span><br><span style="color: hsl(120, 100%, 40%);">+ .resource = MWAIT_RES(2, 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [C_STATE_C6_LONG_LAT] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ .power = C6_POWER,</span><br><span style="color: hsl(120, 100%, 40%);">+ .resource = MWAIT_RES(2, 1),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [C_STATE_C7_SHORT_LAT] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ .power = C7_POWER,</span><br><span style="color: hsl(120, 100%, 40%);">+ .resource = MWAIT_RES(3, 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [C_STATE_C7_LONG_LAT] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ .power = C7_POWER,</span><br><span style="color: hsl(120, 100%, 40%);">+ .resource = MWAIT_RES(3, 1),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [C_STATE_C7S_SHORT_LAT] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ .power = C7_POWER,</span><br><span style="color: hsl(120, 100%, 40%);">+ .resource = MWAIT_RES(3, 2),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [C_STATE_C7S_LONG_LAT] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ .power = C7_POWER,</span><br><span style="color: hsl(120, 100%, 40%);">+ .resource = MWAIT_RES(3, 3),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [C_STATE_C8] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ .power = C8_POWER,</span><br><span style="color: hsl(120, 100%, 40%);">+ .resource = MWAIT_RES(4, 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [C_STATE_C9] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ .power = C9_POWER,</span><br><span style="color: hsl(120, 100%, 40%);">+ .resource = MWAIT_RES(5, 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [C_STATE_C10] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ .power = C10_POWER,</span><br><span style="color: hsl(120, 100%, 40%);">+ .resource = MWAIT_RES(6, 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int cstate_set_s0ix[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C1E,</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C6_LONG_LAT,</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C7S_LONG_LAT</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int cstate_set_non_s0ix[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C1E,</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C7S_LONG_LAT,</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_C10</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+acpi_cstate_t *soc_get_cstate_map(size_t *entries)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),</span><br><span style="color: hsl(120, 100%, 40%);">+ ARRAY_SIZE(cstate_set_non_s0ix))];</span><br><span style="color: hsl(120, 100%, 40%);">+ int *set;</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ config_t *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ int is_s0ix_enable = config->s0ix_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (is_s0ix_enable) {</span><br><span style="color: hsl(120, 100%, 40%);">+ *entries = ARRAY_SIZE(cstate_set_s0ix);</span><br><span style="color: hsl(120, 100%, 40%);">+ set = cstate_set_s0ix;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ *entries = ARRAY_SIZE(cstate_set_non_s0ix);</span><br><span style="color: hsl(120, 100%, 40%);">+ set = cstate_set_non_s0ix;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < *entries; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));</span><br><span style="color: hsl(120, 100%, 40%);">+ map[i].ctype = i + 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return map;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_power_states_generation(int core_id, int cores_per_package)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ config_t *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->eist_enable)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Generate P-state tables */</span><br><span style="color: hsl(120, 100%, 40%);">+ generate_p_state_entries(core_id, cores_per_package);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_fill_fadt(acpi_fadt_t *fadt)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint16_t pmbase = ACPI_BASE_ADDRESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *dev = PCH_DEV_LPC;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_intel_icelake_config *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!config->PmTimerDisabled) {</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->pm_tmr_blk = pmbase + PM1_TMR;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->pm_tmr_len = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm_tmr_blk.space_id = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm_tmr_blk.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm_tmr_blk.resv = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm_tmr_blk.addrh = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->s0ix_enable)</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t soc_read_sci_irq_select(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t pmc_bar = soc_read_pmc_base();</span><br><span style="color: hsl(120, 100%, 40%);">+ return read32((void *)pmc_bar + IRQ_REG);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(struct global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *dev = PCH_DEV_LPC;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_intel_icelake_config *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set unknown wake source */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->pm1i = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU core count */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->pcnt = dev_count_cpu();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Update the mem console pointer. */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_CHROMEOS)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize Verified Boot data */</span><br><span style="color: hsl(120, 100%, 40%);">+ chromeos_init_chromeos_acpi(&(gnvs->chromeos));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->chromeos.vbt2 = google_ec_running_ro() ?</span><br><span style="color: hsl(120, 100%, 40%);">+ ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable DPTF based on mainboard configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->dpte = config->dptf_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Fill in the Wifi Region id */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->cid1 = wifi_regulatory_domain();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set USB2/USB3 wake enable bitmaps. */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->u2we = config->usb2_wake_enable_bitmap;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->u3we = config->usb3_wake_enable_bitmap;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct chipset_power_state *ps)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * WAK_STS bit is set when the system is in one of the sleep states</span><br><span style="color: hsl(120, 100%, 40%);">+ * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting</span><br><span style="color: hsl(120, 100%, 40%);">+ * this bit, the PMC will transition the system to the ON state and</span><br><span style="color: hsl(120, 100%, 40%);">+ * can only be set by hardware and can only be cleared by writing a one</span><br><span style="color: hsl(120, 100%, 40%);">+ * to this bit position.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+ return generic_pm1_en;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int soc_madt_sci_irq_polarity(int sci)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return MP_IRQ_POLARITY_HIGH;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/cnvi.asl b/src/soc/intel/icelake/acpi/cnvi.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..634c609</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/cnvi.asl</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* CNVi Controller 0:14.3 */</span><br><span style="color: hsl(120, 100%, 40%);">+Device (CNVI) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_ADR, 0x00140003)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_S3D, 3) /* D3 supported in S3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_S0W, 3) /* D3 can wake device in S0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_S3W, 3) /* D3 can wake system from S3 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRW, Package() { PME_B0_EN_BIT, 3 })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xF)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/cpu.asl b/src/soc/intel/icelake/acpi/cpu.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..be6e793</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/cpu.asl</span><br><span>@@ -0,0 +1,43 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* These devices are created at runtime */</span><br><span style="color: hsl(120, 100%, 40%);">+External (\_PR.CP00, DeviceObj)</span><br><span style="color: hsl(120, 100%, 40%);">+External (\_PR.CP01, DeviceObj)</span><br><span style="color: hsl(120, 100%, 40%);">+External (\_PR.CP02, DeviceObj)</span><br><span style="color: hsl(120, 100%, 40%);">+External (\_PR.CP03, DeviceObj)</span><br><span style="color: hsl(120, 100%, 40%);">+External (\_PR.CP04, DeviceObj)</span><br><span style="color: hsl(120, 100%, 40%);">+External (\_PR.CP05, DeviceObj)</span><br><span style="color: hsl(120, 100%, 40%);">+External (\_PR.CP06, DeviceObj)</span><br><span style="color: hsl(120, 100%, 40%);">+External (\_PR.CP07, DeviceObj)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Notify OS to re-read CPU tables, assuming ^2 CPU count */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (PNOT)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LGreaterEqual (\PCNT, 2)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify (\_PR.CP00, 0x81) // _CST</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify (\_PR.CP01, 0x81) // _CST</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LGreaterEqual (\PCNT, 4)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify (\_PR.CP02, 0x81) // _CST</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify (\_PR.CP03, 0x81) // _CST</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LGreaterEqual (\PCNT, 8)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify (\_PR.CP04, 0x81) // _CST</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify (\_PR.CP05, 0x81) // _CST</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify (\_PR.CP06, 0x81) // _CST</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify (\_PR.CP07, 0x81) // _CST</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/globalnvs.asl b/src/soc/intel/icelake/acpi/globalnvs.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..678ce5a</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/globalnvs.asl</span><br><span>@@ -0,0 +1,55 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Global Variables */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (\PICM, 0) // IOAPIC/8259</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Global ACPI memory region. This region is used for passing information</span><br><span style="color: hsl(120, 100%, 40%);">+ * between coreboot (aka "the system bios"), ACPI, and the SMI handler.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Since we don't know where this will end up in memory at ACPI compile time,</span><br><span style="color: hsl(120, 100%, 40%);">+ * we have to fix it up in coreboot's ACPI creation phase.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+External (NVSA)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)</span><br><span style="color: hsl(120, 100%, 40%);">+Field (GNVS, ByteAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Miscellaneous */</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x00),</span><br><span style="color: hsl(120, 100%, 40%);">+ OSYS, 16, // 0x00 - Operating System</span><br><span style="color: hsl(120, 100%, 40%);">+ SMIF, 8, // 0x02 - SMI function</span><br><span style="color: hsl(120, 100%, 40%);">+ PCNT, 8, // 0x03 - Processor Count</span><br><span style="color: hsl(120, 100%, 40%);">+ PPCM, 8, // 0x04 - Max PPC State</span><br><span style="color: hsl(120, 100%, 40%);">+ TLVL, 8, // 0x05 - Throttle Level Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ LIDS, 8, // 0x06 - LID State</span><br><span style="color: hsl(120, 100%, 40%);">+ PWRS, 8, // 0x07 - AC Power State</span><br><span style="color: hsl(120, 100%, 40%);">+ CBMC, 32, // 0x08 - 0x0b AC Power State</span><br><span style="color: hsl(120, 100%, 40%);">+ PM1I, 64, // 0x0c - 0x13 PM1 wake status bit</span><br><span style="color: hsl(120, 100%, 40%);">+ GPEI, 64, // 0x14 - 0x17 GPE wake status bit</span><br><span style="color: hsl(120, 100%, 40%);">+ DPTE, 8, // 0x1c - Enable DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ NHLA, 64, // 0x1d - 0x24 NHLT Address</span><br><span style="color: hsl(120, 100%, 40%);">+ NHLL, 32, // 0x25 - 0x28 NHLT Length</span><br><span style="color: hsl(120, 100%, 40%);">+ CID1, 16, // 0x29 - 0x2a Wifi Country Identifier</span><br><span style="color: hsl(120, 100%, 40%);">+ U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap</span><br><span style="color: hsl(120, 100%, 40%);">+ U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap</span><br><span style="color: hsl(120, 100%, 40%);">+ UIOR, 8, // 0x2f - UART debug controller init on S3 resume</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ChromeOS specific */</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x100),</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <vendorcode/google/chromeos/acpi/gnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/gpio.asl b/src/soc/intel/icelake/acpi/gpio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..5784fb1</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/gpio.asl</span><br><span>@@ -0,0 +1,134 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio_defs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/irq.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (GPIO)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, "INT34BB")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "GPIO Controller")</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RBUF, ResourceTemplate()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadWrite, 0, 0, COM0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadWrite, 0, 0, COM1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadWrite, 0, 0, COM2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadWrite, 0, 0, COM3)</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadWrite, 0, 0, COM4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPIO_IRQ14 }</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDWordField (^RBUF, ^COM0._BAS, BAS0)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDWordField (^RBUF, ^COM0._LEN, LEN0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (^^PCRB (PID_GPIOCOM0), BAS0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (GPIO_BASE_SIZE, LEN0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDWordField (^RBUF, ^COM1._BAS, BAS1)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDWordField (^RBUF, ^COM1._LEN, LEN1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (^^PCRB (PID_GPIOCOM1), BAS1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (GPIO_BASE_SIZE, LEN1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDWordField (^RBUF, ^COM2._BAS, BAS2)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDWordField (^RBUF, ^COM2._LEN, LEN2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (^^PCRB (PID_GPIOCOM2), BAS2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (GPIO_BASE_SIZE, LEN2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDWordField (^RBUF, ^COM3._BAS, BAS3)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDWordField (^RBUF, ^COM3._LEN, LEN3)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (^^PCRB (PID_GPIOCOM3), BAS3)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (GPIO_BASE_SIZE, LEN3)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDWordField (^RBUF, ^COM4._BAS, BAS4)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDWordField (^RBUF, ^COM4._LEN, LEN4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (^^PCRB (PID_GPIOCOM4), BAS4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (GPIO_BASE_SIZE, LEN4)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RBUF)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xF)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Get GPIO DW0 Address</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0 - GPIO Number</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (GADD, 1, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPIO_RSVD_11)))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PID_GPIOCOM0, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Arg0, GPP_A0, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPIO_RSVD_52)))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PID_GPIOCOM1, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Arg0, GPP_D0, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, GPD11)))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PID_GPIOCOM1, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Arg0, GPD0, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_78)))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PID_GPIOCOM1, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Arg0, HDA_BCLK, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 04*/</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_67)))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PID_GPIOCOM4, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Arg0, GPP_C0, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PCRB (Local0), Local2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Add (Local2, PAD_CFG_BASE, Local2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Add (Local2, Multiply (Local1, 16)))</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Get GPIO Value</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0 - GPIO Number</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (GRXS, 1, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (PREG, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ VAL0, 32</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/ipu.asl b/src/soc/intel/icelake/acpi/ipu.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..2c550ed</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/ipu.asl</span><br><span>@@ -0,0 +1,23 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* IPU3 input system - Device 05, Function 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+Device (IMGU)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00050000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Imaging Unit")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_CCA, ZERO)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (CAMD, 0x01)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/irqlinks.asl b/src/soc/intel/icelake/acpi/irqlinks.asl</span><br><span>new file mode 100755</span><br><span>index 0000000..0403ea0</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/irqlinks.asl</span><br><span>@@ -0,0 +1,282 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PIRQ routing control is in PCR ITSS region.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Due to what appears to be an ACPI interpreter bug we do not use</span><br><span style="color: hsl(120, 100%, 40%);">+ * the PCRB() method here as it may not be defined yet because the method</span><br><span style="color: hsl(120, 100%, 40%);">+ * definiton depends on the order of the include files in pch.asl.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * https://bugs.acpica.org/show_bug.cgi?id=1201</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+OperationRegion (ITSS, SystemMemory,</span><br><span style="color: hsl(120, 100%, 40%);">+ Add (PCR_ITSS_PIRQA_ROUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ Add (CONFIG_PCR_BASE_ADDRESS,</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8)</span><br><span style="color: hsl(120, 100%, 40%);">+Field (ITSS, ByteAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRA, 8, /* PIRQA Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRB, 8, /* PIRQB Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRC, 8, /* PIRQC Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRD, 8, /* PIRQD Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRE, 8, /* PIRQE Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRF, 8, /* PIRQF Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRG, 8, /* PIRQG Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRH, 8, /* PIRQH Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (IREN, 0x80) /* Interrupt Routing Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+Name (IREM, 0x0f) /* Interrupt Routing Mask */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKA)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLA, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLA, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRA, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLA)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRA, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKB)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLB, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {10}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLB, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRB, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLB)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRB, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKC)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLC, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLC, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRC, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLC)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRC, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKD)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLD, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLD, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRD, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLD)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRD, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKE)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLE, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLE, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRE, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLE)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRE, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKF)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLF, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLF, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRF, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLF)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRF, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKG)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 7)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLG, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLG, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRG, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLG)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRG, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKH)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 8)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLH, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLH, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRH, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLH)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRH, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/lpc.asl b/src/soc/intel/icelake/acpi/lpc.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..f936392</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/lpc.asl</span><br><span>@@ -0,0 +1,115 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LPCB)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001f0000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "LPC Bus Device")</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (FWH)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("INT0800"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Firmware Hub")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_CRS, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HPET)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0103"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "High Precision Event Timer")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_CRS, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xf)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PIC)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0000"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "8259 Interrupt Controller")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_CRS, ResourceTemplate()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x20, 0x20, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x24, 0x24, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x28, 0x28, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x30, 0x30, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x34, 0x34, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x38, 0x38, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0xac, 0xac, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () { 2 }</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (LDRC)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C02"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Legacy Device Resources")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_CRS, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1, 0xff)</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (RTC)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0B00"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Real Time Clock")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_CRS, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x70, 0x70, 1, 8)</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (TIMR)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0100"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "8254 Timer")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_CRS, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x40, 0x40, 0x01, 0x04)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x50, 0x50, 0x10, 0x04)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () {0}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/northbridge.asl b/src/soc/intel/icelake/acpi/northbridge.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..efd0f9a</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/northbridge.asl</span><br><span>@@ -0,0 +1,340 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BASE_32GB 0x800000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIZE_16GB 0x400000000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID</span><br><span style="color: hsl(120, 100%, 40%);">+Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID</span><br><span style="color: hsl(120, 100%, 40%);">+Name (_SEG, Zero) // _SEG: PCI Segment</span><br><span style="color: hsl(120, 100%, 40%);">+Name (_ADR, Zero) // _ADR: Address</span><br><span style="color: hsl(120, 100%, 40%);">+Name (_UID, Zero) // _UID: Unique ID</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (MCHC)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00000000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (MCHP, PCI_Config, 0x00, 0x100)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (MCHP, DWordAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x40), /* EPBAR (0:0:0:40) */</span><br><span style="color: hsl(120, 100%, 40%);">+ EPEN, 1, /* Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ , 11,</span><br><span style="color: hsl(120, 100%, 40%);">+ EPBR, 20, /* EPBAR [31:12] */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x48), /* MCHBAR (0:0:0:48) */</span><br><span style="color: hsl(120, 100%, 40%);">+ MHEN, 1, /* Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ , 14,</span><br><span style="color: hsl(120, 100%, 40%);">+ MHBR, 17, /* MCHBAR [31:15] */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x60), /* PCIEXBAR (0:0:0:60) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PXEN, 1, /* Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ PXSZ, 2, /* PCI Express Size */</span><br><span style="color: hsl(120, 100%, 40%);">+ , 23,</span><br><span style="color: hsl(120, 100%, 40%);">+ PXBR, 6, /* PCI Express BAR [31:26] */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x68), /* DMIBAR (0:0:0:68) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DIEN, 1, /* Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ , 11,</span><br><span style="color: hsl(120, 100%, 40%);">+ DIBR, 20, /* DMIBAR [31:12] */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0xa0), /* Top of Used Memory */</span><br><span style="color: hsl(120, 100%, 40%);">+ TOM, 64,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0xa8), /* Top of Upper Used Memory */</span><br><span style="color: hsl(120, 100%, 40%);">+ TUUD, 64,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0xbc), /* Top of Low Used Memory */</span><br><span style="color: hsl(120, 100%, 40%);">+ TLUD, 32,</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (MCRS, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus Numbers */</span><br><span style="color: hsl(120, 100%, 40%);">+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IO Region 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,</span><br><span style="color: hsl(120, 100%, 40%);">+ EntireRange,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI Config Space */</span><br><span style="color: hsl(120, 100%, 40%);">+ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IO Region 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,</span><br><span style="color: hsl(120, 100%, 40%);">+ EntireRange,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* VGA memory (0xa0000-0xbffff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00020000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* OPROM reserved (0xc0000-0xc3fff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00004000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* OPROM reserved (0xc4000-0xc7fff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00004000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* OPROM reserved (0xc8000-0xcbfff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00004000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* OPROM reserved (0xcc000-0xcffff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00004000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* OPROM reserved (0xd0000-0xd3fff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00004000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* OPROM reserved (0xd4000-0xd7fff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00004000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* OPROM reserved (0xd8000-0xdbfff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00004000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* OPROM reserved (0xdc000-0xdffff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00004000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* BIOS Extension (0xe0000-0xe3fff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00004000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* BIOS Extension (0xe4000-0xe7fff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00004000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* BIOS Extension (0xe8000-0xebfff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00004000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* BIOS Extension (0xec000-0xeffff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000ec000, 0x000effff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00004000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* System BIOS (0xf0000-0xfffff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00010000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI Memory Region (TLUD - 0xdfffffff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ NonCacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xE0000000,,, PM01)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */</span><br><span style="color: hsl(120, 100%, 40%);">+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ NonCacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0x10000, 0x1ffff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10000,,, PM02)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCH reserved resource (0xfc800000-0xfe7fffff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, PCH_PRESERVED_BASE_SIZE)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TPM Area (0xfed40000-0xfed47fff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00008000)</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Find PCI resource area in MCRS */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField (^MCRS, ^PM01._MIN, PMIN)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField (^MCRS, ^PM01._MAX, PMAX)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField (^MCRS, ^PM01._LEN, PLEN)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Fix up PCI memory region</span><br><span style="color: hsl(120, 100%, 40%);">+ * Start with Top of Lower Usable DRAM</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (^MCHC.TLUD, PMIN)</span><br><span style="color: hsl(120, 100%, 40%);">+ Add (Subtract (PMAX, PMIN), 1, PLEN)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Patch PM02 range based on Memory Size */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateQwordField (^MCRS, ^PM02._MIN, MMIN)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateQwordField (^MCRS, ^PM02._MAX, MMAX)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateQwordField (^MCRS, ^PM02._LEN, MLEN)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (^MCHC.TUUD, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LLessEqual (Local0, BASE_32GB)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (BASE_32GB, MMIN)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (SIZE_16GB, MLEN)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, MMIN)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, MLEN)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Add (MMIN, MLEN), 1, MMAX)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (^MCRS)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (EP_B, 0) /* to store EP BAR */</span><br><span style="color: hsl(120, 100%, 40%);">+Name (MH_B, 0) /* to store MCH BAR */</span><br><span style="color: hsl(120, 100%, 40%);">+Name (PC_B, 0) /* to store PCIe BAR */</span><br><span style="color: hsl(120, 100%, 40%);">+Name (PC_L, 0) /* to store PCIe BAR Length */</span><br><span style="color: hsl(120, 100%, 40%);">+Name (DM_B, 0) /* to store DMI BAR */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Get MCH BAR */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (GMHB, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (MH_B, 0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (MH_B)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Get EP BAR */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (GEPB, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (EP_B, 0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (EP_B)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Get PCIe BAR */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (GPCB, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (PC_B, 0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (PC_B)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Get PCIe Length */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (GPCL, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (PC_L, 0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (PC_L)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Get DMI BAR */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (GDMB, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (DM_B, 0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (DM_B)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCI Device Resource Consumption */</span><br><span style="color: hsl(120, 100%, 40%);">+Device (PDRC)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C02"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (BUF0, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MCH BAR _BAS will be updated in _CRS below according to</span><br><span style="color: hsl(120, 100%, 40%);">+ * B0:D0:F0:Reg.48h</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DMI BAR _BAS will be updated in _CRS below according to</span><br><span style="color: hsl(120, 100%, 40%);">+ * B0:D0:F0:Reg.68h</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* EP BAR _BAS will be updated in _CRS below according to</span><br><span style="color: hsl(120, 100%, 40%);">+ * B0:D0:F0:Reg.40h</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI Express BAR _BAS and _LEN will be updated in</span><br><span style="color: hsl(120, 100%, 40%);">+ * _CRS below according to B0:D0:F0:Reg.60h</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadWrite, 0, 0, PCIX)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* VTD engine memory range.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FLASH range */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadOnly, 0xFFF00000, 0x1000000, FIOH)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* HPET address decode range */</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField (BUF0, ^MCHB._BAS, MBR0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (\_SB.PCI0.GMHB (), MBR0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField (BUF0, ^DMIB._BAS, DBR0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (\_SB.PCI0.GDMB (), DBR0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField (BUF0, ^EGPB._BAS, EBR0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (\_SB.PCI0.GEPB (), EBR0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField (BUF0, ^PCIX._BAS, XBR0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (\_SB.PCI0.GPCB (), XBR0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField (BUF0, ^PCIX._LEN, XSZ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (\_SB.PCI0.GPCL (), XSZ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (BUF0)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/pch_glan.asl b/src/soc/intel/icelake/acpi/pch_glan.asl</span><br><span>new file mode 100755</span><br><span>index 0000000..260dd44</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/pch_glan.asl</span><br><span>@@ -0,0 +1,29 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2108 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Intel Gigabit Ethernet Controller 0:1f.6 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (GLAN)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001f0006)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_S0W, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRW, Package() {GPE0_PME_B0, 4})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_DSW, 3) {}</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/pch_hda.asl b/src/soc/intel/icelake/acpi/pch_hda.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..6722329</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/pch_hda.asl</span><br><span>@@ -0,0 +1,83 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Audio Controller - Device 31, Function 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (HDAS)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001f0003)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Audio Controller")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Device is D3 wake capable */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_S0W, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NHLT Table Address populated from GNVS values */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (NBUF, ResourceTemplate () {</span><br><span style="color: hsl(120, 100%, 40%);">+ QWordMemory (ResourceConsumer, PosDecode, MinFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+ MaxFixed, NonCacheable, ReadOnly,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Device Specific Method</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0 - UUID</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg1 - Revision</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg2 - Function Index</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_DSM, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (Arg0, ^UUID)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Function 0: Function Support Query</span><br><span style="color: hsl(120, 100%, 40%);">+ * Returns a bitmask of functions supported.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (Arg2, Zero)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * NHLT Query only supported for revision 1 and</span><br><span style="color: hsl(120, 100%, 40%);">+ * if NHLT address and length are set in NVS.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LEqual (Arg1, One),</span><br><span style="color: hsl(120, 100%, 40%);">+ LAnd (LNotEqual (NHLA, Zero),</span><br><span style="color: hsl(120, 100%, 40%);">+ LNotEqual (NHLL, Zero)))) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Buffer (One) { 0x03 })</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Buffer (One) { 0x01 })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Function 1: Query NHLT memory address used by</span><br><span style="color: hsl(120, 100%, 40%);">+ * Intel Offload Engine Driver to discover any non-HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ * devices that are supported by the DSP.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Returns a pointer to NHLT table in memory.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (Arg2, One)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateQWordField (NBUF, ^NHLT._MIN, NBAS)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateQWordField (NBUF, ^NHLT._MAX, NMAS)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateQWordField (NBUF, ^NHLT._LEN, NLEN)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (NHLA, NBAS)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (NHLA, NMAS)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (NHLL, NLEN)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (NBUF)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Buffer (One) { 0x00 })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/pci_irqs.asl b/src/soc/intel/icelake/acpi/pci_irqs.asl</span><br><span>new file mode 100755</span><br><span>index 0000000..d346ce2</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/pci_irqs.asl</span><br><span>@@ -0,0 +1,141 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/irq.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (PICP, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI Bridge */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* cAVS, SMBus, GbE, Nothpeak */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SerialIo and SCS */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI Express Port 9-16 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI Express Port 1-8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* eMMC */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001AFFFF, 0, 0, eMMC_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SerialIo */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SATA controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0017FFFF, 0, 0, SATA_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CSME (HECI, IDE-R, Keyboard and Text redirection */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0016FFFF, 2, 0, IDER_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0016FFFF, 3, 0, KT_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SerialIo */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D20: xHCI, OTG, SRAM, CNVi WiFi */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 0, 0, XHCI_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 1, 0, OTG_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Integrated Sensor Hub */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0013FFFF, 0, 0, ISH_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Thermal */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0012FFFF, 0, 0, THERMAL_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Host Bridge */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Root Port D1F0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA IGFX Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0002FFFF, 0, 0, IGFX_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA Thermal Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA IPU Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0005FFFF, 0, 0, IPU_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA GNA Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0008FFFF, 0, 0, GNA_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (PICN, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D31: cAVS, SMBus, GbE, Nothpeak */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D32: Can't use PIC*/</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D29: PCI Express Port 9-16 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D28: PCI Express Port 1-8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D25: Can't use PIC*/</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D23 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D22: CSME (HECI, IDE-R, KT redirection */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D21: Can't use PIC*/</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D20: xHCI, OTG, SRAM, CNVi WiFi */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D19: Can't use PIC*/</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Thermal */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0012FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P.E.G. Root Port D1F0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA IGFX Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA Thermal Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA IPU Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA GNA Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (^PICP)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (^PICN)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/pcie.asl b/src/soc/intel/icelake/acpi/pcie.asl</span><br><span>new file mode 100755</span><br><span>index 0000000..69e16ca</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/pcie.asl</span><br><span>@@ -0,0 +1,382 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Intel PCH PCIe support */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method (IRQM, 1, Serialized) {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQAA, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, 0, 19 } })</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQAP, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQBA, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, 0, 19 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, 0, 16 } })</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQBP, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQCA, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, 0, 19 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, 0, 17 } })</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQCP, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQDA, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, 0, 19 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, 0, 18 } })</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQDP, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Switch (ToInteger (Arg0))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Case (Package () { 1, 5, 9, 13 }) {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQAA)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQAP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Case (Package () { 2, 6, 10, 14 }) {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQBA)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQBP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Case (Package () { 3, 7, 11, 15 }) {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQCA)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQCP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Case (Package () { 4, 8, 12, 16 }) {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQDA)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQDP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Default {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQDA)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQDP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP01)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP02)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0001)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP03)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0002)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP04)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0003)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP05)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0004)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP06)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0005)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP07)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0006)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP08)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0007)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP09)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP10)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0001)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP11)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0002)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP12)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0003)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP13)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0004)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP14)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0005)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP15)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0006)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP16)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0007)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/platform.asl b/src/soc/intel/icelake/acpi/platform.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..080bf7b</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/platform.asl</span><br><span>@@ -0,0 +1,42 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable ACPI _SWS methods */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/common/acpi/acpi_wake_source.asl></span><br><span style="color: hsl(120, 100%, 40%);">+/* Generic indicator for sleep state */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/common/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* The APM port can be used for generating software SMIs */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+OperationRegion (APMP, SystemIO, 0xb2, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+Field (APMP, ByteAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ APMC, 8, // APM command</span><br><span style="color: hsl(120, 100%, 40%);">+ APMS, 8 // APM status</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The _PIC method is called by the OS to choose between interrupt</span><br><span style="color: hsl(120, 100%, 40%);">+ * routing via the i8259 interrupt controller or the APIC.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * _PIC is called with a parameter of 0 for i8259 configuration and</span><br><span style="color: hsl(120, 100%, 40%);">+ * with a parameter of 1 for Local Apic/IOAPIC configuration.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method (_PIC, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Remember the OS' IRQ routing choice. */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Arg0, PICM)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/scs.asl b/src/soc/intel/icelake/acpi/scs.asl</span><br><span>new file mode 100755</span><br><span>index 0000000..896fd77</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/scs.asl</span><br><span>@@ -0,0 +1,134 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Scope (\_SB.PCI0) {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Clear register 0x1C20/0x4820</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0 - PCR Port ID</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(SCSC, 1, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ ^PCRA (Arg0, 0x1C20, 0x0)</span><br><span style="color: hsl(120, 100%, 40%);">+ ^PCRA (Arg0, 0x4820, 0x0)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* EMMC */</span><br><span style="color: hsl(120, 100%, 40%);">+ Device(PEMC) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_ADR, 0x001A0000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "eMMC Controller")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (TEMP, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion(SCSR, PCI_Config, 0x00, 0x100)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field(SCSR, WordAcc, NoLock, Preserve) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x84), /* PMECTRLSTATUS */</span><br><span style="color: hsl(120, 100%, 40%);">+ PMCR, 16,</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0xA2), /* PG_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ , 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ PGEN, 1, /* PG_ENABLE */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_INI) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear register 0x1C20/0x4820 */</span><br><span style="color: hsl(120, 100%, 40%);">+ ^^SCSC (PID_EMMC)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_PS0, 0, Serialized) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Stall (50) // Sleep 50 us</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, PGEN) // Disable PG</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear register 0x1C20/0x4820 */</span><br><span style="color: hsl(120, 100%, 40%);">+ ^^SCSC (PID_EMMC)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Power State to D0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ And (PMCR, 0xFFFC, PMCR)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PMCR, ^TEMP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_PS3, 0, Serialized) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(1, PGEN) // Enable PG</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Power State to D3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Or (PMCR, 0x0003, PMCR)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PMCR, ^TEMP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (CARD)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00000008)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_RMV, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SD CARD */</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (SDXC)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00140005)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "SD Controller")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (TEMP, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (SDPC, PCI_Config, 0x00, 0x100)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (SDPC, WordAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x84), /* PMECTRLSTATUS */</span><br><span style="color: hsl(120, 100%, 40%);">+ PMCR, 16,</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0xA2), /* PG_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ , 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ PGEN, 1, /* PG_ENABLE */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_INI)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear register 0x1C20/0x4820 */</span><br><span style="color: hsl(120, 100%, 40%);">+ ^^SCSC (PID_SDX)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PS0, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, PGEN) /* Disable PG */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear register 0x1C20/0x4820 */</span><br><span style="color: hsl(120, 100%, 40%);">+ ^^SCSC (PID_SDX)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Power State to D0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ And (PMCR, 0xFFFC, PMCR)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PMCR, ^TEMP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PS3, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (1, PGEN) /* Enable PG */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Power State to D3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Or (PMCR, 0x0003, PMCR)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PMCR, ^TEMP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (CARD)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00000008)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_RMV, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* Device (SDXC) */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/serialio.asl b/src/soc/intel/icelake/acpi/serialio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..3abf383</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/serialio.asl</span><br><span>@@ -0,0 +1,88 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Intel Serial IO Devices */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (I2C0)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00150000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Serial IO I2C Controller 0")</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (I2C1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00150001)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Serial IO I2C Controller 1")</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (I2C2)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00150002)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Serial IO I2C Controller 2")</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (I2C3)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00150003)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Serial IO I2C Controller 3")</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (I2C4)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00190000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Serial IO I2C Controller 4")</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (I2C5)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00190001)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Serial IO I2C Controller 5")</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (SPI0)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001e0002)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Serial IO SPI Controller 0")</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (SPI1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001e0003)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Serial IO SPI Controller 1")</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (SPI2)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00120006)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Serial IO SPI Controller 2")</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (UAR0)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001e0000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Serial IO UART Controller 0")</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (UAR1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001e0001)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Serial IO UART Controller 1")</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (UAR2)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00190002)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "Serial IO UART Controller 2")</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/sleepstates.asl b/src/soc/intel/icelake/acpi/sleepstates.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..13cc358</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/sleepstates.asl</span><br><span>@@ -0,0 +1,20 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 })</span><br><span style="color: hsl(120, 100%, 40%);">+Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 })</span><br><span style="color: hsl(120, 100%, 40%);">+Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 })</span><br><span>diff --git a/src/soc/intel/icelake/acpi/smbus.asl b/src/soc/intel/icelake/acpi/smbus.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..c654fe2</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/smbus.asl</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Intel SMBus Controller 0:1f.4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (SBUS)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001f0004)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl</span><br><span>new file mode 100755</span><br><span>index 0000000..ff323c4</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/southbridge.asl</span><br><span>@@ -0,0 +1,63 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * (Written by Bora Guvendik <bora.guvendik@intel.com> for Intel Corp.)</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/itss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/itss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Interrupt Routing */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "irqlinks.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCI IRQ assignment */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "pci_irqs.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCR access */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/common/acpi/pcr.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* eMMC, SD Card */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "scs.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO controller */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "gpio.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC 0:1f.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "lpc.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH HDA */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "pch_hda.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCIE Ports */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "pcie.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Serial IO */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "serialio.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBus 0:1f.4 */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "smbus.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB XHCI 0:14.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "xhci.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCI _OSC */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/common/acpi/pci_osc.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* CNVi */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "cnvi.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GBe 0:1f.6 */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "pch_glan.asl"</span><br><span>diff --git a/src/soc/intel/icelake/acpi/xhci.asl b/src/soc/intel/icelake/acpi/xhci.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..9c624e4</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/acpi/xhci.asl</span><br><span>@@ -0,0 +1,71 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpe.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* XHCI Controller 0:14.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (XHCI)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00140000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRW, Package () { GPE0_PME_B0, 3 })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_S3D, 3) /* D3 supported in S3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_S0W, 3) /* D3 can wake device in S0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_S3W, 3) /* D3 can wake system from S3 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PS0, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PS3, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Root Hub for Icelake-LP PCH */</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (RHUB)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, Zero)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS01) { Name (_ADR, 1) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS02) { Name (_ADR, 2) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS03) { Name (_ADR, 3) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS04) { Name (_ADR, 4) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS05) { Name (_ADR, 5) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS06) { Name (_ADR, 6) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS07) { Name (_ADR, 7) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS08) { Name (_ADR, 8) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS09) { Name (_ADR, 9) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS10) { Name (_ADR, 10) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS11) { Name (_ADR, 11) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS12) { Name (_ADR, 12) }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USBr */</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (USR1) { Name (_ADR, 11) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (USR2) { Name (_ADR, 12) }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (SS01) { Name (_ADR, 13) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (SS02) { Name (_ADR, 14) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (SS03) { Name (_ADR, 15) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (SS04) { Name (_ADR, 16) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (SS05) { Name (_ADR, 17) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (SS06) { Name (_ADR, 18) }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..40c2d41</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/bootblock/bootblock.c</span><br><span>@@ -0,0 +1,43 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/uart.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Call lib/bootblock.c main */</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_main_with_timestamp(base_timestamp, NULL, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_soc_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_systemagent_early_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_pch_early_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_cpu_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_early_iorange_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_UART_DEBUG))</span><br><span style="color: hsl(120, 100%, 40%);">+ uart_bootblock_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_soc_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ report_platform_info();</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_early_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/bootblock/cpu.c b/src/soc/intel/icelake/bootblock/cpu.c</span><br><span>new file mode 100644</span><br><span>index 0000000..f02b090</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/bootblock/cpu.c</span><br><span>@@ -0,0 +1,26 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/cpulib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/fast_spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_cpu_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Temporarily cache the memory-mapped boot media. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))</span><br><span style="color: hsl(120, 100%, 40%);">+ fast_spi_cache_bios_region();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c</span><br><span>new file mode 100755</span><br><span>index 0000000..7749fcb</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/bootblock/pch.c</span><br><span>@@ -0,0 +1,210 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/fast_spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/p2sb.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pmclib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/smbus.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/lpc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/p2sb.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smbus.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP 0x1400</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 0x0980</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_TO_SHDW_BAR0 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_TO_SHDW_BAR1 0x4</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_TO_SHDW_BAR2 0x8</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_TO_SHDW_BAR3 0xC</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_TO_SHDW_BAR4 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_T0_SHDW_PCIEN 0x1C</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_ACPIBA 0x27B4</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_ACPIBDID 0x27B8</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_PMBASEA 0x27AC</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_PMBASEC 0x27B0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_TCOBASE 0x2778</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCOEN (1 << 1) /* Enable TCO I/O range decode. */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_LPCIOD 0x2770</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_LPCIOE 0x2774</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint32_t get_pmc_reg_base(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pch_series;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_series = get_pch_series();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pch_series == PCH_H)</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H;</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (pch_series == PCH_LP)</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_config_pwrmbase(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Assign Resources to PWRMBASE</span><br><span style="color: hsl(120, 100%, 40%);">+ * Clear BIT 1-2 Command Register</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~(PCI_COMMAND_MEMORY);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program PWRM Base */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable Bus Master and MMIO Space */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= PCI_COMMAND_MEMORY;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable PWRM in PMC */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_pch_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ fast_spi_early_init(SPI_BASE_ADDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+ gspi_early_bar_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb_enable_bar();</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb_configure_hpet();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enabling PWRM Base for accessing</span><br><span style="color: hsl(120, 100%, 40%);">+ * Global Reset Cause Register.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_config_pwrmbase();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_config_acpibase(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pmc_reg_value;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pmc_base_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_base_reg = get_pmc_reg_base();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!pmc_base_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Invalid PMC base address\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg +</span><br><span style="color: hsl(120, 100%, 40%);">+ PCR_PSFX_TO_SHDW_BAR4);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pmc_reg_value != 0xFFFFFFFF)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable Io Space before changing the address */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_rmw32(PID_PSF3, pmc_base_reg +</span><br><span style="color: hsl(120, 100%, 40%);">+ PCR_PSFX_T0_SHDW_PCIEN,</span><br><span style="color: hsl(120, 100%, 40%);">+ ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program ABASE in PSF3 PMC space BAR4*/</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_PSF3, pmc_base_reg +</span><br><span style="color: hsl(120, 100%, 40%);">+ PCR_PSFX_TO_SHDW_BAR4,</span><br><span style="color: hsl(120, 100%, 40%);">+ ACPI_BASE_ADDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable IO Space */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_rmw32(PID_PSF3, pmc_base_reg +</span><br><span style="color: hsl(120, 100%, 40%);">+ PCR_PSFX_T0_SHDW_PCIEN,</span><br><span style="color: hsl(120, 100%, 40%);">+ ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_config_tco(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tcobase;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tcocnt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable TCO in SMBUS Device first before changing Base Address */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~TCO_BASE_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program TCO Base */</span><br><span style="color: hsl(120, 100%, 40%);">+ tcobase = TCO_BASE_ADDRESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_SMBUS, TCOBASE, tcobase);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable TCO in SMBUS */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_BASE_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program TCO timer halt */</span><br><span style="color: hsl(120, 100%, 40%);">+ tcocnt = inw(tcobase + TCO1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ tcocnt |= TCO_TMR_HLT;</span><br><span style="color: hsl(120, 100%, 40%);">+ outw(tcocnt, tcobase + TCO1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_early_iorange_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t dec_rng, dec_en = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IO Decode Range */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ IS_ENABLED(CONFIG_UART_DEBUG)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dec_rng = COMA_RANGE | (COMB_RANGE << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ dec_en = COMA_LPC_EN | COMB_LPC_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, dec_rng);</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write16(PID_DMI, PCR_DMI_LPCIOD, dec_rng);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IO Decode Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program generic IO Decode Range */</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_enable_lpc();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,</span><br><span style="color: hsl(120, 100%, 40%);">+ * GPE0_STS, GPE0_EN registers.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_config_acpibase();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_config_tco();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program SMBUS_BASE_ADDRESS and Enable it */</span><br><span style="color: hsl(120, 100%, 40%);">+ smbus_common_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set up GPE configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_gpe_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_rtc_upper_bank();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c</span><br><span>new file mode 100755</span><br><span>index 0000000..cb71ba3</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/bootblock/report_platform.c</span><br><span>@@ -0,0 +1,205 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/mp_init.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIOS_SIGN_ID 0x8B</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpuid;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *name;</span><br><span style="color: hsl(120, 100%, 40%);">+} cpu_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { CPUID_CANNONLAKE_A0, "Cannonlake A0" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { CPUID_CANNONLAKE_B0, "Cannonlake B0" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { CPUID_CANNONLAKE_C0, "Cannonlake C0" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { CPUID_CANNONLAKE_D0, "Cannonlake D0" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { CPUID_COFFEELAKE_D0, "Coffeelake D0" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0"},</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 mchid;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *name;</span><br><span style="color: hsl(120, 100%, 40%);">+} mch_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)"},</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, "Whiskeylake W (4+2)"},</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)"},</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 lpcid;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *name;</span><br><span style="color: hsl(120, 100%, 40%);">+} pch_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 igdid;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *name;</span><br><span style="color: hsl(120, 100%, 40%);">+} igd_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1, "Cannonlake ULX GT2" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2, "Cannonlake ULX GT1.5" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3, "Cannonlake ULX GT1" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4, "Cannonlake ULX GT0.5" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1, "Cannonlake ULT GT2" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, "Cannonlake ULT GT1.5" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2"},</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1"},</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t get_dev_revision(pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return pci_read_config8(dev, PCI_REVISION_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint16_t get_dev_id(pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return pci_read_config16(dev, PCI_DEVICE_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void report_cpu_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cpuid_result cpuidr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 i, index;</span><br><span style="color: hsl(120, 100%, 40%);">+ char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */</span><br><span style="color: hsl(120, 100%, 40%);">+ int vt, txt, aes;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t microcode_ver;</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const mode[] = {"NOT ", ""};</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *cpu_type = "Unknown";</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 p[13];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ index = 0x80000000;</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuidr = cpuid(index);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cpuidr.eax < 0x80000004) {</span><br><span style="color: hsl(120, 100%, 40%);">+ strcpy(cpu_string, "Platform info not available");</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ int j=0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 2; i <= 4; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuidr = cpuid(index + i);</span><br><span style="color: hsl(120, 100%, 40%);">+ p[j++] = cpuidr.eax;</span><br><span style="color: hsl(120, 100%, 40%);">+ p[j++] = cpuidr.ebx;</span><br><span style="color: hsl(120, 100%, 40%);">+ p[j++] = cpuidr.ecx;</span><br><span style="color: hsl(120, 100%, 40%);">+ p[j++] = cpuidr.edx;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ p[12]=0;</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_name = (char *)p;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Skip leading spaces in CPU name string */</span><br><span style="color: hsl(120, 100%, 40%);">+ while (cpu_name[0] == ' ')</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_name++;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ microcode_ver.lo = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ microcode_ver.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(BIOS_SIGN_ID, microcode_ver);</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuidr = cpuid(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ microcode_ver = rdmsr(BIOS_SIGN_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Look for string to match the name */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cpu_table[i].cpuid == cpuidr.eax) {</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_type = cpu_table[i].name;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuidr.eax, cpu_type, microcode_ver.hi);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ mode[aes], mode[txt], mode[vt]);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void report_mch_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t mchid = get_dev_id(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t mch_revision = get_dev_revision(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *mch_type = "Unknown";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(mch_table); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (mch_table[i].mchid == mchid) {</span><br><span style="color: hsl(120, 100%, 40%);">+ mch_type = mch_table[i].name;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ mchid, mch_revision, mch_type);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void report_pch_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCH_DEV_LPC;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t lpcid = get_dev_id(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *pch_type = "Unknown";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(pch_table); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pch_table[i].lpcid == lpcid) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_type = pch_table[i].name;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ lpcid, get_dev_revision(dev), pch_type);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void report_igd_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = SA_DEV_IGD;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t igdid = get_dev_id(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *igd_type = "Unknown";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(igd_table); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (igd_table[i].igdid == igdid) {</span><br><span style="color: hsl(120, 100%, 40%);">+ igd_type = igd_table[i].name;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ igdid, get_dev_revision(dev), igd_type);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void report_platform_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ report_cpu_info();</span><br><span style="color: hsl(120, 100%, 40%);">+ report_mch_info();</span><br><span style="color: hsl(120, 100%, 40%);">+ report_pch_info();</span><br><span style="color: hsl(120, 100%, 40%);">+ report_igd_info();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/cbmem.c b/src/soc/intel/icelake/cbmem.c</span><br><span>new file mode 100644</span><br><span>index 0000000..bd6dec2</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/cbmem.c</span><br><span>@@ -0,0 +1,22 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void *cbmem_top(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* not implemented yet */</span><br><span style="color: hsl(120, 100%, 40%);">+ return (void *) NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c</span><br><span>new file mode 100755</span><br><span>index 0000000..5bdaec1</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/chip.c</span><br><span>@@ -0,0 +1,150 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/itss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/xdci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <romstage_handoff.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/common/vbt.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/itss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/ramstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span style="color: hsl(120, 100%, 40%);">+const char *soc_acpi_name(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.type == DEVICE_PATH_DOMAIN)</span><br><span style="color: hsl(120, 100%, 40%);">+ return "PCI0";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.type != DEVICE_PATH_PCI)</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (dev->path.pci.devfn) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case SA_DEVFN_ROOT: return "MCHC";</span><br><span style="color: hsl(120, 100%, 40%);">+ case SA_DEVFN_IGD: return "GFX0";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_ISH: return "ISHB";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_XHCI: return "XHCI";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_USBOTG: return "XDCI";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_THERMAL: return "THRM";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_I2C0: return "I2C0";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_I2C1: return "I2C1";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_I2C2: return "I2C2";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_I2C3: return "I2C3";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_CSE: return "CSE1";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_CSE_2: return "CSE2";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_CSE_IDER: return "CSED";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_CSE_KT: return "CSKT";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_CSE_3: return "CSE3";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_SATA: return "SATA";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_UART2: return "UAR2";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_I2C4: return "I2C4";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_I2C5: return "I2C5";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE1: return "RP01";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE2: return "RP02";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE3: return "RP03";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE4: return "RP04";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE5: return "RP05";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE6: return "RP06";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE7: return "RP07";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE8: return "RP08";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE9: return "RP09";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE10: return "RP10";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE11: return "RP11";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE12: return "RP12";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE13: return "RP13";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE14: return "RP14";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE15: return "RP15";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE16: return "RP16";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_UART0: return "UAR0";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_UART1: return "UAR1";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_GSPI0: return "SPI0";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_GSPI1: return "SPI1";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_GSPI2: return "SPI2";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_EMMC: return "EMMC";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_SDCARD: return "SDXC";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_LPC: return "LPCB";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_P2SB: return "P2SB";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PMC: return "PMC_";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_HDA: return "HDAS";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_SMBUS: return "SBUS";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_SPI: return "FSPI";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_GBE: return "IGBE";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_TRACEHUB:return "THUB";</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_init_pre_device(void *chip_info)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Snapshot the current GPIO IRQ polarities. FSP is setting a</span><br><span style="color: hsl(120, 100%, 40%);">+ * default policy that doesn't honor boards' requirements. */</span><br><span style="color: hsl(120, 100%, 40%);">+ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Perform silicon specific init. */</span><br><span style="color: hsl(120, 100%, 40%);">+ fsp_silicon_init(romstage_handoff_is_resume());</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Display FIRMWARE_VERSION_INFO_HOB */</span><br><span style="color: hsl(120, 100%, 40%);">+ fsp_display_fvi_version_hob();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Restore GPIO IRQ polarities back to previous settings. */</span><br><span style="color: hsl(120, 100%, 40%);">+ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_domain_set_resources(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ assign_resources(dev->link_list);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct device_operations pci_domain_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .read_resources = &pci_domain_read_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ .set_resources = &pci_domain_set_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ .scan_bus = &pci_domain_scan_bus,</span><br><span style="color: hsl(120, 100%, 40%);">+ #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_name = &soc_acpi_name,</span><br><span style="color: hsl(120, 100%, 40%);">+ #endif</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct device_operations cpu_bus_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .read_resources = DEVICE_NOOP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .set_resources = DEVICE_NOOP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_resources = DEVICE_NOOP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .init = DEVICE_NOOP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_fill_ssdt_generator = generate_cpu_entries,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the operations if it is a special bus type */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.type == DEVICE_PATH_DOMAIN)</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->ops = &pci_domain_ops;</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->ops = &cpu_bus_ops;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations soc_intel_icelake_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ CHIP_NAME("Intel Icelake")</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = &soc_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+ .init = &soc_init_pre_device,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h</span><br><span>new file mode 100755</span><br><span>index 0000000..bd31946</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/chip.h</span><br><span>@@ -0,0 +1,268 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_CHIP_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_CHIP_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/i2c/designware/dw_i2c.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio_defs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pmc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/serialio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/usb.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct soc_intel_icelake_config {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Common struct containing soc config data required by common code */</span><br><span style="color: hsl(120, 100%, 40%);">+ struct soc_intel_common_config common_soc_config;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Interrupt Routing configuration.</span><br><span style="color: hsl(120, 100%, 40%);">+ * If bit7 is 1, the interrupt is disabled. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pirqa_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pirqb_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pirqc_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pirqd_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pirqe_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pirqf_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pirqg_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pirqh_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPE configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_en_1; /* GPE0_EN_31_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_en_2; /* GPE0_EN_63_32 */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_en_3; /* GPE0_EN_95_64 */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Gpio group routed to each dword of the GPE0 block. Values are</span><br><span style="color: hsl(120, 100%, 40%);">+ * of the form GPP_[A:G] or GPD. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Generic IO decode ranges */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gen1_dec;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gen2_dec;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gen3_dec;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gen4_dec;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable S0iX support */</span><br><span style="color: hsl(120, 100%, 40%);">+ int s0ix_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable DPTF support */</span><br><span style="color: hsl(120, 100%, 40%);">+ int dptf_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Deep SX enable for both AC and DC */</span><br><span style="color: hsl(120, 100%, 40%);">+ int deep_s3_enable_ac;</span><br><span style="color: hsl(120, 100%, 40%);">+ int deep_s3_enable_dc;</span><br><span style="color: hsl(120, 100%, 40%);">+ int deep_s5_enable_ac;</span><br><span style="color: hsl(120, 100%, 40%);">+ int deep_s5_enable_dc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Deep Sx Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ * DSX_EN_WAKE_PIN - Enable WAKE# pin</span><br><span style="color: hsl(120, 100%, 40%);">+ * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin</span><br><span style="color: hsl(120, 100%, 40%);">+ * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t deep_sx_config;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TCC activation offset */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t tcc_offset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t PlatformMemorySize;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SmramMask;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t MrcFastBoot;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t TsegSize;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t MmioSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DDR Frequency Limit. Maximum Memory Frequency Selections in Mhz.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t DdrFreqLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SAGV Low Frequency Selections in Mhz.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t FreqSaGvLow;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SAGV Mid Frequency Selections in Mhz.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t FreqSaGvMid;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.</span><br><span style="color: hsl(120, 100%, 40%);">+ * When enabled memory will be training at two different frequencies.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled */</span><br><span style="color: hsl(120, 100%, 40%);">+ enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SaGv_Disabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ SaGv_FixedLow,</span><br><span style="color: hsl(120, 100%, 40%);">+ SaGv_FixedMid,</span><br><span style="color: hsl(120, 100%, 40%);">+ SaGv_FixedHigh,</span><br><span style="color: hsl(120, 100%, 40%);">+ SaGv_Enabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ } SaGv;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rank Margin Tool. 1:Enable, 0:Disable */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t RMT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB related */</span><br><span style="color: hsl(120, 100%, 40%);">+ struct usb2_port_config usb2_ports[16];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct usb3_port_config usb3_ports[10];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SsicPortEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Wake Enable Bitmap for USB2 ports */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t usb2_wake_enable_bitmap;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Wake Enable Bitmap for USB3 ports */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t usb3_wake_enable_bitmap;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SATA related */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SataMode;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SataSalpSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SataPortsEnable[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SataPortsDevSlp[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Audio related */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PchHdaEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PchHdaDspEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PchHdaAudioLinkHda;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PchHdaAudioLinkDmic0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PchHdaAudioLinkDmic1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PchHdaAudioLinkSsp0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PchHdaAudioLinkSsp1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PchHdaAudioLinkSsp2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PchHdaAudioLinkSndw1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PchHdaAudioLinkSndw2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PchHdaAudioLinkSndw3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PchHdaAudioLinkSndw4;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCIe Root Ports */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCIe output clocks type to Pcie devices.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0xFF: not used */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to</span><br><span style="color: hsl(120, 100%, 40%);">+ * clksrc. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SMBus */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SmbusEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* eMMC and SD */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t ScsEmmcHs400Enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Need to update DLL setting to get Emmc running at HS400 speed */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t EmmcHs400DllNeed;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 0-39: number of active delay for RX strobe, unit is 125 psec */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t EmmcHs400RxStrobeDll1;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 0-78: number of active delay for TX data, unit is 125 psec */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t EmmcHs400TxDataDll;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Integrated Sensor */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PchIshEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Heci related */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t Heci3Enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Gfx related */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t IgdDvmt50PreAlloc;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t InternalGfx;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SkipExtGfxScan;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t GraphicsConfigPtr;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t Device4Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO IRQ Select. The valid value is 14 or 15 */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t GpioIrqRoute;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SCI IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SciIrqSelect;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t TcoIrqSelect;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t TcoIrqEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* HeciEnabled decides the state of Heci1 at end of boot</span><br><span style="color: hsl(120, 100%, 40%);">+ * Setting to 0 (default) disables Heci1 and hides the device from OS */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t HeciEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PL2 Override value in Watts */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t tdp_pl2_override;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Intel Speed Shift Technology */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t speed_shift_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable VR specific mailbox command</span><br><span style="color: hsl(120, 100%, 40%);">+ * 00b - no VR specific cmd sent</span><br><span style="color: hsl(120, 100%, 40%);">+ * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent</span><br><span style="color: hsl(120, 100%, 40%);">+ * 10b - VR specific cmd sent for PS4 exit issue</span><br><span style="color: hsl(120, 100%, 40%);">+ * 11b - Reserved */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SendVrMbxCmd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t eist_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Statically clock gate 8254 PIT. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t clock_gate_8254;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable C6 DRAM */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t enable_c6dram;</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PRMRR size setting with below options</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x00100000 - 1MiB</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x02000000 - 32MiB and beyond</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t PrmrrSize;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PmTimerDisabled;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Desired platform debug type. */</span><br><span style="color: hsl(120, 100%, 40%);">+ enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DebugConsent_Disabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ DebugConsent_DCI_DBC,</span><br><span style="color: hsl(120, 100%, 40%);">+ DebugConsent_DCI,</span><br><span style="color: hsl(120, 100%, 40%);">+ DebugConsent_USB3_DBC,</span><br><span style="color: hsl(120, 100%, 40%);">+ DebugConsent_XDP, /* XDP/Mipi60 */</span><br><span style="color: hsl(120, 100%, 40%);">+ DebugConsent_USB2_DBC,</span><br><span style="color: hsl(120, 100%, 40%);">+ } DebugConsent;</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SerialIO device mode selection:</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Device index:</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoIndexI2C0</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoIndexI2C1</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoIndexI2C2</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoIndexI2C3</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoIndexI2C4</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoIndexI2C5</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoIndexSPI0</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoIndexSPI1</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoIndexSPI2</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoIndexUART0</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoIndexUART1</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoIndexUART2</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Mode select:</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoDisabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoPci</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoAcpi</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoHidden</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SerialIoDevMode[PchSerialIoIndexMAX];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO SD card detect pin */</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int sdcard_cd_gpio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable Pch iSCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pch_isclk;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Intel VT configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t VtdDisable;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t VmxEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct soc_intel_icelake_config config_t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c</span><br><span>new file mode 100644</span><br><span>index 0000000..bfe9f7be</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/cpu.c</span><br><span>@@ -0,0 +1,243 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/lapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/turbo.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/cpulib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/mp_init.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <romstage_handoff.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_fsp_load(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ fsps_load(romstage_handoff_is_resume());</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void configure_isst(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ config_t *conf = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (conf->speed_shift_enable) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP</span><br><span style="color: hsl(120, 100%, 40%);">+ * is supported or not. coreboot needs to configure MSR 0x1AA</span><br><span style="color: hsl(120, 100%, 40%);">+ * which is then reflected in the CPUID register.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_MISC_PWR_MGMT);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_MISC_PWR_MGMT, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_MISC_PWR_MGMT);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_MISC_PWR_MGMT, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void configure_misc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ config_t *conf = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo |= (1 << 0); /* Fast String enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (conf->eist_enable)</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_enable_eist();</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_disable_eist();</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable Thermal interrupts */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_THERM_INTERRUPT, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable package critical interrupt only */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo = 1 << 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable PROCHOT */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_POWER_CTL);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo |= (1 << 23); /* Lock it */</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_POWER_CTL, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_lapic_tpr(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_PIC_MSG_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PIC_MSG_CONTROL, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void configure_dca_cap(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cpuid_result cpuid_regs;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuid_regs = cpuid(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cpuid_regs.ecx & (1 << 18)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_PLATFORM_DCA_CAP);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo |= 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PLATFORM_DCA_CAP, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_energy_perf_bias(u8 policy)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ int ecx;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Determine if energy efficient policy is supported. */</span><br><span style="color: hsl(120, 100%, 40%);">+ ecx = cpuid_ecx(0x6);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(ecx & (1 << 3)))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo &= ~0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo |= policy & 0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void configure_c_states(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C-state Interrupt Response Latency Control 3 - package C8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo = IRTL_VALID | IRTL_32768_NS |</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_LATENCY_CONTROL_3_LIMIT;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C-state Interrupt Response Latency Control 4 - package C9 */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo = IRTL_VALID | IRTL_32768_NS |</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_LATENCY_CONTROL_4_LIMIT;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C-state Interrupt Response Latency Control 5 - package C10 */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo = IRTL_VALID | IRTL_32768_NS |</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_LATENCY_CONTROL_5_LIMIT;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* All CPUs including BSP will run the following function. */</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_core_init(struct device *cpu)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear out pending MCEs */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO(adurbin): This should only be done on a cold boot. Also, some</span><br><span style="color: hsl(120, 100%, 40%);">+ * of these banks are core vs package scope. For now every CPU clears</span><br><span style="color: hsl(120, 100%, 40%);">+ * every bank. */</span><br><span style="color: hsl(120, 100%, 40%);">+ mca_configure(NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable the local CPU apics */</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_lapic_tpr();</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_lapic();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Configure c-state interrupt response time */</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_c_states();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Configure Enhanced SpeedStep and Thermal Sensors */</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_misc();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Configure Intel Speed Shift */</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_isst();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable Direct Cache Access */</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_dca_cap();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set energy policy */</span><br><span style="color: hsl(120, 100%, 40%);">+ set_energy_perf_bias(ENERGY_POLICY_NORMAL);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable Turbo */</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_turbo();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void per_cpu_smm_trigger(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Relocate the SMM handler. */</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_relocate();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void post_mp_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Max Ratio */</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_set_max_ratio();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Now that all APs have been relocated as well as the BSP let SMIs</span><br><span style="color: hsl(120, 100%, 40%);">+ * start flowing.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_southbridge_enable(PWRBTN_EN | GBL_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Lock down the SMRAM space. */</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_lock();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct mp_ops mp_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,</span><br><span style="color: hsl(120, 100%, 40%);">+ * that are set prior to ramstage.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Real MTRRs programming are being done after resource allocation.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_mp_init = soc_fsp_load,</span><br><span style="color: hsl(120, 100%, 40%);">+ .get_cpu_count = get_cpu_count,</span><br><span style="color: hsl(120, 100%, 40%);">+ .get_smm_info = smm_info,</span><br><span style="color: hsl(120, 100%, 40%);">+ .get_microcode_info = get_microcode_info,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_mp_smm_init = smm_initialize,</span><br><span style="color: hsl(120, 100%, 40%);">+ .per_cpu_smm_trigger = per_cpu_smm_trigger,</span><br><span style="color: hsl(120, 100%, 40%);">+ .relocation_handler = smm_relocation_handler,</span><br><span style="color: hsl(120, 100%, 40%);">+ .post_mp_init = post_mp_init,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_init_cpus(struct bus *cpu_bus)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (mp_init_with_smm(cpu_bus, &mp_ops))</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "MP initialization failure.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c</span><br><span>new file mode 100755</span><br><span>index 0000000..fb78350</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/finalize.c</span><br><span>@@ -0,0 +1,107 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootstate.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/post_codes.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <reg_script.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <spi-generic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/p2sb.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smbus.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CAM_CLK_EN (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MIPI_CLK (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDPLL_CLK (0 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_enable_isclk(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_handle_sideband(config_t *config)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->pch_isclk)</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_enable_isclk();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_finalize(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tcobase, tcocnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *pmcbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ config_t *config;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TCO Lock down */</span><br><span style="color: hsl(120, 100%, 40%);">+ tcobase = smbus_tco_regs();</span><br><span style="color: hsl(120, 100%, 40%);">+ tcocnt = inw(tcobase + TCO1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ tcocnt |= TCO_LOCK;</span><br><span style="color: hsl(120, 100%, 40%);">+ outw(tcocnt, tcobase + TCO1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Disable ACPI PM timer based on dt policy</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Disabling ACPI PM timer also switches off TCO</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = PCH_DEV_PMC;</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ pmcbase = pmc_mmio_regs();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->PmTimerDisabled) {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 |= (1 << 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable XTAL shutdown qualification for low power idle. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->s0ix_enable) {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = read32(pmcbase + CPPMVRIC);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= XTALSDQDIS;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pmcbase + CPPMVRIC, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_handle_sideband(config);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_finalize(void *unused)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Finalizing chipset.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_finalize();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Finalizing SMM.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(APM_CNT_FINALIZE, APM_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Indicate finalize step with post code */</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(POST_OS_BOOT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);</span><br><span>diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c</span><br><span>new file mode 100644</span><br><span>index 0000000..513ef00</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/fsp_params.c</span><br><span>@@ -0,0 +1,30 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/ramstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* UPD parameters to be initialized before SiliconInit */</span><br><span style="color: hsl(120, 100%, 40%);">+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ToDo: update with UPD override as FSP matures */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Mainboard GPIO Configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/gpio.c b/src/soc/intel/icelake/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..e965494</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/gpio.c</span><br><span>@@ -0,0 +1,170 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pmc.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct reset_mapping rst_map[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct reset_mapping rst_map_com0[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_group icl_community0_groups[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_A0, GPP_A0, GPIO_RSVD_0), /* GPP_A */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_A0, GPP_B0, GPIO_RSVD_2), /* GPP_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_A0, GPP_G0, GPP_G7), /* GPP_G */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_A0, GPIO_RSVD_3, GPIO_RSVD_11), /* SPI */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_group icl_community1_groups[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_D0, GPP_D0, GPIO_RSVD_12), /* GPP_D */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_D0, GPP_F0, GPP_F23), /* GPP_F */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_D0, GPP_H0, GPP_H23), /* GPP_H */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_D0, GPIO_RSVD_12, GPIO_RSVD_52), /* VGPIO */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_group icl_community2_groups[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_group icl_community3_groups[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD), /* AZA */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(HDA_BCLK, GPIO_RSVD_68, GPIO_RSVD_78), /* CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_group icl_community4_groups[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP_E */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPIO_RSVD_53, GPIO_RSVD_61), /* JTAG */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPIO_RSVD_62, GPIO_RSVD_67), /* HVMOS */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_community icl_communities[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { /* GPP A, B, G, SPI */</span><br><span style="color: hsl(120, 100%, 40%);">+ .port = PID_GPIOCOM0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPP_A0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPIO_RSVD_11,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pad_cfg_base = PAD_CFG_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_ABG",</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset_map = rst_map_com0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_reset_vals = ARRAY_SIZE(rst_map_com0),</span><br><span style="color: hsl(120, 100%, 40%);">+ .groups = icl_community0_groups,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_groups = ARRAY_SIZE(icl_community0_groups),</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* GPP D, F, H, VGPIO */</span><br><span style="color: hsl(120, 100%, 40%);">+ .port = PID_GPIOCOM1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPP_D0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPIO_RSVD_52,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pad_cfg_base = PAD_CFG_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_DFH",</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset_map = rst_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span style="color: hsl(120, 100%, 40%);">+ .groups = icl_community1_groups,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_groups = ARRAY_SIZE(icl_community1_groups),</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* GPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ .port = PID_GPIOCOM2,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPD0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPD11,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pad_cfg_base = PAD_CFG_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPD",</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset_map = rst_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span style="color: hsl(120, 100%, 40%);">+ .groups = icl_community2_groups,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_groups = ARRAY_SIZE(icl_community2_groups),</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* AZA, CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+ .port = PID_GPIOCOM3,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = HDA_BCLK,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPIO_RSVD_78,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pad_cfg_base = PAD_CFG_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GP_AC",</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset_map = rst_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span style="color: hsl(120, 100%, 40%);">+ .groups = icl_community3_groups,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_groups = ARRAY_SIZE(icl_community3_groups),</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* GPP C, E, JTAG, HVMOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ .port = PID_GPIOCOM4,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPP_C0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPIO_RSVD_67,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pad_cfg_base = PAD_CFG_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_CEJ",</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset_map = rst_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span style="color: hsl(120, 100%, 40%);">+ .groups = icl_community4_groups,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_groups = ARRAY_SIZE(icl_community4_groups),</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_community *soc_gpio_get_community(size_t *num_communities)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num_communities = ARRAY_SIZE(icl_communities);</span><br><span style="color: hsl(120, 100%, 40%);">+ return icl_communities;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static const struct pmc_to_gpio_route routes[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_A, GPP_A },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_B, GPP_B },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_C, GPP_C },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_D, GPP_D },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_E, GPP_E },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_F, GPP_F },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_G, GPP_G },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_H, GPP_H },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPD, GPD },</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(routes);</span><br><span style="color: hsl(120, 100%, 40%);">+ return routes;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c</span><br><span>new file mode 100644</span><br><span>index 0000000..1c22f49</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/graphics.c</span><br><span>@@ -0,0 +1,82 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpigen.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/intel/gma/i915_reg.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/intel/gma/opregion.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/graphics.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t fsp_soc_get_igd_bar(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return graphics_get_memory_base();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void graphics_soc_init(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ddi_buf_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.</span><br><span style="color: hsl(120, 100%, 40%);">+ * This will allow the kernel to use 4-lane eDP links properly</span><br><span style="color: hsl(120, 100%, 40%);">+ * if the VBIOS or GOP driver do not execute.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED |</span><br><span style="color: hsl(120, 100%, 40%);">+ DDI_BUF_IS_IDLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * GFX PEIM module inside FSP binary is taking care of graphics</span><br><span style="color: hsl(120, 100%, 40%);">+ * initialization based on INTEL_GMA_ADD_VBT Kconfig</span><br><span style="color: hsl(120, 100%, 40%);">+ * option and input VBT file. Hence no need to load/execute legacy VGA</span><br><span style="color: hsl(120, 100%, 40%);">+ * OpROM in order to initialize GFX.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * In case of non-FSP solution, SoC need to select VGA_ROM_RUN</span><br><span style="color: hsl(120, 100%, 40%);">+ * Kconfig to perform GFX initialization through VGA OpRom.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IGD needs to Bus Master */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize PCI device, load/execute BIOS Option ROM */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_dev_init(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t graphics_soc_write_acpi_opregion(struct device *device,</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t current, struct acpi_rsdp *rsdp)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ igd_opregion_t *opregion;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ opregion = (igd_opregion_t *)current;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ current += sizeof(igd_opregion_t);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_align_current(current);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/gspi.c b/src/soc/intel/icelake/gspi.c</span><br><span>new file mode 100644</span><br><span>index 0000000..cd5dc8e</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/gspi.c</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int gspi_soc_bus_to_devfn(unsigned int gspi_bus)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (gspi_bus) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0:</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_DEVFN_GSPI0;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1:</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_DEVFN_GSPI1;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2:</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_DEVFN_GSPI2;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/i2c.c b/src/soc/intel/icelake/i2c.c</span><br><span>new file mode 100644</span><br><span>index 0000000..2820a85</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/i2c.c</span><br><span>@@ -0,0 +1,56 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/i2c/designware/dw_i2c.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int dw_i2c_soc_devfn_to_bus(unsigned int devfn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (devfn) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_I2C0:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_I2C1:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_I2C2:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_I2C3:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_I2C4:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_I2C5:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 5;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int dw_i2c_soc_bus_to_devfn(unsigned int bus)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (bus) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0:</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_DEVFN_I2C0;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1:</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_DEVFN_I2C1;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2:</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_DEVFN_I2C2;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 3:</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_DEVFN_I2C3;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 4:</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_DEVFN_I2C4;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 5:</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_DEVFN_I2C5;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/bootblock.h b/src/soc/intel/icelake/include/soc/bootblock.h</span><br><span>new file mode 100644</span><br><span>index 0000000..2f6473d</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/bootblock.h</span><br><span>@@ -0,0 +1,30 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ICELAKE_BOOTBLOCK_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ICELAKE_BOOTBLOCK_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bootblock pre console init programming */</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_cpu_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_pch_early_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bootblock post console init programming */</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_early_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_early_iorange_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void report_platform_info(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h</span><br><span>new file mode 100644</span><br><span>index 0000000..856d685</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/cpu.h</span><br><span>@@ -0,0 +1,48 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ICELAKE_CPU_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ICELAKE_CPU_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Latency times in units of 32768ns */</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Power in units of mW */</span><br><span style="color: hsl(120, 100%, 40%);">+#define C1_POWER 0x3e8</span><br><span style="color: hsl(120, 100%, 40%);">+#define C6_POWER 0x15e</span><br><span style="color: hsl(120, 100%, 40%);">+#define C7_POWER 0xc8</span><br><span style="color: hsl(120, 100%, 40%);">+#define C8_POWER 0xc8</span><br><span style="color: hsl(120, 100%, 40%);">+#define C9_POWER 0xc8</span><br><span style="color: hsl(120, 100%, 40%);">+#define C10_POWER 0xc8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \</span><br><span style="color: hsl(120, 100%, 40%);">+ (((1 << ((base)*5)) * (limit)) / 1000)</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_FROM_LAT_REG(reg) \</span><br><span style="color: hsl(120, 100%, 40%);">+ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \</span><br><span style="color: hsl(120, 100%, 40%);">+ (IRTL_1024_NS >> 10))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Configure power limits for turbo mode */</span><br><span style="color: hsl(120, 100%, 40%);">+void set_power_limits(u8 power_limit_1_time);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/ebda.h b/src/soc/intel/icelake/include/soc/ebda.h</span><br><span>new file mode 100644</span><br><span>index 0000000..9c44a50</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/ebda.h</span><br><span>@@ -0,0 +1,25 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_EBDA_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_EBDA_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct ebda_config {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t signature; /* 0x00 - EBDA signature */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t tolum_base; /* 0x04 - coreboot memory start */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved_mem_size; /* 0x08 - chipset reserved memory size */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/gpe.h b/src/soc/intel/icelake/include/soc/gpe.h</span><br><span>new file mode 100644</span><br><span>index 0000000..d946e2a</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/gpe.h</span><br><span>@@ -0,0 +1,134 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_GPE_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_GPE_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPE_31_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_00 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_01 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_02 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_03 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_04 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_05 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_06 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_07 7</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_08 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_09 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_10 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_11 11</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_12 12</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_13 13</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_14 14</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_15 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_16 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_17 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_18 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_19 19</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_20 20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_21 21</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_22 22</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_23 23</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_24 24</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_25 25</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_26 26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_27 27</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_28 28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_29 29</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_30 30</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW0_31 31</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPE_63_32 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_00 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_01 33</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_02 34</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_03 36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_04 36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_05 37</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_06 38</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_07 39</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_08 40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_09 41</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_10 42</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_11 43</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_12 44</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_13 45</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_14 46</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_15 47</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_16 48</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_17 49</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_18 50</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_19 51</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_20 52</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_21 53</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_22 54</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_23 55</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_24 56</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_25 57</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_26 58</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_27 59</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_28 60</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_29 61</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_30 62</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW1_31 63</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPE_95_64 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_00 64</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_01 65</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_02 66</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_03 67</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_04 68</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_05 69</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_06 70</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_07 71</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_08 72</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_09 73</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_10 74</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_11 75</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_12 76</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_13 77</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_14 78</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_15 79</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_16 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_17 81</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_18 82</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_19 83</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_20 84</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_21 85</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_22 86</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_23 87</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_24 88</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_25 89</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_26 90</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_27 91</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_28 92</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_29 93</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_30 94</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW2_31 95</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPE_STD */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_HOT_PLUG 97</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_SWGPE 98</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_TCOSCI 102</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_SMB_WAK 103</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_PCI_EXP 105</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_BATLOW 106</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_PME 107</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_ME_SCI 108</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_PME_B0 109</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_ESPI 110</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_GPIO_T2 111</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_LAN_WAK 112</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_WADT 114</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_MAX GPE0_WADT</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _SOC_GPE_H_ */</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/gpio.h b/src/soc/intel/icelake/include/soc/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..2e55e74</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/gpio.h</span><br><span>@@ -0,0 +1,24 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ICELAKE_GPIO_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ICELAKE_GPIO_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio_defs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define CROS_GPIO_DEVICE_NAME "INT34BB:00"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h</span><br><span>new file mode 100644</span><br><span>index 0000000..44425f4</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/gpio_defs.h</span><br><span>@@ -0,0 +1,255 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ICELAKE_GPIO_DEFS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ICELAKE_GPIO_DEFS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stddef.h></span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio_soc_defs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COMx_GPI_REGS(n) \</span><br><span style="color: hsl(120, 100%, 40%);">+ (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPI_STATUS_REGS \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((NUM_GPIO_COM0_GPI_REGS) +\</span><br><span style="color: hsl(120, 100%, 40%);">+ (NUM_GPIO_COM1_GPI_REGS) +\</span><br><span style="color: hsl(120, 100%, 40%);">+ (NUM_GPIO_COM2_GPI_REGS) +\</span><br><span style="color: hsl(120, 100%, 40%);">+ (NUM_GPIO_COM3_GPI_REGS) +\</span><br><span style="color: hsl(120, 100%, 40%);">+ (NUM_GPIO_COM4_GPI_REGS))</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * IOxAPIC IRQs for the GPIOs</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group A */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A0_IRQ 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A1_IRQ 0x19</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A2_IRQ 0x1a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A3_IRQ 0x1b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A4_IRQ 0x1c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A5_IRQ 0x1d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A6_IRQ 0x1e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A7_IRQ 0x1f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A8_IRQ 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A9_IRQ 0x21</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A10_IRQ 0x22</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A11_IRQ 0x23</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A12_IRQ 0x24</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A13_IRQ 0x25</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A14_IRQ 0x26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A15_IRQ 0x27</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A16_IRQ 0x28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A17_IRQ 0x29</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A18_IRQ 0x2a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A19_IRQ 0x2b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A20_IRQ 0x2c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A21_IRQ 0x2d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A22_IRQ 0x2e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A23_IRQ 0x2f</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group B */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B0_IRQ 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B1_IRQ 0x31</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B2_IRQ 0x32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B3_IRQ 0x33</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B4_IRQ 0x34</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B5_IRQ 0x35</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B6_IRQ 0x36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B7_IRQ 0x37</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B8_IRQ 0x38</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B9_IRQ 0x39</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B10_IRQ 0x3a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B11_IRQ 0x3b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B12_IRQ 0x3c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B13_IRQ 0x3d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B14_IRQ 0x3e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B15_IRQ 0x3f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B16_IRQ 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B17_IRQ 0x41</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B18_IRQ 0x42</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B19_IRQ 0x43</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B20_IRQ 0x44</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B21_IRQ 0x45</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B22_IRQ 0x46</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B23_IRQ 0x47</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group C */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C0_IRQ 0x48</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C1_IRQ 0x49</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C2_IRQ 0x4a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C3_IRQ 0x4b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C4_IRQ 0x4c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C5_IRQ 0x4d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C6_IRQ 0x4e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C7_IRQ 0x4f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C8_IRQ 0x50</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C9_IRQ 0x51</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C10_IRQ 0x52</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C11_IRQ 0x53</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C12_IRQ 0x54</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C13_IRQ 0x55</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C14_IRQ 0x56</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C15_IRQ 0x57</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C16_IRQ 0x58</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C17_IRQ 0x59</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C18_IRQ 0x5a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C19_IRQ 0x5b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C20_IRQ 0x5c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C21_IRQ 0x5d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C22_IRQ 0x5e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C23_IRQ 0x5f</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group D */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D0_IRQ 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D1_IRQ 0x61</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D2_IRQ 0x62</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D3_IRQ 0x63</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D4_IRQ 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D5_IRQ 0x65</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D6_IRQ 0x66</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D7_IRQ 0x67</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D8_IRQ 0x68</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D9_IRQ 0x69</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D10_IRQ 0x6a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D11_IRQ 0x6b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D12_IRQ 0x6c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D13_IRQ 0x6d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D14_IRQ 0x6e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D15_IRQ 0x6f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D16_IRQ 0x70</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D17_IRQ 0x71</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D18_IRQ 0x72</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D19_IRQ 0x73</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D20_IRQ 0x74</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D21_IRQ 0x75</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D22_IRQ 0x76</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D23_IRQ 0x77</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group E */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E0_IRQ 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E1_IRQ 0x19</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E2_IRQ 0x1a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E3_IRQ 0x1b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E4_IRQ 0x1c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E5_IRQ 0x1d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E6_IRQ 0x1e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E7_IRQ 0x1f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E8_IRQ 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E9_IRQ 0x21</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E10_IRQ 0x22</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E11_IRQ 0x23</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E12_IRQ 0x24</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E13_IRQ 0x25</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E14_IRQ 0x26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E15_IRQ 0x27</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E16_IRQ 0x28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E17_IRQ 0x29</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E18_IRQ 0x2a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E19_IRQ 0x2b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E20_IRQ 0x2c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E21_IRQ 0x2d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E22_IRQ 0x2e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E23_IRQ 0x2f</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group F */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F0_IRQ 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F1_IRQ 0x31</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F2_IRQ 0x32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F3_IRQ 0x33</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F4_IRQ 0x34</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F5_IRQ 0x35</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F6_IRQ 0x36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F7_IRQ 0x37</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F8_IRQ 0x38</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F9_IRQ 0x39</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F10_IRQ 0x3a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F11_IRQ 0x3b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F12_IRQ 0x3c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F13_IRQ 0x3d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F14_IRQ 0x3e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F15_IRQ 0x3f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F16_IRQ 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F17_IRQ 0x41</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F18_IRQ 0x42</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F19_IRQ 0x43</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F20_IRQ 0x44</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F21_IRQ 0x45</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F22_IRQ 0x46</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F23_IRQ 0x47</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group G */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G0_IRQ 0x6c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G1_IRQ 0x6d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G2_IRQ 0x6e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G3_IRQ 0x6f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G4_IRQ 0x70</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G5_IRQ 0x71</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G6_IRQ 0x72</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G7_IRQ 0x73</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group GPD */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD0_IRQ 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD1_IRQ 0x61</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD2_IRQ 0x62</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD3_IRQ 0x63</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD4_IRQ 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD5_IRQ 0x65</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD6_IRQ 0x66</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD7_IRQ 0x67</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD8_IRQ 0x68</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD9_IRQ 0x69</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD10_IRQ 0x6a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD11_IRQ 0x6b</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group H */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H0_IRQ 0x48</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H1_IRQ 0x49</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H2_IRQ 0x4a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H3_IRQ 0x4b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H4_IRQ 0x4c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H5_IRQ 0x4d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H6_IRQ 0x4e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H7_IRQ 0x4f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H8_IRQ 0x50</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H9_IRQ 0x51</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H10_IRQ 0x52</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H11_IRQ 0x53</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H12_IRQ 0x54</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H13_IRQ 0x55</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H14_IRQ 0x56</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H15_IRQ 0x57</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H16_IRQ 0x58</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H17_IRQ 0x59</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H18_IRQ 0x5a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H19_IRQ 0x5b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H20_IRQ 0x5c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H21_IRQ 0x5d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H22_IRQ 0x5e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H23_IRQ 0x5f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Register defines. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MISCCFG 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_DW_SHIFT 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_DW_MASK 0xfff00</span><br><span style="color: hsl(120, 100%, 40%);">+#define HOSTSW_OWN_REG_0 0xb0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPI_SMI_STS_0 0x180</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPI_SMI_EN_0 0x1A0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PAD_CFG_BASE 0x600</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIORXSTATE_MASK 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIORXSTATE_SHIFT 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h</span><br><span>new file mode 100644</span><br><span>index 0000000..34216bc</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h</span><br><span>@@ -0,0 +1,354 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ICELAKE_GPIO_SOC_DEFS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ICELAKE_GPIO_SOC_DEFS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Most of the fixed numbers and macros are based on the GPP groups.</span><br><span style="color: hsl(120, 100%, 40%);">+ * The GPIO groups are accessed through register blocks called</span><br><span style="color: hsl(120, 100%, 40%);">+ * communities.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GROUP_SPI 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define GROUP_VGPIO 7</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define GROUP_AZA 0xA</span><br><span style="color: hsl(120, 100%, 40%);">+#define GROUP_CPU 0xB</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C 0xC</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E 0xD</span><br><span style="color: hsl(120, 100%, 40%);">+#define GROUP_JTAG 0xE</span><br><span style="color: hsl(120, 100%, 40%);">+#define GROUP_HVMOS 0xF</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_NUM_GROUPS 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MAX_NUM_PER_GROUP 24</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * GPIOs are ordered monotonically increasing to match ACPI/OS driver.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group A */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A0 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A1 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A2 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A3 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A4 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A5 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A6 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A7 7</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A8 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A9 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A10 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A11 11</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A12 12</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A13 13</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A14 14</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A15 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A16 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A17 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A18 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A19 19</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A20 20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A21 21</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A22 22</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A23 23</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_0 24</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group B */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B0 25</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B1 26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B2 27</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B3 28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B4 29</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B5 30</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B6 31</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B7 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B8 33</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B9 34</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B10 35</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B11 36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B12 37</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B13 38</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B14 39</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B15 40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B16 41</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B17 42</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B18 43</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B19 44</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B20 45</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B21 46</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B22 47</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B23 48</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_1 49</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_2 50</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group G */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G0 51</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G1 52</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G2 53</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G3 54</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G4 55</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G5 56</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G6 57</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G7 58</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group SPI */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_3 59</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_4 60</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_5 61</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_6 62</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_7 63</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_8 64</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_9 65</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_10 66</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_11 67</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM0_PADS (GPIO_RSVD_11 - GPP_A0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group D */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D0 68</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D1 69</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D2 70</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D3 71</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D4 72</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D5 73</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D6 74</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D7 75</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D8 76</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D9 77</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D10 78</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D11 79</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D12 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D13 81</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D14 82</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D15 83</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D16 84</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D17 85</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D18 86</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D19 87</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D20 88</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D21 89</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D22 90</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D23 91</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_12 92</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group F */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F0 93</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F1 94</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F2 95</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F3 96</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F4 97</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F5 98</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F6 99</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F7 100</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F8 101</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F9 102</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F10 103</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F11 104</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F12 105</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F13 106</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F14 107</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F15 108</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F16 109</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F17 110</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F18 111</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F19 112</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F20 113</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F21 114</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F22 115</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F23 116</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group H */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H0 117</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H1 118</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H2 119</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H3 120</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H4 121</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H5 122</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H6 123</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H7 124</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H8 125</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H9 126</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H10 127</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H11 128</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H12 129</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H13 130</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H14 131</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H15 132</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H16 133</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H17 134</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H18 135</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H19 136</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H20 137</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H21 138</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H22 139</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H23 140</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group VGOIO */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_13 141</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_14 142</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_15 143</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_16 144</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_17 145</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_18 146</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_19 147</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_20 148</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_21 149</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_22 150</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_23 151</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_24 152</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_25 153</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_26 154</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_27 155</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_28 156</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_29 157</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_30 158</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_31 159</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_32 160</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_33 161</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_34 162</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_35 163</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_36 164</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_37 165</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_38 166</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_39 167</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_40 168</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_41 169</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_42 170</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_43 171</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_44 172</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_45 173</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_46 174</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_47 175</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_48 176</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_49 177</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_50 178</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_51 179</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_52 180</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM1_PADS (GPIO_RSVD_52 - GPP_D0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group C */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C0 181</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C1 182</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C2 183</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C3 184</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C4 185</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C5 186</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C6 187</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C7 188</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C8 189</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C9 190</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C10 191</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C11 192</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C12 193</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C13 194</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C14 195</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C15 196</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C16 197</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C17 198</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C18 199</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C19 200</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C20 201</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C21 202</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C22 203</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C23 204</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group E */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E0 205</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E1 206</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E2 207</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E3 208</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E4 209</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E5 210</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E6 211</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E7 212</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E8 213</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E9 214</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E10 215</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E11 216</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E12 217</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E13 218</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E14 219</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E15 220</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E16 221</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E17 222</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E18 223</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E19 224</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E20 225</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E21 226</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E22 227</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E23 228</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group Jtag */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_53 229</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_54 230</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_55 231</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_56 232</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_57 233</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_58 234</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_59 235</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_60 236</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_61 237</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group HVMOS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_62 238</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_63 239</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_64 240</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_65 241</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_66 242</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_67 243</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM4_PADS (GPIO_RSVD_67 - GPP_C0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group GPD */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD0 244</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD1 245</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD2 246</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD3 247</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD4 248</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD5 249</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD6 250</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD7 251</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD8 252</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD9 253</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD10 254</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD11 255</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group AZA */</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDA_BCLK 256</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDA_RSTB 257</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDA_SYNC 258</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDA_SDO 259</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDA_SDI_0 260</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDA_SDI_1 261</span><br><span style="color: hsl(120, 100%, 40%);">+#define SSP1_SFRM 262</span><br><span style="color: hsl(120, 100%, 40%);">+#define SSP1_TXD 263</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_68 264</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_69 265</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_70 266</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_71 267</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_72 268</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_73 269</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_74 270</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_75 271</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_76 272</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_77 273</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_78 274</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM3_PADS (GPIO_RSVD_78 - HDA_BCLK + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOTAL_PADS 275</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h</span><br><span>new file mode 100755</span><br><span>index 0000000..7c42b57</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/iomap.h</span><br><span>@@ -0,0 +1,86 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ICELAKE_IOMAP_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ICELAKE_IOMAP_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Memory-mapped I/O registers.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCFG_BASE_SIZE 0x4000000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_PRESERVED_BASE_SIZE 0x02000000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_TRACE_HUB_BASE_SIZE 0x00800000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART_BASE_SIZE 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART_BASE_0_ADDRESS 0xfe032000</span><br><span style="color: hsl(120, 100%, 40%);">+/* Both UART BAR 0 and 1 are 4KB in size */</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \</span><br><span style="color: hsl(120, 100%, 40%);">+ UART_BASE_SIZE * (x)))</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART_BASE(x) UART_BASE_0_ADDR(x)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define EARLY_I2C_BASE_ADDRESS 0xfe040000</span><br><span style="color: hsl(120, 100%, 40%);">+#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCH_BASE_ADDRESS 0xfed10000</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCH_BASE_SIZE 0x8000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DMI_BASE_ADDRESS 0xfeda0000</span><br><span style="color: hsl(120, 100%, 40%);">+#define DMI_BASE_SIZE 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define EP_BASE_ADDRESS 0xfeda1000</span><br><span style="color: hsl(120, 100%, 40%);">+#define EP_BASE_SIZE 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDRAM_BASE_ADDRESS 0xfed80000</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDRAM_BASE_SIZE 0x4000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define REG_BASE_ADDRESS 0xfc000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define REG_BASE_SIZE 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define HPET_BASE_ADDRESS 0xfed00000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_PWRM_BASE_ADDRESS 0xfe000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_PWRM_BASE_SIZE 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_BASE_ADDRESS 0xfe010000</span><br><span style="color: hsl(120, 100%, 40%);">+#define EARLY_GSPI_BASE_ADDRESS 0xfe011000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_BASE_SIZE 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define HECI1_BASE_ADDRESS 0xfeda2000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define VTD_BASE_ADDRESS 0xFED90000</span><br><span style="color: hsl(120, 100%, 40%);">+#define VTD_BASE_SIZE 0x00004000</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * I/O port address space</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMBUS_BASE_ADDRESS 0x0efa0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMBUS_BASE_SIZE 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_BASE_ADDRESS 0x1800</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_BASE_SIZE 0x100</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_BASE_ADDRESS 0x400</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_BASE_SIZE 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_SIZE (16 * MiB)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/irq.h b/src/soc/intel/icelake/include/soc/irq.h</span><br><span>new file mode 100755</span><br><span>index 0000000..2f980ff</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/irq.h</span><br><span>@@ -0,0 +1,106 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_IRQ_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_IRQ_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_IRQ14 14</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_IRQ15 15</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_IRQ10 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_IRQ11 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_IRQ9 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_IRQ10 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_IRQ11 11</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_IRQ20 20</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_IRQ21 21</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_IRQ22 22</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_IRQ23 23</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_IRQ9 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_IRQ10 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_IRQ11 11</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_IRQ20 20</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_IRQ21 21</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_IRQ22 22</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_IRQ23 23</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPSS_I2C0_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPSS_I2C1_IRQ 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPSS_I2C2_IRQ 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPSS_I2C3_IRQ 19</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPSS_I2C4_IRQ 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPSS_I2C5_IRQ 33</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPSS_SPI0_IRQ 22</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPSS_SPI1_IRQ 23</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPSS_SPI2_IRQ 24</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPSS_UART0_IRQ 20</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPSS_UART1_IRQ 21</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPSS_UART2_IRQ 34</span><br><span style="color: hsl(120, 100%, 40%);">+#define SDIO_IRQ 22</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define cAVS_INTA_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMBUS_INTA_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMBUS_INTB_IRQ 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define GbE_INTA_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define GbE_INTC_IRQ 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRACE_HUB_INTA_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRACE_HUB_INTD_IRQ 19</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define eMMC_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define SD_IRQ 19</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_1_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_2_IRQ 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_3_IRQ 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_4_IRQ 19</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_5_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_6_IRQ 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_7_IRQ 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_8_IRQ 19</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_9_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_10_IRQ 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_11_IRQ 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_12_IRQ 19</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATA_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define HECI_1_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define HECI_2_IRQ 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define IDER_IRQ 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define KT_IRQ 19</span><br><span style="color: hsl(120, 100%, 40%);">+#define HECI_3_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define XHCI_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define OTG_IRQ 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_SRAM_IRQ 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define THERMAL_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define CNViWIFI_IRQ 19</span><br><span style="color: hsl(120, 100%, 40%);">+#define UFS_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define CIO_INTA_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define CIO_INTD_IRQ 19</span><br><span style="color: hsl(120, 100%, 40%);">+#define ISH_IRQ 20</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PEG_RP_INTA_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define PEG_RP_INTB_IRQ 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define PEG_RP_INTC_IRQ 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define PEG_RP_INTD_IRQ 19</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define IGFX_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define SA_THERMAL_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define IPU_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define GNA_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _SOC_IRQ_H_ */</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/itss.h b/src/soc/intel/icelake/include/soc/itss.h</span><br><span>new file mode 100755</span><br><span>index 0000000..d846ce0</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/itss.h</span><br><span>@@ -0,0 +1,26 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_INTEL_ICL_ITSS_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_INTEL_ICL_ITSS_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_IRQ_START 50</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_IRQ_END ITSS_MAX_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define ITSS_MAX_IRQ 119</span><br><span style="color: hsl(120, 100%, 40%);">+#define IRQS_PER_IPC 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOC_INTEL_ICL_ITSS_H */</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/lpc.h b/src/soc/intel/icelake/include/soc/lpc.h</span><br><span>new file mode 100755</span><br><span>index 0000000..df781be</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/lpc.h</span><br><span>@@ -0,0 +1,66 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ICELAKE_LPC_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ICELAKE_LPC_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCI Configuration Space (D31:F0): LPC */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_IRQ_SEL (7 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ9 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ10 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ11 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ20 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ21 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ22 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ23 7</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIRQ_CNTL 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */</span><br><span style="color: hsl(120, 100%, 40%);">+#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/</span><br><span style="color: hsl(120, 100%, 40%);">+#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_EN 0x82 /* LPC IF Enables Register */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MC2_LPC_EN (1 << 13) /* 0x4e/0x4f */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SE_LPC_EN (1 << 12) /* 0x2e/0x2f */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MC1_LPC_EN (1 << 11) /* 0x62/0x66 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDD_LPC_EN (1 << 3) /* Floppy Drive Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPT_LPC_EN (1 << 2) /* Parallel Port Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+#define COMB_LPC_EN (1 << 1) /* Com Port B Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+#define COMA_LPC_EN (1 << 0) /* Com Port A Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LGMR 0x98 /* LPC Generic Memory Range */</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIOS_CNTL 0xdc</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_BC_BILD (1 << 7) /* BILD */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_BC_LE (1 << 1) /* LE */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_BC_EISS (1 << 5) /* EISS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCCTL 0xE0 /* PCI Clock Control */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CLKRUN_EN (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This function will help to differentiate between 2 PCH on single type of soc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Since same soc may have LP series pch or H series PCH, we need to</span><br><span style="color: hsl(120, 100%, 40%);">+ * differentiate by reading upper 8 bits of PCH device ids.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Return:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Return PCH_LP or PCH_H macro in case of respective device ID found.</span><br><span style="color: hsl(120, 100%, 40%);">+ * PCH_UNKNOWN_SERIES in case of invalid device ID.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+uint8_t get_pch_series(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/msr.h b/src/soc/intel/icelake/include/soc/msr.h</span><br><span>new file mode 100644</span><br><span>index 0000000..2aa79af</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/msr.h</span><br><span>@@ -0,0 +1,24 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_MSR_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_MSR_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PIC_MSG_CONTROL 0x2e</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_VR_MISC_CONFIG2 0x636</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/nvs.h b/src/soc/intel/icelake/include/soc/nvs.h</span><br><span>new file mode 100755</span><br><span>index 0000000..b2d903a</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/nvs.h</span><br><span>@@ -0,0 +1,49 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_NVS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_NVS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <vendorcode/google/chromeos/gnvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct global_nvs_t {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Miscellaneous */</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 osys; /* 0x00 - 0x01 Operating System */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 smif; /* 0x02 - SMI function call ("TRAP") */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pcnt; /* 0x03 - Processor Count */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ppcm; /* 0x04 - Max PPC State */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 tlvl; /* 0x05 - Throttle Level Limit */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 lids; /* 0x06 - LID State */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pwrs; /* 0x07 - AC Power State */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cbmc; /* 0x08 - 0xb AC Power State */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 gpei; /* 0x14 - 0x1b GPE wake status bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dpte; /* 0x1c - Enable DPTF */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 nhla; /* 0x1d - 0x24 NHLT Address */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 nhll; /* 0x25 - 0x28 NHLT Length */</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 cid1; /* 0x29 - 0x2a Wifi Country Identifier */</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 uior; /* 0x2f - UART debug controller init on S3 resume */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 unused[208];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ChromeOS specific (0x100 - 0xfff) */</span><br><span style="color: hsl(120, 100%, 40%);">+ chromeos_acpi_t chromeos;</span><br><span style="color: hsl(120, 100%, 40%);">+} __packed global_nvs_t;</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/p2sb.h b/src/soc/intel/icelake/include/soc/p2sb.h</span><br><span>new file mode 100644</span><br><span>index 0000000..253b54c</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/p2sb.h</span><br><span>@@ -0,0 +1,24 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ICELAKE_P2SB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ICELAKE_P2SB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define HPTC_OFFSET 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+#define HPTC_ADDR_ENABLE_BIT (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_P2SB_EPMASK0 0x220</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/pch.h b/src/soc/intel/icelake/include/soc/pch.h</span><br><span>new file mode 100644</span><br><span>index 0000000..d5478d2</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/pch.h</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ICELAKE_PCH_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ICELAKE_PCH_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_H 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_LP 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_UNKNOWN_SERIES 0xFF</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_CLK_NOTUSED 0xFF</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_CLK_LAN 0x70</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_CLK_FREE 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_log_state(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h</span><br><span>new file mode 100644</span><br><span>index 0000000..fe00bd0</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/pci_devs.h</span><br><span>@@ -0,0 +1,177 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ICELAKE_PCI_DEVS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ICELAKE_PCI_DEVS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <rules.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if !defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))</span><br><span style="color: hsl(120, 100%, 40%);">+#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func))</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* System Agent Devices */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SA_DEV_SLOT_ROOT 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define SA_DEVFN_ROOT _SA_DEVFN(ROOT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SA_DEV_ROOT _SA_DEV(ROOT)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SA_DEV_SLOT_IGD 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+#define SA_DEVFN_IGD _SA_DEVFN(IGD)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SA_DEV_IGD _SA_DEV(IGD)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SA_DEV_SLOT_DSP 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+#define SA_DEVFN_DSP _SA_DEVFN(DSP)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SA_DEV_DSP _SA_DEV(DSP)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH Devices */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_THERMAL 0x12</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_GSPI2 _PCH_DEVFN(THERMAL, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_THERMAL _PCH_DEV(THERMAL, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_UFS _PCH_DEV(THERMAL, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_GSPI2 _PCH_DEV(THERMAL, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_ISH 0x13</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_ISH _PCH_DEV(ISH, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_XHCI 0x14</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_CNViWIFI _PCH_DEVFN(XHCI, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_CNViWIFI _PCH_DEV(XHCI, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_SIO1 0x15</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO1, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO1, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO1, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_I2C0 _PCH_DEV(SIO1, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_I2C1 _PCH_DEV(SIO1, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_I2C2 _PCH_DEV(SIO1, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_I2C3 _PCH_DEV(SIO1, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_CSE 0x16</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_CSE _PCH_DEV(CSE, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_SATA 0x17</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SATA _PCH_DEV(SATA, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_SIO2 0x19</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_UART2 _PCH_DEV(SIO2, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_STORAGE 0x1A</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_PCIE 0x1c</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE3 _PCH_DEVFN(PCIE, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_PCIE_1 0x1d</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE13 _PCH_DEVFN(PCIE_1, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE14 _PCH_DEVFN(PCIE_1, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE15 _PCH_DEVFN(PCIE_1, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE16 _PCH_DEVFN(PCIE_1, 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE13 _PCH_DEV(PCIE_1, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE14 _PCH_DEV(PCIE_1, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_SIO3 0x1e</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO3, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO3, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_UART0 _PCH_DEV(SIO3, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_UART1 _PCH_DEV(SIO3, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_LPC 0x1f</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_HDA _PCH_DEVFN(LPC, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_GBE _PCH_DEVFN(LPC, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(LPC, 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_LPC _PCH_DEV(LPC, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_P2SB _PCH_DEV(LPC, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PMC _PCH_DEV(LPC, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_HDA _PCH_DEV(LPC, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SPI _PCH_DEV(LPC, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_GBE _PCH_DEV(LPC, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/pcr_ids.h b/src/soc/intel/icelake/include/soc/pcr_ids.h</span><br><span>new file mode 100644</span><br><span>index 0000000..b75bf67</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/pcr_ids.h</span><br><span>@@ -0,0 +1,42 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_ICELAKE_PCR_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_ICELAKE_PCR_H</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Port ids</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_EMMC 0x52</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_SDX 0x53</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIOCOM4 0x6a</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIOCOM3 0x6b</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIOCOM2 0x6c</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIOCOM1 0x6d</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIOCOM0 0x6e</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_DMI 0x88</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_PSTH 0x89</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_CSME0 0x90</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_ISCLK 0xad</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_PSF1 0xba</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_PSF2 0xbb</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_PSF3 0xbc</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_PSF4 0xbd</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_SCS 0xc0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_RTC 0xc3</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_ITSS 0xc2</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_LPC 0xc7</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_SERIALIO 0xcb</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h</span><br><span>new file mode 100644</span><br><span>index 0000000..6b1b298</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/pm.h</span><br><span>@@ -0,0 +1,173 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_PM_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_PM_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM1_STS 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define WAK_STS (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIEXPWAK_STS (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRBTNOR_STS (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RTC_STS (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PWRBTN_STS (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GBL_STS (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BM_STS (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TMROF_STS (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM1_EN 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIEXPWAK_DIS (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RTC_EN (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PWRBTN_EN (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GBL_EN (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TMROF_EN (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM1_CNT 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+#define GBL_RLS (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BM_RLD (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_EN (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM1_TMR 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMI_EN 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+#define XHCI_SMI_EN (1 << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ME_SMI_EN (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ESPI_SMI_EN (1 << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_UNLOCK_SMI_EN (1 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define INTEL_USB2_EN (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LEGACY_USB2_EN (1 << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PERIODIC_EN (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_SMI_EN (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCSMI_EN (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIOS_RLS (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SWSMI_TMR_EN (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define APMC_EN (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SLP_SMI_EN (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LEGACY_USB_EN (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIOS_EN (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define EOS (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GBL_SMI_EN (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMI_STS 0x34</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMI_STS_BITS 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define XHCI_SMI_STS_BIT 31</span><br><span style="color: hsl(120, 100%, 40%);">+#define ME_SMI_STS_BIT 30</span><br><span style="color: hsl(120, 100%, 40%);">+#define ESPI_SMI_STS_BIT 28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_UNLOCK_SMI_STS_BIT 27</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_SMI_STS_BIT 26</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCC_SMI_STS_BIT 25</span><br><span style="color: hsl(120, 100%, 40%);">+#define MONITOR_STS_BIT 21</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_EXP_SMI_STS_BIT 20</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMBUS_SMI_STS_BIT 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIRQ_SMI_STS_BIT 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define PERIODIC_STS_BIT 14</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_STS_BIT 13</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEVMON_STS_BIT 12</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCSMI_STS_BIT 11</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_STS_BIT 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_STS_BIT 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM1_STS_BIT 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define SWSMI_TMR_STS_BIT 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define APM_STS_BIT 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMI_ON_SLP_EN_STS_BIT 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define LEGACY_USB_STS_BIT 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIOS_STS_BIT 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_CNTL 0x42</span><br><span style="color: hsl(120, 100%, 40%);">+#define SWGPE_CTRL (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEVACT_STS 0x44</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM2_CNT 0x50</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_REG_MAX 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_REG_SIZE 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_STS(x) (0x60 + ((x) * 4))</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_STS_RSVD GPE_STD</span><br><span style="color: hsl(120, 100%, 40%);">+#define WADT_STS (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_T2_STS (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ESPI_STS (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PME_B0_STS (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ME_SCI_STS (1 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PME_STS (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BATLOW_STS (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_EXP_STS (1 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMB_WAK_STS (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCOSCI_STS (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SWGPE_STS (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HOT_PLUG_STS (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_EN(x) (0x70 + ((x) * 4))</span><br><span style="color: hsl(120, 100%, 40%);">+#define WADT_EN (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_T2_EN (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ESPI_EN (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PME_B0_EN_BIT 13</span><br><span style="color: hsl(120, 100%, 40%);">+#define PME_B0_EN (1 << PME_B0_EN_BIT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ME_SCI_EN (1 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PME_EN (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BATLOW_EN (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_EXP_EN (1 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCOSCI_EN (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SWGPE_EN (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HOT_PLUG_EN (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define EN_BLOCK 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable SMI generation:</span><br><span style="color: hsl(120, 100%, 40%);">+ * - on APMC writes (io 0xb2)</span><br><span style="color: hsl(120, 100%, 40%);">+ * - on writes to SLP_EN (sleep states)</span><br><span style="color: hsl(120, 100%, 40%);">+ * - on writes to GBL_RLS (bios commands)</span><br><span style="color: hsl(120, 100%, 40%);">+ * - on eSPI events (does nothing on LPC systems)</span><br><span style="color: hsl(120, 100%, 40%);">+ * No SMIs:</span><br><span style="color: hsl(120, 100%, 40%);">+ * - on microcontroller writes (io 0x62/0x66)</span><br><span style="color: hsl(120, 100%, 40%);">+ * - on TCO events</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENABLE_SMI_PARAMS \</span><br><span style="color: hsl(120, 100%, 40%);">+ (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PSS_RATIO_STEP 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define PSS_MAX_ENTRIES 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define PSS_LATENCY_TRANSITION 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define PSS_LATENCY_BUSMASTER 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if !defined(__ACPI__)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpe.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smbus.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pmc.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chipset_power_state {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t pm1_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t pm1_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pm1_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tco1_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tco2_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_sts[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_en[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gen_pmcon_a;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gen_pmcon_b;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gblrst_cause[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t prev_sleep_state;</span><br><span style="color: hsl(120, 100%, 40%);">+} __packed;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Get base address PMC memory mapped registers. */</span><br><span style="color: hsl(120, 100%, 40%);">+uint8_t *pmc_mmio_regs(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Get base address of TCO I/O registers. */</span><br><span style="color: hsl(120, 100%, 40%);">+uint16_t smbus_tco_regs(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set the DISB after DRAM init */</span><br><span style="color: hsl(120, 100%, 40%);">+void pmc_set_disb(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* !defined(__ACPI__) */</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/pmc.h b/src/soc/intel/icelake/include/soc/pmc.h</span><br><span>new file mode 100644</span><br><span>index 0000000..9418c73</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/pmc.h</span><br><span>@@ -0,0 +1,149 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ICELAKE_PMC_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ICELAKE_PMC_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCI Configuration Space (D31:F2): PMC */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PWRMBASE 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define ABASE 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Memory mapped IO registers in PMC */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN_PMCON_A 0x1020</span><br><span style="color: hsl(120, 100%, 40%);">+#define DC_PP_DIS (1 << 30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSX_PP_DIS (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AG3_PP_EN (1 << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SX_PP_EN (1 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ALLOW_ICLK_PLL_SD_INC0 (1 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GBL_RST_STS (1 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISB (1 << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ALLOW_OPI_PLL_SD_INC0 (1 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MEM_SR (1 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ALLOW_SPXB_CG_INC0 (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ALLOW_L1LOW_C0 (1 << 19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MS4V (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ALLOW_L1LOW_OPI_ON (1 << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUS_PWR_FLR (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PME_B0_S5_DIS (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PWR_FLR (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIS_SLP_X_STRCH_SUS_UP (1 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HOST_RST_STS (1 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ESPI_SMI_LOCK (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define S4MAW_MASK (3 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define S4MAW_1S (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define S4MAW_2S (2 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define S4MAW_3S (3 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define S4MAW_4S (0 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define S4ASE (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PER_SMI_SEL_MASK (3 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMI_RATE_64S (0 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMI_RATE_32S (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMI_RATE_16S (2 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMI_RATE_8S (3 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SLEEP_AFTER_POWER_FAIL (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN_PMCON_B 0x1024</span><br><span style="color: hsl(120, 100%, 40%);">+#define SLP_STR_POL_LOCK (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_BASE_LOCK (1 << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM_DATA_BAR_DIS (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WOL_EN_OVRD (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIOS_PCI_EXP_EN (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PWRBTN_LVL (1 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMI_LOCK (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RTC_BATTERY_DEAD (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define ETR 0x1048</span><br><span style="color: hsl(120, 100%, 40%);">+#define CF9_LOCK (1 << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CF9_GLB_RST (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SSML 0x104C</span><br><span style="color: hsl(120, 100%, 40%);">+#define SSML_SSL_DS (0 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SSML_SSL_EN (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SSMC 0x1050</span><br><span style="color: hsl(120, 100%, 40%);">+#define SSMC_SSMS (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SSMD 0x1054</span><br><span style="color: hsl(120, 100%, 40%);">+#define SSMD_SSD_MASK (0xffff << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRSTS 0x1810</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define S3_PWRGATE_POL 0x1828</span><br><span style="color: hsl(120, 100%, 40%);">+#define S3DC_GATE_SUS (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define S3AC_GATE_SUS (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define S4_PWRGATE_POL 0x182c</span><br><span style="color: hsl(120, 100%, 40%);">+#define S4DC_GATE_SUS (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define S4AC_GATE_SUS (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define S5_PWRGATE_POL 0x1830</span><br><span style="color: hsl(120, 100%, 40%);">+#define S5DC_GATE_SUS (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define S5AC_GATE_SUS (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSX_CFG 0x1834</span><br><span style="color: hsl(120, 100%, 40%);">+#define REQ_CNV_NOWAKE_DSX (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define REQ_BATLOW_DSX (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSX_EN_WAKE_PIN (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSX_DIS_AC_PRESENT_PD (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSX_EN_LAN_WAKE_PIN (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DSX_CFG_MASK (0x1f << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMSYNC_TPR_CFG 0x18C4</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH2CPU_TPR_CFG_LOCK (1 << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH2CPU_TT_EN (1 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_PWRM_ACPI_TMR_CTL 0x18FC</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_GPE_CFG 0x1920</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DWX_MASK 0xf</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW_SHIFT(x) (4*(x))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_A 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_B 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_C 0xD</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_D 0x4</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_E 0xE</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_F 0x5</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_G 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_H 0x6</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPD 0xA</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GBLRST_CAUSE0 0x1924</span><br><span style="color: hsl(120, 100%, 40%);">+#define GBLRST_CAUSE0_THERMTRIP (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GBLRST_CAUSE1 0x1928</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPPMVRIC 0x1B1C</span><br><span style="color: hsl(120, 100%, 40%);">+#define XTALSDQDIS (1 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define IRQ_REG ACTL</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_IRQ_ADJUST 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACTL 0x1BD8</span><br><span style="color: hsl(120, 100%, 40%);">+#define PWRM_EN (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_EN (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCI_IRQ_SEL (7 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ9 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ10 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ11 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ20 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ21 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ22 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCIS_IRQ23 7</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/ramstage.h b/src/soc/intel/icelake/include/soc/ramstage.h</span><br><span>new file mode 100644</span><br><span>index 0000000..d0b500d</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/ramstage.h</span><br><span>@@ -0,0 +1,27 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_RAMSTAGE_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_RAMSTAGE_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_silicon_init_params(FSP_S_CONFIG *params);</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_init_pre_device(void *chip_info);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/romstage.h b/src/soc/intel/icelake/include/soc/romstage.h</span><br><span>new file mode 100644</span><br><span>index 0000000..1517264</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/romstage.h</span><br><span>@@ -0,0 +1,33 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ROMSTAGE_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ROMSTAGE_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/api.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_memory_init_params(FSPM_UPD *mupd);</span><br><span style="color: hsl(120, 100%, 40%);">+void systemagent_early_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Board type */</span><br><span style="color: hsl(120, 100%, 40%);">+enum board_type {</span><br><span style="color: hsl(120, 100%, 40%);">+ BOARD_TYPE_MOBILE = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ BOARD_TYPE_DESKTOP = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ BOARD_TYPE_ULT_ULX = 5,</span><br><span style="color: hsl(120, 100%, 40%);">+ BOARD_TYPE_SERVER = 7</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _SOC_ROMSTAGE_H_ */</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/serialio.h b/src/soc/intel/icelake/include/soc/serialio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..30a48a1</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/serialio.h</span><br><span>@@ -0,0 +1,42 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SERIALIO_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SERIALIO_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+typedef enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoAcpi,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoHidden,</span><br><span style="color: hsl(120, 100%, 40%);">+} PCH_SERIAL_IO_MODE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+typedef enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexI2C0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexI2C1,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexI2C2,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexI2C3,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexI2C4,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexI2C5,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexSPI0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexSPI1,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexSPI2,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexUART0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexUART1,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexUART2,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexMAX</span><br><span style="color: hsl(120, 100%, 40%);">+} PCH_SERIAL_IO_CONTROLLER;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/smbus.h b/src/soc/intel/icelake/include/soc/smbus.h</span><br><span>new file mode 100644</span><br><span>index 0000000..64c3eb3</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/smbus.h</span><br><span>@@ -0,0 +1,44 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ICELAKE_SMBUS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ICELAKE_SMBUS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCI registers */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCOBASE 0x50 /* TCO base address. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCOCTL 0x54</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_BASE_EN (1 << 8) /* TCO base enable. */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* IO and MMIO registers under primary BAR */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set address for PCH as SMBus slave role */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMB_RCV_SLVA 0x09</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO1_STS 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_TIMEOUT (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO2_STS 0x06</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO2_STS_SECOND_TO (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO1_CNT 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_LOCK (1 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_TMR_HLT (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Default slave address value for PCH. This value is set to match default</span><br><span style="color: hsl(120, 100%, 40%);">+ * value set by hardware. It is useful since PCH is able to respond even</span><br><span style="color: hsl(120, 100%, 40%);">+ * before CPU is up. This is reset by RSMRST# but not by PLTRST#.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMBUS_SLAVE_ADDR 0x44</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h</span><br><span>new file mode 100644</span><br><span>index 0000000..a9cd748</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/smm.h</span><br><span>@@ -0,0 +1,70 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_SMM_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_SMM_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/memmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct ied_header {</span><br><span style="color: hsl(120, 100%, 40%);">+ char signature[10];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 size;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reserved[34];</span><br><span style="color: hsl(120, 100%, 40%);">+} __packed;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct smm_relocation_params {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smram_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smram_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ied_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ied_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t smrr_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t smrr_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t emrr_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t emrr_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t uncore_emrr_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t uncore_emrr_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The smm_save_state_in_msrs field indicates if SMM save state</span><br><span style="color: hsl(120, 100%, 40%);">+ * locations live in MSRs. This indicates to the CPUs how to adjust</span><br><span style="color: hsl(120, 100%, 40%);">+ * the SMMBASE and IEDBASE</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ int smm_save_state_in_msrs;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Mainboard handler for eSPI SMIs */</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_smi_espi_handler(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_relocation_handler(int cpu, uintptr_t curr_smbase,</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t staggered_smbase);</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t *smm_save_state_size);</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_initialize(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_relocate(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#else /* CONFIG_HAVE_SMI_HANDLER */</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void smm_relocation_handler(int cpu, uintptr_t curr_smbase,</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t staggered_smbase) {}</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t *smm_save_state_size) {}</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void smm_initialize(void) {}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void smm_relocate(void) {}</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* CONFIG_HAVE_SMI_HANDLER */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/soc_chip.h b/src/soc/intel/icelake/include/soc/soc_chip.h</span><br><span>new file mode 100644</span><br><span>index 0000000..2d996e9</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/soc_chip.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_ICELAKE_SOC_CHIP_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_ICELAKE_SOC_CHIP_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "../../chip.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _SOC_ICELAKE_SOC_CHIP_H_ */</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/systemagent.h b/src/soc/intel/icelake/include/soc/systemagent.h</span><br><span>new file mode 100644</span><br><span>index 0000000..4e78ceb</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/systemagent.h</span><br><span>@@ -0,0 +1,44 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_ICELAKE_SYSTEMAGENT_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_ICELAKE_SYSTEMAGENT_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Device 0:0.0 PCI configuration space */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define EPBAR 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define DMIBAR 0x68</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMRAM 0x88 /* System Management RAM Control */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D_OPEN (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define D_CLS (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define D_LCK (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define G_SMRAME (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIOS_RESET_CPL 0x5da8</span><br><span style="color: hsl(120, 100%, 40%);">+#define EDRAMBAR 0x5408</span><br><span style="color: hsl(120, 100%, 40%);">+#define REGBAR 0x5420</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCH_PKG_POWER_LIMIT_LO 0x59a0</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCH_PKG_POWER_LIMIT_HI 0x59a4</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCH_DDR_POWER_LIMIT_LO 0x58e0</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCH_DDR_POWER_LIMIT_HI 0x58e4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define IMRBASE 0x6A40</span><br><span style="color: hsl(120, 100%, 40%);">+#define IMRLIMIT 0x6A48</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/usb.h b/src/soc/intel/icelake/include/soc/usb.h</span><br><span>new file mode 100644</span><br><span>index 0000000..d2e50ef</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/include/soc/usb.h</span><br><span>@@ -0,0 +1,152 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_USB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_USB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Per Port HS Transmitter Emphasis */</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_EMP_OFF 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_DE_EMP_ON 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_PRE_EMP_ON 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_DE_EMP_ON_PRE_EMP_ON 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Per Port Half Bit Pre-emphasis */</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_FULL_BIT_PRE_EMP 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_HALF_BIT_PRE_EMP 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Per Port HS Preemphasis Bias */</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_BIAS_0MV 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_BIAS_11P25MV 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_BIAS_16P9MV 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_BIAS_28P15MV 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_BIAS_39P35MV 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_BIAS_45MV 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_BIAS_56P3MV 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct usb2_port_config {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t ocpin;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t tx_bias;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t tx_emp_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pre_emp_bias;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pre_emp_bit;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB Overcurrent pins definition */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ OC0 = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ OC1,</span><br><span style="color: hsl(120, 100%, 40%);">+ OC2,</span><br><span style="color: hsl(120, 100%, 40%);">+ OC3,</span><br><span style="color: hsl(120, 100%, 40%);">+ OC4,</span><br><span style="color: hsl(120, 100%, 40%);">+ OC5,</span><br><span style="color: hsl(120, 100%, 40%);">+ OC6,</span><br><span style="color: hsl(120, 100%, 40%);">+ OC7,</span><br><span style="color: hsl(120, 100%, 40%);">+ OCMAX,</span><br><span style="color: hsl(120, 100%, 40%);">+ OC_SKIP = 0xff, /* Skip OC programming */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Standard USB Port based on length:</span><br><span style="color: hsl(120, 100%, 40%);">+ * - External</span><br><span style="color: hsl(120, 100%, 40%);">+ * - Back Panel</span><br><span style="color: hsl(120, 100%, 40%);">+ * - OTG</span><br><span style="color: hsl(120, 100%, 40%);">+ * - M.2</span><br><span style="color: hsl(120, 100%, 40%);">+ * - Internal device down */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_PORT_EMPTY { \</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable = 0, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .ocpin = OC_SKIP, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_bias = USB2_BIAS_0MV, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_emp_enable = USB2_EMP_OFF, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_emp_bias = USB2_BIAS_0MV, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Length = 11.5"-12" */</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_PORT_LONG(pin) { \</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .ocpin = (pin), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_bias = USB2_BIAS_39P35MV, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_emp_enable = USB2_PRE_EMP_ON, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_emp_bias = USB2_BIAS_56P3MV, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Length = 6"-11.49" */</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_PORT_MID(pin) { \</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .ocpin = (pin), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_bias = USB2_BIAS_0MV, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_emp_enable = USB2_PRE_EMP_ON, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_emp_bias = USB2_BIAS_56P3MV, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Length = 3"-5.99" */</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_PORT_SHORT(pin) { \</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .ocpin = (pin), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_bias = USB2_BIAS_39P35MV, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_emp_bias = USB2_BIAS_39P35MV, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Max TX and Pre-emp settings */</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_PORT_MAX(pin) { \</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .ocpin = (pin), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_bias = USB2_BIAS_56P3MV, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_emp_enable = USB2_PRE_EMP_ON, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_emp_bias = USB2_BIAS_56P3MV, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Type-C Port, no BC1.2 charge detect module / MUX</span><br><span style="color: hsl(120, 100%, 40%);">+ * Length = 3.0" - 9.00" */</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_PORT_TYPE_C(pin) { \</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .ocpin = (pin), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_bias = USB2_BIAS_0MV, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_emp_enable = USB2_PRE_EMP_ON, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_emp_bias = USB2_BIAS_56P3MV, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct usb3_port_config {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t ocpin;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t tx_de_emp;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t tx_downscale_amp;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB3_PORT_EMPTY { \</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable = 0, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .ocpin = OC_SKIP, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_de_emp = 0x00, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_downscale_amp = 0x00, \</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB3_PORT_DEFAULT(pin) { \</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .ocpin = (pin), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_de_emp = 0x0, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .tx_downscale_amp = 0x00, \</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/lockdown.c b/src/soc/intel/icelake/lockdown.c</span><br><span>new file mode 100644</span><br><span>index 0000000..5581e16</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/lockdown.c</span><br><span>@@ -0,0 +1,72 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelpch/lockdown.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pmc_lock_pmsync(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *pmcbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pmsyncreg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pmcbase = pmc_mmio_regs();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);</span><br><span style="color: hsl(120, 100%, 40%);">+ pmsyncreg |= PCH2CPU_TPR_CFG_LOCK;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pmc_lock_abase(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *pmcbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pmcbase = pmc_mmio_regs();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = read32(pmcbase + GEN_PMCON_B);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pmcbase + GEN_PMCON_B, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pmc_lock_smi(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *pmcbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pmcbase = pmc_mmio_regs();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = read8(pmcbase + GEN_PMCON_B);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 |= SMI_LOCK;</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(pmcbase + GEN_PMCON_B, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pmc_lockdown_cfg(int chipset_lockdown)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PMSYNC */</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_lock_pmsync();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Lock down ABASE and sleep stretching policy */</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_lock_abase();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_lock_smi();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_lockdown_config(int chipset_lockdown)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PMC lock down configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_lockdown_cfg(chipset_lockdown);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/lpc.c b/src/soc/intel/icelake/lpc.c</span><br><span>new file mode 100755</span><br><span>index 0000000..8859c5d</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/lpc.c</span><br><span>@@ -0,0 +1,257 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "chip.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <pc80/isa-dma.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <pc80/i8259.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/ioapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/itss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <reg_script.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/lpc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve</span><br><span style="color: hsl(120, 100%, 40%);">+* certain memory range as reserved range for BIOS usage.</span><br><span style="color: hsl(120, 100%, 40%);">+* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"</span><br><span style="color: hsl(120, 100%, 40%);">+*/</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct lpc_mmio_range icl_lpc_fixed_mmio_ranges[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 0 }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return icl_lpc_fixed_mmio_ranges;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const config_t *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gen_io_dec[0] = config->gen1_dec;</span><br><span style="color: hsl(120, 100%, 40%);">+ gen_io_dec[1] = config->gen2_dec;</span><br><span style="color: hsl(120, 100%, 40%);">+ gen_io_dec[2] = config->gen3_dec;</span><br><span style="color: hsl(120, 100%, 40%);">+ gen_io_dec[3] = config->gen4_dec;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Mirror these same settings in DMI PCR */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint8_t get_pch_series(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t lpc_did_hi_byte;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Fetch upper 8 bits on LPC device ID to determine PCH type</span><br><span style="color: hsl(120, 100%, 40%);">+ * Adding 1 to the offset to fetch upper 8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc_did_hi_byte = pci_read_config8(PCH_DEV_LPC, PCI_DEVICE_ID + 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (lpc_did_hi_byte == 0x9D)</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_LP;</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (lpc_did_hi_byte == 0xA3)</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_H;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_UNKNOWN_SERIES;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if ENV_RAMSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_mirror_dmi_pcr_io_dec(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t io_dec_arr[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC),</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC),</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC),</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC),</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Mirror these same settings in DMI PCR */</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_enable_ioapic(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCH-LP has 120 redirection entries */</span><br><span style="color: hsl(120, 100%, 40%);">+ const int redir_entries = 120;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ set_ioapic_id((void *)IO_APIC_ADDR, 0x02);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* affirm full set of redirection table entries ("write once") */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~0x00ff0000;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= (redir_entries - 1) << 16;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Select Boot Configuration register (0x03) and</span><br><span style="color: hsl(120, 100%, 40%);">+ * use Processor System Bus (0x01) to deliver interrupts.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x00 - 0000 = Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x01 - 0001 = Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x02 - 0010 = Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x03 - 0011 = IRQ3</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x04 - 0100 = IRQ4</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x05 - 0101 = IRQ5</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x06 - 0110 = IRQ6</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x07 - 0111 = IRQ7</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x08 - 1000 = Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x09 - 1001 = IRQ9</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0A - 1010 = IRQ10</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0B - 1011 = IRQ11</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0C - 1100 = IRQ12</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0D - 1101 = Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0E - 1110 = IRQ14</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0F - 1111 = IRQ15</span><br><span style="color: hsl(120, 100%, 40%);">+ * PIRQ[n]_ROUT[7] - PIRQ Routing Control</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x80 - The PIRQ is not routed.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_pch_pirq_init(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const config_t *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[0] = config->pirqa_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[1] = config->pirqb_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[2] = config->pirqc_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[3] = config->pirqd_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[4] = config->pirqe_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[5] = config->pirqf_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[6] = config->pirqg_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[7] = config->pirqh_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ itss_irq_init(pch_interrupt_routing);</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 int_pin = 0, int_line = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (int_pin) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1: /* INTA# */</span><br><span style="color: hsl(120, 100%, 40%);">+ int_line = config->pirqa_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2: /* INTB# */</span><br><span style="color: hsl(120, 100%, 40%);">+ int_line = config->pirqb_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 3: /* INTC# */</span><br><span style="color: hsl(120, 100%, 40%);">+ int_line = config->pirqc_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 4: /* INTD# */</span><br><span style="color: hsl(120, 100%, 40%);">+ int_line = config->pirqd_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!int_line)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_misc_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setup NMI on errors, disable SERR */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = (inb(0x61)) & 0xf0;</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x61, (reg8 | (1 << 2)));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable NMI sources */</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x70, (1 << 7));</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void clock_gate_8254(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const config_t *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!config->clock_gate_8254)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ itss_clock_gate_8254();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void lpc_soc_init(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Legacy initialization */</span><br><span style="color: hsl(120, 100%, 40%);">+ isa_dma_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_misc_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable CLKRUN_EN for power gating LPC */</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc_enable_pci_clk_cntl();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set LPC Serial IRQ mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc_set_serirq_mode(SERIRQ_CONTINUOUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc_set_serirq_mode(SERIRQ_QUIET);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Interrupt configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_enable_ioapic(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_pch_pirq_init(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_i8259();</span><br><span style="color: hsl(120, 100%, 40%);">+ i8259_configure_irq_trigger(9, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_gate_8254(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_mirror_dmi_pcr_io_dec();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Fill up LPC IO resource structure inside SoC directory */</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_lpc_soc_fill_io_resources(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PMC pci device gets hidden from PCI bus due to Silicon</span><br><span style="color: hsl(120, 100%, 40%);">+ * policy hence bind ACPI BASE aka ABASE (offset 0x20) with</span><br><span style="color: hsl(120, 100%, 40%);">+ * LPC IO resources to ensure that ABASE falls under PCI reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * IO memory range.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Note: Don't add any more resource with same offset 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+ * under this device space.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO |</span><br><span style="color: hsl(120, 100%, 40%);">+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c</span><br><span>new file mode 100644</span><br><span>index 0000000..027b8b0</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/memmap.c</span><br><span>@@ -0,0 +1,312 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/ebda.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/ebda.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_region(void **start, size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *start = (void *)sa_get_tseg_base();</span><br><span style="color: hsl(120, 100%, 40%);">+ *size = sa_get_tseg_size();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Subregions within SMM</span><br><span style="color: hsl(120, 100%, 40%);">+ * +-------------------------+ BGSM</span><br><span style="color: hsl(120, 100%, 40%);">+ * | IED | IED_REGION_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ * +-------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | External Stage Cache | SMM_RESERVED_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ * +-------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | code and data |</span><br><span style="color: hsl(120, 100%, 40%);">+ * | (TSEG) |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +-------------------------+ TSEG</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int smm_subregion(int sub, void **start, size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t sub_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t sub_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *smm_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t ied_size = CONFIG_IED_REGION_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_region(&smm_base, &sub_size);</span><br><span style="color: hsl(120, 100%, 40%);">+ sub_base = (uintptr_t)smm_base;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (sub) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case SMM_SUBREGION_HANDLER:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Handler starts at the base of TSEG. */</span><br><span style="color: hsl(120, 100%, 40%);">+ sub_size -= ied_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ sub_size -= cache_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case SMM_SUBREGION_CACHE:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* External cache is in the middle of TSEG. */</span><br><span style="color: hsl(120, 100%, 40%);">+ sub_base += sub_size - (ied_size + cache_size);</span><br><span style="color: hsl(120, 100%, 40%);">+ sub_size = cache_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case SMM_SUBREGION_CHIPSET:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IED is at the top. */</span><br><span style="color: hsl(120, 100%, 40%);">+ sub_base += sub_size - ied_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ sub_size = ied_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ *start = (void *)sub_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ *size = sub_size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Calculate ME Stolen size */</span><br><span style="color: hsl(120, 100%, 40%);">+static size_t get_imr_size(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t imr_size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME stolen memory */</span><br><span style="color: hsl(120, 100%, 40%);">+ imr_size = MCHBAR32(IMRLIMIT) - MCHBAR32(IMRBASE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return imr_size;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Calculate PRMRR size based on user input PRMRR size and alignment */</span><br><span style="color: hsl(120, 100%, 40%);">+static size_t get_prmrr_size(uintptr_t dram_base,</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_intel_icelake_config *config)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t prmrr_base = dram_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t prmrr_size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ prmrr_size = config->PrmrrSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Allocate PRMRR memory for C6DRAM */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!prmrr_size) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->enable_c6dram)</span><br><span style="color: hsl(120, 100%, 40%);">+ prmrr_size = 1*MiB;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PRMRR Sizes that are > 1MB and < 32MB are</span><br><span style="color: hsl(120, 100%, 40%);">+ * not supported and will fail out.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB))</span><br><span style="color: hsl(120, 100%, 40%);">+ die("PRMRR Sizes that are > 1MB and < 32MB are not"</span><br><span style="color: hsl(120, 100%, 40%);">+ "supported!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ prmrr_base -= prmrr_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (prmrr_size >= 32*MiB)</span><br><span style="color: hsl(120, 100%, 40%);">+ prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ prmrr_base = ALIGN_DOWN(prmrr_base, 16*MiB);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PRMRR Area Size */</span><br><span style="color: hsl(120, 100%, 40%);">+ prmrr_size = dram_base - prmrr_base;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return prmrr_size;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */</span><br><span style="color: hsl(120, 100%, 40%);">+static size_t calculate_traditional_mem_size(uintptr_t dram_base,</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t traditional_mem_base = dram_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t traditional_mem_size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->enabled) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read BDSM from Host Bridge */</span><br><span style="color: hsl(120, 100%, 40%);">+ traditional_mem_base -= sa_get_dsm_size();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read BGSM from Host Bridge */</span><br><span style="color: hsl(120, 100%, 40%);">+ traditional_mem_base -= sa_get_gsm_size();</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get TSEG size */</span><br><span style="color: hsl(120, 100%, 40%);">+ traditional_mem_base -= sa_get_tseg_size();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get DPR size */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))</span><br><span style="color: hsl(120, 100%, 40%);">+ traditional_mem_base -= sa_get_dpr_size();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Traditional Area Size */</span><br><span style="color: hsl(120, 100%, 40%);">+ traditional_mem_size = dram_base - traditional_mem_base;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return traditional_mem_size;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Calculate Intel Reserved Memory size based on</span><br><span style="color: hsl(120, 100%, 40%);">+ * PRMRR size, Me stolen memory and PTT selection.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static size_t calculate_reserved_mem_size(uintptr_t dram_base,</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t reserve_mem_base = dram_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t reserve_mem_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_intel_icelake_config *config;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get PRMRR size */</span><br><span style="color: hsl(120, 100%, 40%);">+ reserve_mem_base -= get_prmrr_size(reserve_mem_base, config);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get Tracehub size */</span><br><span style="color: hsl(120, 100%, 40%);">+ reserve_mem_base -= get_imr_size();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Traditional Area Size */</span><br><span style="color: hsl(120, 100%, 40%);">+ reserve_mem_size = dram_base - reserve_mem_base;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return reserve_mem_size;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Host Memory Map:</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * +--------------------------+ TOUUD</span><br><span style="color: hsl(120, 100%, 40%);">+ * | |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +--------------------------+ 4GiB</span><br><span style="color: hsl(120, 100%, 40%);">+ * | PCI Address Space |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +--------------------------+ TOLUD (also maps into MC address space)</span><br><span style="color: hsl(120, 100%, 40%);">+ * | iGD |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +--------------------------+ BDSM</span><br><span style="color: hsl(120, 100%, 40%);">+ * | GTT |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +--------------------------+ BGSM</span><br><span style="color: hsl(120, 100%, 40%);">+ * | TSEG |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +--------------------------+ TSEGMB</span><br><span style="color: hsl(120, 100%, 40%);">+ * | DMA Protected Region |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +--------------------------+ DPR</span><br><span style="color: hsl(120, 100%, 40%);">+ * | PRM (C6DRAM/SGX) |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +--------------------------+ PRMRR</span><br><span style="color: hsl(120, 100%, 40%);">+ * | ME Stolen Memory |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +--------------------------+ ME Stolen</span><br><span style="color: hsl(120, 100%, 40%);">+ * | PTT |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +--------------------------+ top_of_ram</span><br><span style="color: hsl(120, 100%, 40%);">+ * | Reserved - FSP/CBMEM |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +--------------------------+ TOLUM</span><br><span style="color: hsl(120, 100%, 40%);">+ * | Usage DRAM |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +--------------------------+ 0</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Some of the base registers above can be equal making the size of those</span><br><span style="color: hsl(120, 100%, 40%);">+ * regions 0. The reason is because the memory controller internally subtracts</span><br><span style="color: hsl(120, 100%, 40%);">+ * the base registers from each other to determine sizes of the regions. In</span><br><span style="color: hsl(120, 100%, 40%);">+ * other words, the memory map is in a fixed order no matter what.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static uintptr_t calculate_dram_base(size_t *reserved_mem_size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t dram_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *dev;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev)</span><br><span style="color: hsl(120, 100%, 40%);">+ die("ERROR - IGD device not found!");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read TOLUD from Host Bridge offset */</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_base = sa_get_tolud_base();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get Intel Traditional Memory Range Size */</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_base -= calculate_traditional_mem_size(dram_base, dev);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get Intel Reserved Memory Range Size */</span><br><span style="color: hsl(120, 100%, 40%);">+ *reserved_mem_size = calculate_reserved_mem_size(dram_base, dev);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_base -= *reserved_mem_size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return dram_base;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SoC implementation</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * SoC call to summarize all Intel Reserve MMIO size and report to SA</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+size_t soc_reserved_mmio_size(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct ebda_config cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ retrieve_ebda_object(&cfg);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get Intel Reserved Memory Range Size */</span><br><span style="color: hsl(120, 100%, 40%);">+ return cfg.reserved_mem_size;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Fill up memory layout information */</span><br><span style="color: hsl(120, 100%, 40%);">+void fill_soc_memmap_ebda(struct ebda_config *cfg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t chipset_mem_size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->tolum_base = calculate_dram_base(&chipset_mem_size);</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->reserved_mem_size = chipset_mem_size;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void cbmem_top_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Fill up EBDA area */</span><br><span style="color: hsl(120, 100%, 40%);">+ fill_ebda_area();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * +-------------------------+ Top of RAM (aligned)</span><br><span style="color: hsl(120, 100%, 40%);">+ * | System Management Mode |</span><br><span style="color: hsl(120, 100%, 40%);">+ * | code and data | Length: CONFIG_TSEG_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ * | (TSEG) |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +-------------------------+ SMM base (aligned)</span><br><span style="color: hsl(120, 100%, 40%);">+ * | |</span><br><span style="color: hsl(120, 100%, 40%);">+ * | Chipset Reserved Memory |</span><br><span style="color: hsl(120, 100%, 40%);">+ * | |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +-------------------------+ top_of_ram (aligned)</span><br><span style="color: hsl(120, 100%, 40%);">+ * | |</span><br><span style="color: hsl(120, 100%, 40%);">+ * | CBMEM Root |</span><br><span style="color: hsl(120, 100%, 40%);">+ * | |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +-------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | |</span><br><span style="color: hsl(120, 100%, 40%);">+ * | FSP Reserved Memory |</span><br><span style="color: hsl(120, 100%, 40%);">+ * | |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +-------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | |</span><br><span style="color: hsl(120, 100%, 40%);">+ * | Various CBMEM Entries |</span><br><span style="color: hsl(120, 100%, 40%);">+ * | |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +-------------------------+ top_of_stack (8 byte aligned)</span><br><span style="color: hsl(120, 100%, 40%);">+ * | |</span><br><span style="color: hsl(120, 100%, 40%);">+ * | stack (CBMEM Entry) |</span><br><span style="color: hsl(120, 100%, 40%);">+ * | |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +-------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void *cbmem_top(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct ebda_config ebda_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Check if Tseg has been initialized, we will use this as a flag</span><br><span style="color: hsl(120, 100%, 40%);">+ * to check if the MRC is done, and only then continue to read the</span><br><span style="color: hsl(120, 100%, 40%);">+ * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before</span><br><span style="color: hsl(120, 100%, 40%);">+ * PRMRR_MASK MSR lock bit is set.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (sa_get_tseg_base() == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ retrieve_ebda_object(&ebda_cfg);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return (void *)(uintptr_t)ebda_cfg.tolum_base;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/p2sb.c b/src/soc/intel/icelake/p2sb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..6a7fac4</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/p2sb.c</span><br><span>@@ -0,0 +1,43 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/p2sb.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mask;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (count != P2SB_EP_MASK_MAX_REG) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "Unable to program EPMASK registers\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Remove the host accessing right to PSF register range.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband</span><br><span style="color: hsl(120, 100%, 40%);">+ * access for PCI Root Bridge.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ep_mask[P2SB_EP_MASK_5_REG] = mask;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband</span><br><span style="color: hsl(120, 100%, 40%);">+ * access for Broadcast and Multicast.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ mask = (1 << 31) | (1 << 30);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ep_mask[P2SB_EP_MASK_7_REG] = mask;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c</span><br><span>new file mode 100644</span><br><span>index 0000000..2453210</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/pmc.c</span><br><span>@@ -0,0 +1,160 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootstate.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ops.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pmc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pmclib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set which power state system will be after reapplying</span><br><span style="color: hsl(120, 100%, 40%);">+ * the power (from G3 State)</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static void pmc_set_afterg3(struct device *dev, int s5pwr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(dev, GEN_PMCON_B);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (s5pwr) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case MAINBOARD_POWER_STATE_OFF:</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 |= 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case MAINBOARD_POWER_STATE_ON:</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 &= ~1;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case MAINBOARD_POWER_STATE_PREVIOUS:</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, GEN_PMCON_B, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set PMC register to know which state system should be after</span><br><span style="color: hsl(120, 100%, 40%);">+ * power reapplied</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void pmc_soc_restore_power_failure(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_set_afterg3(PCH_DEV_PMC,</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_get_mainboard_power_failure_state_choice());</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *pmcbase = pmc_mmio_regs();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "%sabling Deep S%c\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ enable ? "En" : "Dis", sx + '0');</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = read32(pmcbase + offset);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (enable)</span><br><span style="color: hsl(120, 100%, 40%);">+ reg |= mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ reg &= ~mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pmcbase + offset, reg);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void config_deep_s5(int on_ac, int on_dc)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Treat S4 the same as S5. */</span><br><span style="color: hsl(120, 100%, 40%);">+ config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);</span><br><span style="color: hsl(120, 100%, 40%);">+ config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);</span><br><span style="color: hsl(120, 100%, 40%);">+ config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);</span><br><span style="color: hsl(120, 100%, 40%);">+ config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void config_deep_s3(int on_ac, int on_dc)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);</span><br><span style="color: hsl(120, 100%, 40%);">+ config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void config_deep_sx(uint32_t deepsx_config)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *pmcbase = pmc_mmio_regs();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = read32(pmcbase + DSX_CFG);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg &= ~DSX_CFG_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg |= deepsx_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pmcbase + DSX_CFG, reg);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_power_options(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *state;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get the chip configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ int pwr_on = pmc_get_mainboard_power_failure_state_choice();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Which state do we want to goto after g3 (power restored)?</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 == S5 Soft Off</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 == S0 Full On</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2 == Keep Previous State</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (pwr_on) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case MAINBOARD_POWER_STATE_OFF:</span><br><span style="color: hsl(120, 100%, 40%);">+ state = "off";</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case MAINBOARD_POWER_STATE_ON:</span><br><span style="color: hsl(120, 100%, 40%);">+ state = "on";</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case MAINBOARD_POWER_STATE_PREVIOUS:</span><br><span style="color: hsl(120, 100%, 40%);">+ state = "state keep";</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ state = "undefined";</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_set_afterg3(dev, pwr_on);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "Set power %s after power failure.\n", state);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set up GPE configuration. */</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_gpe_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pmc_init(void *unused)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = PCH_DEV_PMC;</span><br><span style="color: hsl(120, 100%, 40%);">+ config_t *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rtc_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize power management */</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_power_options(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_set_acpi_mode();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);</span><br><span style="color: hsl(120, 100%, 40%);">+ config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);</span><br><span style="color: hsl(120, 100%, 40%);">+ config_deep_sx(config->deep_sx_config);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+* Initialize PMC controller.</span><br><span style="color: hsl(120, 100%, 40%);">+*</span><br><span style="color: hsl(120, 100%, 40%);">+* PMC controller gets hidden from PCI bus during FSP-Silicon init call.</span><br><span style="color: hsl(120, 100%, 40%);">+* Hence PCI enumeration can't be used to initialize bus device and</span><br><span style="color: hsl(120, 100%, 40%);">+* allocate resources.</span><br><span style="color: hsl(120, 100%, 40%);">+*/</span><br><span style="color: hsl(120, 100%, 40%);">+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL);</span><br><span>diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c</span><br><span>new file mode 100644</span><br><span>index 0000000..c020bf6</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/pmutil.c</span><br><span>@@ -0,0 +1,231 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Helper functions for dealing with power management registers</span><br><span style="color: hsl(120, 100%, 40%);">+ * and the differences between PCH variants.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pmclib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <halt.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <rules.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpe.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/lpc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smbus.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vbnv.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "chip.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SMI</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const char *const *soc_smi_sts_array(size_t *a)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const smi_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ [BIOS_STS_BIT] = "BIOS",</span><br><span style="color: hsl(120, 100%, 40%);">+ [LEGACY_USB_STS_BIT] = "LEGACY_USB",</span><br><span style="color: hsl(120, 100%, 40%);">+ [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",</span><br><span style="color: hsl(120, 100%, 40%);">+ [APM_STS_BIT] = "APM",</span><br><span style="color: hsl(120, 100%, 40%);">+ [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",</span><br><span style="color: hsl(120, 100%, 40%);">+ [PM1_STS_BIT] = "PM1",</span><br><span style="color: hsl(120, 100%, 40%);">+ [GPE0_STS_BIT] = "GPE0",</span><br><span style="color: hsl(120, 100%, 40%);">+ [GPIO_STS_BIT] = "GPI",</span><br><span style="color: hsl(120, 100%, 40%);">+ [MCSMI_STS_BIT] = "MCSMI",</span><br><span style="color: hsl(120, 100%, 40%);">+ [DEVMON_STS_BIT] = "DEVMON",</span><br><span style="color: hsl(120, 100%, 40%);">+ [TCO_STS_BIT] = "TCO",</span><br><span style="color: hsl(120, 100%, 40%);">+ [PERIODIC_STS_BIT] = "PERIODIC",</span><br><span style="color: hsl(120, 100%, 40%);">+ [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",</span><br><span style="color: hsl(120, 100%, 40%);">+ [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",</span><br><span style="color: hsl(120, 100%, 40%);">+ [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",</span><br><span style="color: hsl(120, 100%, 40%);">+ [MONITOR_STS_BIT] = "MONITOR",</span><br><span style="color: hsl(120, 100%, 40%);">+ [SPI_SMI_STS_BIT] = "SPI",</span><br><span style="color: hsl(120, 100%, 40%);">+ [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",</span><br><span style="color: hsl(120, 100%, 40%);">+ [ESPI_SMI_STS_BIT] = "ESPI_SMI",</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ *a = ARRAY_SIZE(smi_sts_bits);</span><br><span style="color: hsl(120, 100%, 40%);">+ return smi_sts_bits;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * TCO</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const char *const *soc_tco_sts_array(size_t *a)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const tco_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ [0] = "NMI2SMI",</span><br><span style="color: hsl(120, 100%, 40%);">+ [1] = "SW_TCO",</span><br><span style="color: hsl(120, 100%, 40%);">+ [2] = "TCO_INT",</span><br><span style="color: hsl(120, 100%, 40%);">+ [3] = "TIMEOUT",</span><br><span style="color: hsl(120, 100%, 40%);">+ [7] = "NEWCENTURY",</span><br><span style="color: hsl(120, 100%, 40%);">+ [8] = "BIOSWR",</span><br><span style="color: hsl(120, 100%, 40%);">+ [9] = "DMISCI",</span><br><span style="color: hsl(120, 100%, 40%);">+ [10] = "DMISMI",</span><br><span style="color: hsl(120, 100%, 40%);">+ [12] = "DMISERR",</span><br><span style="color: hsl(120, 100%, 40%);">+ [13] = "SLVSEL",</span><br><span style="color: hsl(120, 100%, 40%);">+ [16] = "INTRD_DET",</span><br><span style="color: hsl(120, 100%, 40%);">+ [17] = "SECOND_TO",</span><br><span style="color: hsl(120, 100%, 40%);">+ [18] = "BOOT",</span><br><span style="color: hsl(120, 100%, 40%);">+ [20] = "SMLINK_SLV"</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ *a = ARRAY_SIZE(tco_sts_bits);</span><br><span style="color: hsl(120, 100%, 40%);">+ return tco_sts_bits;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * GPE0</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const char *const *soc_std_gpe_sts_array(size_t *a)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const gpe_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ [1] = "HOTPLUG",</span><br><span style="color: hsl(120, 100%, 40%);">+ [2] = "SWGPE",</span><br><span style="color: hsl(120, 100%, 40%);">+ [6] = "TCO_SCI",</span><br><span style="color: hsl(120, 100%, 40%);">+ [7] = "SMB_WAK",</span><br><span style="color: hsl(120, 100%, 40%);">+ [9] = "PCI_EXP",</span><br><span style="color: hsl(120, 100%, 40%);">+ [10] = "BATLOW",</span><br><span style="color: hsl(120, 100%, 40%);">+ [11] = "PME",</span><br><span style="color: hsl(120, 100%, 40%);">+ [12] = "ME",</span><br><span style="color: hsl(120, 100%, 40%);">+ [13] = "PME_B0",</span><br><span style="color: hsl(120, 100%, 40%);">+ [14] = "eSPI",</span><br><span style="color: hsl(120, 100%, 40%);">+ [15] = "GPIO Tier-2",</span><br><span style="color: hsl(120, 100%, 40%);">+ [16] = "LAN_WAKE",</span><br><span style="color: hsl(120, 100%, 40%);">+ [18] = "WADT"</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ *a = ARRAY_SIZE(gpe_sts_bits);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpe_sts_bits;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void pmc_set_disb(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the DISB after DRAM init */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t disb_val;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Only care about bits [23:16] of register GEN_PMCON_A */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *addr = (void *)(pmc_mmio_regs() + GEN_PMCON_A + 2);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ disb_val = read8(addr);</span><br><span style="color: hsl(120, 100%, 40%);">+ disb_val |= (DISB >> 16);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Don't clear bits that are write-1-to-clear */</span><br><span style="color: hsl(120, 100%, 40%);">+ disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(addr, disb_val);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PMC controller gets hidden from PCI bus</span><br><span style="color: hsl(120, 100%, 40%);">+ * during FSP-Silicon init call. Hence PWRMBASE</span><br><span style="color: hsl(120, 100%, 40%);">+ * can't be accessible using PCI configuration space</span><br><span style="color: hsl(120, 100%, 40%);">+ * read/write.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+uint8_t *pmc_mmio_regs(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint16_t smbus_tco_regs(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t reg16;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return ALIGN_DOWN(reg16, 0x20);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t soc_reset_tco_status(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 tco1_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 tco2_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 tcobase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tcobase = smbus_tco_regs();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TCO Status 2 register */</span><br><span style="color: hsl(120, 100%, 40%);">+ tco2_sts = inw(tcobase + TCO2_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ tco2_sts |= TCO2_STS_SECOND_TO;</span><br><span style="color: hsl(120, 100%, 40%);">+ outw(tco2_sts, tcobase + TCO2_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TCO Status 1 register */</span><br><span style="color: hsl(120, 100%, 40%);">+ tco1_sts = inw(tcobase + TCO1_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear SECOND_TO_STS bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (tco2_sts & TCO2_STS_SECOND_TO)</span><br><span style="color: hsl(120, 100%, 40%);">+ outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return (tco2_sts << 16) | tco1_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t soc_read_pmc_base(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return (uintptr_t)pmc_mmio_regs();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ DEVTREE_CONST struct soc_intel_icelake_config *config;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Look up the device in devicetree */</span><br><span style="color: hsl(120, 100%, 40%);">+ DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev || !dev->chip_info) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Assign to out variable */</span><br><span style="color: hsl(120, 100%, 40%);">+ *dw0 = config->gpe0_dw0;</span><br><span style="color: hsl(120, 100%, 40%);">+ *dw1 = config->gpe0_dw1;</span><br><span style="color: hsl(120, 100%, 40%);">+ *dw2 = config->gpe0_dw2;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int rtc_failed(uint32_t gen_pmcon_b)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(gen_pmcon_b & RTC_BATTERY_DEAD);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int soc_get_rtc_failed(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!ps) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return rtc_failed(ps->gen_pmcon_b);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vbnv_cmos_failed(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c</span><br><span>new file mode 100755</span><br><span>index 0000000..745233a</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/reset.c</span><br><span>@@ -0,0 +1,103 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/cse.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pmclib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Reset Request */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MKHI_GLOBAL_RESET 0x0b</span><br><span style="color: hsl(120, 100%, 40%);">+#define MKHI_STATUS_SUCCESS 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GR_ORIGIN_BIOS_MEM_INIT 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define GR_ORIGIN_BIOS_POST 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+#define GR_ORIGIN_MEBX 0x03</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GLOBAL_RST_TYPE 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIOS_HOST_ADD 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define HECI_MKHI_ADD 0x07</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int send_heci_reset_message(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int status;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct reset_reply {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 group_id;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 command;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reserved;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 result;</span><br><span style="color: hsl(120, 100%, 40%);">+ } __packed reply;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct reset_message {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 group_id;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 cmd;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reserved;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 result;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 req_origin;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reset_type;</span><br><span style="color: hsl(120, 100%, 40%);">+ } __packed;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct reset_message msg = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .cmd = MKHI_GLOBAL_RESET,</span><br><span style="color: hsl(120, 100%, 40%);">+ .req_origin = GR_ORIGIN_BIOS_POST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset_type = GLOBAL_RST_TYPE</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t reply_size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ heci_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADD, HECI_MKHI_ADD);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status != 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reply_size = sizeof(reply);</span><br><span style="color: hsl(120, 100%, 40%);">+ memset(&reply, 0, reply_size);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!heci_receive(&reply, &reply_size))</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (reply.result != MKHI_STATUS_SUCCESS) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Returned Mkhi Status is not success!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Heci receive success!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void do_global_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ask CSE to do the global reset */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!send_heci_reset_message())</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* global reset if CSE fail to reset */</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_global_reset_enable(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void chipset_handle_reset(uint32_t status)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (status) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "GLOBAL RESET!!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ do_global_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "unhandled reset type %x\n", status);</span><br><span style="color: hsl(120, 100%, 40%);">+ die("unknown reset type");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/romstage/Makefile.inc b/src/soc/intel/icelake/romstage/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..9fc199d</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/romstage/Makefile.inc</span><br><span>@@ -0,0 +1,19 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2018 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += fsp_params.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += power_state.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += romstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += systemagent.c</span><br><span>diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c</span><br><span>new file mode 100644</span><br><span>index 0000000..69b5b7a</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/romstage/fsp_params.c</span><br><span>@@ -0,0 +1,28 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ToDo: update with UPD override as FSP matures */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__weak void mainboard_memory_init_params(FSPM_UPD *mupd)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/romstage/power_state.c b/src/soc/intel/icelake/romstage/power_state.c</span><br><span>new file mode 100644</span><br><span>index 0000000..3b6d5f2</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/romstage/power_state.c</span><br><span>@@ -0,0 +1,91 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/early_variables.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pmclib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int deep_s3_enabled(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t deep_s3_pol;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Return 0, 3, or 5 to indicate the previous sleep state. */</span><br><span style="color: hsl(120, 100%, 40%);">+int soc_prev_sleep_state(const struct chipset_power_state *ps,</span><br><span style="color: hsl(120, 100%, 40%);">+ int prev_sleep_state)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Check for any power failure to determine if this a wake from</span><br><span style="color: hsl(120, 100%, 40%);">+ * S5 because the PCH does not set the WAK_STS bit when waking</span><br><span style="color: hsl(120, 100%, 40%);">+ * from a true G3 state.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))</span><br><span style="color: hsl(120, 100%, 40%);">+ prev_sleep_state = ACPI_S5;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * If waking from S3 determine if deep S3 is enabled. If not,</span><br><span style="color: hsl(120, 100%, 40%);">+ * need to check both deep sleep well and normal suspend well.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Otherwise just check deep sleep well.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (prev_sleep_state == ACPI_S3) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PWR_FLR represents deep sleep power well loss. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mask = PWR_FLR;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* If deep s3 isn't enabled check the suspend well too. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!deep_s3_enabled())</span><br><span style="color: hsl(120, 100%, 40%);">+ mask |= SUS_PWR_FLR;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ps->gen_pmcon_b & mask)</span><br><span style="color: hsl(120, 100%, 40%);">+ prev_sleep_state = ACPI_S5;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return prev_sleep_state;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_fill_power_state(struct chipset_power_state *ps)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tcobase;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *pmc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tcobase = smbus_tco_regs();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->tco1_sts = inw(tcobase + TCO1_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->tco2_sts = inw(tcobase + TCO2_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->tco1_sts, ps->tco2_sts);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc = pmc_mmio_regs();</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->gen_pmcon_a, ps->gen_pmcon_b);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->gblrst_cause[0], ps->gblrst_cause[1]);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c</span><br><span>new file mode 100755</span><br><span>index 0000000..432cae5</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/romstage/romstage.c</span><br><span>@@ -0,0 +1,148 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/early_variables.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/cse.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pmclib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <memory_info.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/common/smbios.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct chipset_power_state power_state CAR_GLOBAL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define FSP_SMBIOS_MEMORY_INFO_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+{ \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Save the DIMM information for SMBIOS table 17 */</span><br><span style="color: hsl(120, 100%, 40%);">+static void save_dimm_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int channel, dimm, dimm_max, index;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t hob_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ const CONTROLLER_INFO *ctrlr_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ const CHANNEL_INFO *channel_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ const DIMM_INFO *src_dimm;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dimm_info *dest_dimm;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct memory_info *mem_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ const MEMORY_INFO_DATA_HOB *memory_info_hob;</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint8_t smbios_memory_info_guid[16] =</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_SMBIOS_MEMORY_INFO_GUID;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Locate the memory info HOB, presence validated by raminit */</span><br><span style="color: hsl(120, 100%, 40%);">+ memory_info_hob = fsp_find_extension_hob_by_guid(</span><br><span style="color: hsl(120, 100%, 40%);">+ smbios_memory_info_guid,</span><br><span style="color: hsl(120, 100%, 40%);">+ &hob_size);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (memory_info_hob == NULL || hob_size == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Allocate CBMEM area for DIMM information used to populate SMBIOS</span><br><span style="color: hsl(120, 100%, 40%);">+ * table 17</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (mem_info == NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ memset(mem_info, 0, sizeof(*mem_info));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Describe the first N DIMMs in the system */</span><br><span style="color: hsl(120, 100%, 40%);">+ index = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dimm_max = ARRAY_SIZE(mem_info->dimm);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlr_info = &memory_info_hob->Controller[0];</span><br><span style="color: hsl(120, 100%, 40%);">+ for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ channel_info = &ctrlr_info->ChannelInfo[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+ if (channel_info->Status != CHANNEL_PRESENT)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ src_dimm = &channel_info->DimmInfo[dimm];</span><br><span style="color: hsl(120, 100%, 40%);">+ dest_dimm = &mem_info->dimm[index];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (src_dimm->Status != DIMM_PRESENT)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Populate the DIMM information */</span><br><span style="color: hsl(120, 100%, 40%);">+ dimm_info_fill(dest_dimm,</span><br><span style="color: hsl(120, 100%, 40%);">+ src_dimm->DimmCapacity,</span><br><span style="color: hsl(120, 100%, 40%);">+ memory_info_hob->MemoryType,</span><br><span style="color: hsl(120, 100%, 40%);">+ memory_info_hob->ConfiguredMemoryClockSpeed,</span><br><span style="color: hsl(120, 100%, 40%);">+ channel_info->ChannelId,</span><br><span style="color: hsl(120, 100%, 40%);">+ src_dimm->DimmId,</span><br><span style="color: hsl(120, 100%, 40%);">+ (const char *)src_dimm->ModulePartNum,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(src_dimm->ModulePartNum),</span><br><span style="color: hsl(120, 100%, 40%);">+ memory_info_hob->DataWidth);</span><br><span style="color: hsl(120, 100%, 40%);">+ index++;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_info->dimm_cnt = index;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+asmlinkage void car_stage_entry(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ bool s3wake;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct postcar_frame pcf;</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t top_of_ram;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct chipset_power_state *ps = car_get_var_ptr(&power_state);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */</span><br><span style="color: hsl(120, 100%, 40%);">+ systemagent_early_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* initialize Heci interface */</span><br><span style="color: hsl(120, 100%, 40%);">+ heci_init(HECI1_BASE_ADDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_START_ROMSTAGE);</span><br><span style="color: hsl(120, 100%, 40%);">+ s3wake = pmc_fill_power_state(ps) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+ fsp_memory_init(s3wake);</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_set_disb();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!s3wake)</span><br><span style="color: hsl(120, 100%, 40%);">+ save_dimm_info();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (postcar_frame_init(&pcf, 1 * KiB))</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Unable to initialize postcar frame.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * We need to make sure ramstage will be run cached. At this</span><br><span style="color: hsl(120, 100%, 40%);">+ * point exact location of ramstage in cbmem is not known.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Instruct postcar to cache 16 megs under cbmem top which is</span><br><span style="color: hsl(120, 100%, 40%);">+ * a safe bet to cover ramstage.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ top_of_ram = (uintptr_t) cbmem_top();</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);</span><br><span style="color: hsl(120, 100%, 40%);">+ top_of_ram -= 16*MiB;</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ run_postcar_phase(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/romstage/systemagent.c b/src/soc/intel/icelake/romstage/systemagent.c</span><br><span>new file mode 100644</span><br><span>index 0000000..fc046a6</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/romstage/systemagent.c</span><br><span>@@ -0,0 +1,43 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void systemagent_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Fixed MMIO address into PCI configuration space */</span><br><span style="color: hsl(120, 100%, 40%);">+ sa_set_pci_bar(soc_fixed_pci_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ ARRAY_SIZE(soc_fixed_pci_resources));</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Fixed MMIO address into MCH base address */</span><br><span style="color: hsl(120, 100%, 40%);">+ sa_set_mch_bar(soc_fixed_mch_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ ARRAY_SIZE(soc_fixed_mch_resources));</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable PAM registers */</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_pam_region();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/sd.c b/src/soc/intel/icelake/sd.c</span><br><span>new file mode 100644</span><br><span>index 0000000..c3565c8</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/sd.c</span><br><span>@@ -0,0 +1,37 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/sd.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "chip.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ config_t *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!config->sdcard_cd_gpio)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio->type = ACPI_GPIO_TYPE_INTERRUPT;</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio->pull = ACPI_GPIO_PULL_NONE;</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED;</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH;</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio->irq.shared = ACPI_IRQ_SHARED;</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio->irq.wake = ACPI_IRQ_WAKE;</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio->interrupt_debounce_timeout = 10000; /* 100ms */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio->pin_count = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio->pins[0] = config->sdcard_cd_gpio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c</span><br><span>new file mode 100644</span><br><span>index 0000000..aa4a1cc</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/smihandler.c</span><br><span>@@ -0,0 +1,133 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/fast_spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/p2sb.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/smihandler.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/p2sb.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSME0_FBE 0xf</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSME0_BAR 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSME0_FID 0xb0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct smm_save_state_ops *get_smm_save_state_ops(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return &em64t101_smm_ops;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_disable_heci(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct pcr_sbi_msg msg = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .pid = PID_CSME0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .offset = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .opcode = PCR_WRITE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .is_posted = false,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fast_byte_enable = CSME0_FBE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bar = CSME0_BAR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fid = CSME0_FID</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bit 0: Set to make HECI#1 Function disable */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t data32 = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t response;</span><br><span style="color: hsl(120, 100%, 40%);">+ int status;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* unhide p2sb device */</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb_unhide();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Send SBI command to make HECI#1 function disable */</span><br><span style="color: hsl(120, 100%, 40%);">+ status = pcr_execute_sideband_msg(&msg, &data32, &response);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status && response)</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "Fail to make CSME function disable\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure to Lock SBI interface after this command */</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb_disable_sideband_access();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* hide p2sb device */</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb_hide();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Specific SOC SMI handler during ramstage finalize phase</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * BIOS can't make CSME function disable as is due to POSTBOOT_SAI</span><br><span style="color: hsl(120, 100%, 40%);">+ * restriction in place from ICP chipset. Hence create SMI Handler to</span><br><span style="color: hsl(120, 100%, 40%);">+ * perform CSME function disabling logic during SMM mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void smihandler_soc_at_finalize(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_intel_icelake_config *config;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev || !dev->chip_info) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ return ;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->HeciEnabled == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_disable_heci();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void smihandler_soc_check_illegal_access(uint32_t tco_sts)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM)</span><br><span style="color: hsl(120, 100%, 40%);">+ && fast_spi_wpd_status()))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * BWE is RW, so the SMI was caused by a</span><br><span style="color: hsl(120, 100%, 40%);">+ * write to BWE, not by a write to the BIOS</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This is the place where we notice someone</span><br><span style="color: hsl(120, 100%, 40%);">+ * is trying to tinker with the BIOS. We are</span><br><span style="color: hsl(120, 100%, 40%);">+ * trying to be nice and just ignore it. A more</span><br><span style="color: hsl(120, 100%, 40%);">+ * resolute answer would be to power down the</span><br><span style="color: hsl(120, 100%, 40%);">+ * box.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Switching back to RO\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ fast_spi_enable_wp();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMI handlers that should be serviced in SCI mode too. */</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t smihandler_soc_get_sci_mask(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t sci_mask =</span><br><span style="color: hsl(120, 100%, 40%);">+ SMI_HANDLER_SCI_EN(APM_STS_BIT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return sci_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const smi_handler_t southbridge_smi[SMI_STS_BITS] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,</span><br><span style="color: hsl(120, 100%, 40%);">+ [APM_STS_BIT] = smihandler_southbridge_apmc,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PM1_STS_BIT] = smihandler_southbridge_pm1,</span><br><span style="color: hsl(120, 100%, 40%);">+ [GPE0_STS_BIT] = smihandler_southbridge_gpe0,</span><br><span style="color: hsl(120, 100%, 40%);">+ [GPIO_STS_BIT] = smihandler_southbridge_gpi,</span><br><span style="color: hsl(120, 100%, 40%);">+ [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,</span><br><span style="color: hsl(120, 100%, 40%);">+ [MCSMI_STS_BIT] = smihandler_southbridge_mc,</span><br><span style="color: hsl(120, 100%, 40%);">+ [TCO_STS_BIT] = smihandler_southbridge_tco,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PERIODIC_STS_BIT] = smihandler_southbridge_periodic,</span><br><span style="color: hsl(120, 100%, 40%);">+ [MONITOR_STS_BIT] = smihandler_southbridge_monitor,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c</span><br><span>new file mode 100644</span><br><span>index 0000000..57a366a</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/smmrelocate.c</span><br><span>@@ -0,0 +1,309 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/lapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "chip.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* This gets filled in and used during relocation. */</span><br><span style="color: hsl(120, 100%, 40%);">+static struct smm_relocation_params smm_reloc_params;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void write_smrr(struct smm_relocation_params *relo_params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ relo_params->smrr_base.lo, relo_params->smrr_mask.lo);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void update_save_state(int cpu, uintptr_t curr_smbase,</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t staggered_smbase,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct smm_relocation_params *relo_params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 iedbase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The relocated handler runs with all CPUs concurrently. Therefore</span><br><span style="color: hsl(120, 100%, 40%);">+ * stagger the entry points adjusting SMBASE downwards by save state</span><br><span style="color: hsl(120, 100%, 40%);">+ * size * CPU num.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ smbase = staggered_smbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ iedbase = relo_params->ied_base;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ smbase, iedbase);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * All threads need to set IEDBASE and SMBASE to the relocated</span><br><span style="color: hsl(120, 100%, 40%);">+ * handler region. However, the save state location depends on the</span><br><span style="color: hsl(120, 100%, 40%);">+ * smm_save_state_in_msrs field in the relocation parameters. If</span><br><span style="color: hsl(120, 100%, 40%);">+ * smm_save_state_in_msrs is non-zero then the CPUs are relocating</span><br><span style="color: hsl(120, 100%, 40%);">+ * the SMM handler in parallel, and each CPUs save state area is</span><br><span style="color: hsl(120, 100%, 40%);">+ * located in their respective MSR space. If smm_save_state_in_msrs</span><br><span style="color: hsl(120, 100%, 40%);">+ * is zero then the SMM relocation is happening serially so the</span><br><span style="color: hsl(120, 100%, 40%);">+ * save state is at the same default location for all CPUs.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (relo_params->smm_save_state_in_msrs) {</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t smbase_msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t iedbase_msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ smbase_msr.lo = smbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ smbase_msr.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * According the BWG the IEDBASE MSR is in bits 63:32. It's</span><br><span style="color: hsl(120, 100%, 40%);">+ * not clear why it differs from the SMBASE MSR.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ iedbase_msr.lo = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ iedbase_msr.hi = iedbase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(SMBASE_MSR, smbase_msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IEDBASE_MSR, iedbase_msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ em64t101_smm_state_save_area_t *save_state;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(*save_state));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ save_state->smbase = smbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ save_state->iedbase = iedbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Returns 1 if SMM MSR save state was set. */</span><br><span style="color: hsl(120, 100%, 40%);">+static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t smm_mca_cap;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t smm_feature_control;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR);</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_feature_control.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_feature_control.lo |= SMM_CPU_SAVE_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);</span><br><span style="color: hsl(120, 100%, 40%);">+ relo_params->smm_save_state_in_msrs = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return relo_params->smm_save_state_in_msrs;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The relocation work is actually performed in SMM context, but the code</span><br><span style="color: hsl(120, 100%, 40%);">+ * resides in the ramstage module. This occurs by trampolining from the default</span><br><span style="color: hsl(120, 100%, 40%);">+ * SMRAM entry point to here.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_relocation_handler(int cpu, uintptr_t curr_smbase,</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t staggered_smbase)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t mtrr_cap;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct smm_relocation_params *relo_params = &smm_reloc_params;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Determine if the processor supports saving state in MSRs. If so,</span><br><span style="color: hsl(120, 100%, 40%);">+ * enable it before the non-BSPs run so that SMM relocation can occur</span><br><span style="color: hsl(120, 100%, 40%);">+ * in parallel in the non-BSP CPUs.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cpu == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * If smm_save_state_in_msrs is 1 then that means this is the</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2nd time through the relocation handler for the BSP.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Parallel SMM handler relocation is taking place. However,</span><br><span style="color: hsl(120, 100%, 40%);">+ * it is desired to access other CPUs save state in the real</span><br><span style="color: hsl(120, 100%, 40%);">+ * SMM handler. Therefore, disable the SMM save state in MSRs</span><br><span style="color: hsl(120, 100%, 40%);">+ * feature.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (relo_params->smm_save_state_in_msrs) {</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t smm_feature_control;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR);</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_feature_control.lo &= ~SMM_CPU_SAVE_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (bsp_setup_msr_save_state(relo_params))</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Just return from relocation handler if MSR save</span><br><span style="color: hsl(120, 100%, 40%);">+ * state is enabled. In that case the BSP will come</span><br><span style="color: hsl(120, 100%, 40%);">+ * back into the relocation handler to setup the new</span><br><span style="color: hsl(120, 100%, 40%);">+ * SMBASE as well disabling SMM save state in MSRs.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Make appropriate changes to the save state map. */</span><br><span style="color: hsl(120, 100%, 40%);">+ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Write EMRR and SMRR MSRs based on indicated support. */</span><br><span style="color: hsl(120, 100%, 40%);">+ mtrr_cap = rdmsr(MTRR_CAP_MSR);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (mtrr_cap.lo & SMRR_SUPPORTED)</span><br><span style="color: hsl(120, 100%, 40%);">+ write_smrr(relo_params);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void fill_in_relocation_params(struct device *dev,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct smm_relocation_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ void *handler_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t handler_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *ied_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t ied_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *tseg_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t tseg_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 emrr_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 emrr_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ int phys_bits;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* All range registers are aligned to 4KiB */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 rmask = ~(4 * KiB - 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Some of the range registers are dependent on the number of physical</span><br><span style="color: hsl(120, 100%, 40%);">+ * address bits supported.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ phys_bits = cpu_phys_address_size();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_region(&tseg_base, &tseg_size);</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ params->smram_size = handler_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->smram_base = (uintptr_t)handler_base;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ied_base = (uintptr_t)ied_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ied_size = ied_size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SMRR has 32-bits of valid address aligned to 4KiB. */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->smrr_base.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->smrr_mask.lo = (~(tseg_size - 1) & rmask)</span><br><span style="color: hsl(120, 100%, 40%);">+ | MTRR_PHYS_MASK_VALID;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->smrr_mask.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */</span><br><span style="color: hsl(120, 100%, 40%);">+ emrr_base = (params->ied_base + 2 * MiB) & rmask;</span><br><span style="color: hsl(120, 100%, 40%);">+ emrr_size = params->ied_size - 2 * MiB;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * EMRR has 46 bits of valid address aligned to 4KiB. It's dependent</span><br><span style="color: hsl(120, 100%, 40%);">+ * on the number of physical address bits supported.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->emrr_base.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->emrr_mask.lo = (~(emrr_size - 1) & rmask)</span><br><span style="color: hsl(120, 100%, 40%);">+ | MTRR_PHYS_MASK_VALID;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->uncore_emrr_base.lo = emrr_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->uncore_emrr_base.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |</span><br><span style="color: hsl(120, 100%, 40%);">+ MTRR_PHYS_MASK_VALID;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void setup_ied_area(struct smm_relocation_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ char *ied_base;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ struct ied_header ied = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .signature = "INTEL RSVD",</span><br><span style="color: hsl(120, 100%, 40%);">+ .size = params->ied_size,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reserved = {0},</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ied_base = (void *)params->ied_base;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Place IED header at IEDBASE. */</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(ied_base, &ied, sizeof(ied));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Zero out 32KiB at IEDBASE + 1MiB */</span><br><span style="color: hsl(120, 100%, 40%);">+ memset(ied_base + 1 * MiB, 0, 32 * KiB);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t *smm_save_state_size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Setting up SMI for CPU\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fill_in_relocation_params(dev, &smm_reloc_params);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (smm_reloc_params.ied_size)</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_ied_area(&smm_reloc_params);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ *perm_smbase = smm_reloc_params.smram_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ *perm_smsize = smm_reloc_params.smram_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_initialize(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear the SMM state in the southbridge. */</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_southbridge_clear_state();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Run the relocation handler for on the BSP to check and set up</span><br><span style="color: hsl(120, 100%, 40%);">+ * parallel SMM relocation.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_initiate_relocation();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (smm_reloc_params.smm_save_state_in_msrs)</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_relocate(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * If smm_save_state_in_msrs is non-zero then parallel SMM relocation</span><br><span style="color: hsl(120, 100%, 40%);">+ * shall take place. Run the relocation handler a second time on the</span><br><span style="color: hsl(120, 100%, 40%);">+ * BSP to do * the final move. For APs, a relocation handler always</span><br><span style="color: hsl(120, 100%, 40%);">+ * needs to be run.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (smm_reloc_params.smm_save_state_in_msrs)</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_initiate_relocation_parallel();</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (!boot_cpu())</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_initiate_relocation();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_lock(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * LOCK the SMM memory window and enable normal SMM.</span><br><span style="color: hsl(120, 100%, 40%);">+ * After running this function, only a full reset can</span><br><span style="color: hsl(120, 100%, 40%);">+ * make the SMM registers writable again.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Locking SMM.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/spi.c b/src/soc/intel/icelake/spi.c</span><br><span>new file mode 100644</span><br><span>index 0000000..8e4f089</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/spi.c</span><br><span>@@ -0,0 +1,33 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int spi_soc_devfn_to_bus(unsigned int devfn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (devfn) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_SPI:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_GSPI0:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_GSPI1:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_GSPI2:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c</span><br><span>new file mode 100644</span><br><span>index 0000000..7903667</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/systemagent.c</span><br><span>@@ -0,0 +1,68 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SoC implementation</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Add all known fixed memory ranges for Host Controller/Memory</span><br><span style="color: hsl(120, 100%, 40%);">+ * controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_add_fixed_mmio_resources(struct device *dev, int *index)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static const struct sa_mmio_descriptor soc_fixed_resources[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ "PCIEXBAR" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PMC pci device gets hidden from PCI bus due to Silicon</span><br><span style="color: hsl(120, 100%, 40%);">+ * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with</span><br><span style="color: hsl(120, 100%, 40%);">+ * SA resources to ensure that PMCBAR falls under PCI reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * memory range.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Note: Don't add any more resource with same offset 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+ * under this device space.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ "PMCBAR" },</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ ARRAY_SIZE(soc_fixed_resources));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SoC implementation</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Perform System Agent Initialization during Ramstage phase.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_systemagent_init(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable Power Aware Interrupt Routing */</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_power_aware_intr();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable BIOS Reset CPL */</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_bios_reset_cpl();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c</span><br><span>new file mode 100755</span><br><span>index 0000000..d03d21e</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/icelake/uart.c</span><br><span>@@ -0,0 +1,86 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2018 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/lpss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/uart.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Serial IO UART controller legacy mode */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_SERIAL_IO_GPPRVRW7 0x618</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct uart_gpio_pad_config uart_gpio_pads[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .console_index = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpios = {</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .console_index = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpios = {</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .console_index = 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpios = {</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_uart_set_legacy_mode(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Dummy read after setting any of GPPRVRW7.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Required for UART 16550 8-bit Legacy mode to become active</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct device *soc_uart_console_to_device(int uart_console)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * if index is valid, this function will return corresponding structure</span><br><span style="color: hsl(120, 100%, 40%);">+ * for uart console else will return NULL.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (uart_console) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0:</span><br><span style="color: hsl(120, 100%, 40%);">+ return (struct device *)PCH_DEV_UART0;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1:</span><br><span style="color: hsl(120, 100%, 40%);">+ return (struct device *)PCH_DEV_UART1;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2:</span><br><span style="color: hsl(120, 100%, 40%);">+ return (struct device *)PCH_DEV_UART2;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "Invalid UART console index\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29162">change 29162</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29162"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I756fa7275c4190aebc0695f14484498aaf5662a5 </div>
<div style="display:none"> Gerrit-Change-Number: 29162 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>