<p><a href="https://review.coreboot.org/29065">View Change</a></p><p>8 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29065/18/src/cpu/amd/family_10h-family_15h/defaults.h">File src/cpu/amd/family_10h-family_15h/defaults.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29065/18/src/cpu/amd/family_10h-family_15h/defaults.h@77">Patch Set #18, Line 77:</a> <code style="font-family:monospace,monospace">  { NB_CFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC,</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29065/18/src/cpu/amd/family_10h-family_15h/defaults.h@107">Patch Set #18, Line 107:</a> <code style="font-family:monospace,monospace">   1 << 21, 0x00000000 },  /* Erratum #254 DR B1 BU_CFG_MSR[21]=1 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29065/18/src/cpu/amd/family_10h-family_15h/defaults.h@118">Patch Set #18, Line 118:</a> <code style="font-family:monospace,monospace">   { CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC,</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29065/18/src/include/cpu/amd/msr.h">File src/include/cpu/amd/msr.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29065/18/src/include/cpu/amd/msr.h@40">Patch Set #18, Line 40:</a> <code style="font-family:monospace,monospace">#define PS_CTL_REG                       0xC0010062 /* P-state Control Register */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29065/18/src/include/cpu/amd/msr.h@41">Patch Set #18, Line 41:</a> <code style="font-family:monospace,monospace">#define  PS_CMD_MASK_OFF                0xfffffff8 /* P-state Control Register CMD Mask OFF */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29065/18/src/include/cpu/amd/msr.h@43">Patch Set #18, Line 43:</a> <code style="font-family:monospace,monospace">#define PS_MAX_REG                 0xC0010068 /* Maximum P-State Register */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29065/18/src/include/cpu/amd/msr.h@44">Patch Set #18, Line 44:</a> <code style="font-family:monospace,monospace">#define PS_MIN_REG                      0xC0010064 /* Mimimum P-State Register */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/29065/18/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c">File src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/29065/18/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c@672">Patch Set #18, Line 672:</a> <code style="font-family:monospace,monospace"> wrmsr(HWCR_MSR, msr);   /* Setting wrap32dis allows 64-bit memory references in real mode */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/29065">change 29065</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29065"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
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<div style="display:none"> Gerrit-Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 </div>
<div style="display:none"> Gerrit-Change-Number: 29065 </div>
<div style="display:none"> Gerrit-PatchSet: 18 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-CC: Marc Jones <marc@marcjonesconsulting.com> </div>
<div style="display:none"> Gerrit-Comment-Date: Wed, 17 Oct 2018 07:12:24 +0000 </div>
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