<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29173">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">{cpu,drivers}/amd: Replace MSR addresses with macros<br><br>Change-Id: I315c0b70c552c5dd7f640b18b913350bb88be81b<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/amd/agesa/family12/fixme.c<br>M src/cpu/amd/agesa/family14/fixme.c<br>M src/cpu/amd/agesa/family14/model_14_init.c<br>M src/cpu/amd/agesa/family15tn/fixme.c<br>M src/cpu/amd/agesa/family15tn/model_15_init.c<br>M src/cpu/amd/agesa/family16kb/fixme.c<br>M src/cpu/amd/agesa/family16kb/model_16_init.c<br>M src/cpu/amd/pi/00630F01/fixme.c<br>M src/cpu/amd/pi/00630F01/model_15_init.c<br>M src/cpu/amd/pi/00660F01/fixme.c<br>M src/cpu/amd/pi/00660F01/model_15_init.c<br>M src/cpu/amd/pi/00730F01/fixme.c<br>M src/cpu/amd/pi/00730F01/model_16_init.c<br>M src/drivers/amd/agesa/s3_mtrr.c<br>14 files changed, 37 insertions(+), 37 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29173/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c</span><br><span>index 084cae8..e97a819 100644</span><br><span>--- a/src/cpu/amd/agesa/family12/fixme.c</span><br><span>+++ b/src/cpu/amd/agesa/family12/fixme.c</span><br><span>@@ -98,7 +98,7 @@</span><br><span> </span><br><span> /* Set ROM cache onto WP to decrease post time */</span><br><span> MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);</span><br><span> MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);</span><br><span> }</span><br><span>diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c</span><br><span>index 33e1643..978c25f 100644</span><br><span>--- a/src/cpu/amd/agesa/family14/fixme.c</span><br><span>+++ b/src/cpu/amd/agesa/family14/fixme.c</span><br><span>@@ -90,9 +90,9 @@</span><br><span> </span><br><span> /* Set ROM cache onto WP to decrease post time */</span><br><span> MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);</span><br><span> MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);</span><br><span> </span><br><span> /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */</span><br><span> MsrReg = 0;</span><br><span>diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c</span><br><span>index 3f0501e..34eaa27 100644</span><br><span>--- a/src/cpu/amd/agesa/family14/model_14_init.c</span><br><span>+++ b/src/cpu/amd/agesa/family14/model_14_init.c</span><br><span>@@ -55,10 +55,10 @@</span><br><span> </span><br><span> /* Set shadow WB, RdMEM, WrMEM */</span><br><span> msr.lo = msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr (0x259, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_A0000, msr);</span><br><span> msr.lo = msr.hi = 0x1e1e1e1e;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x250, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x258, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_64K_00000, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_80000, msr);</span><br><span> for (msrno = 0x268; msrno <= 0x26f; msrno++)</span><br><span> wrmsr(msrno, msr);</span><br><span> </span><br><span>diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c</span><br><span>index 847f753..7e493f9 100644</span><br><span>--- a/src/cpu/amd/agesa/family15tn/fixme.c</span><br><span>+++ b/src/cpu/amd/agesa/family15tn/fixme.c</span><br><span>@@ -76,7 +76,7 @@</span><br><span> </span><br><span> /* Set ROM cache onto WP to decrease post time */</span><br><span> MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);</span><br><span> MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);</span><br><span> }</span><br><span>diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c</span><br><span>index d188bcc..82596dc 100644</span><br><span>--- a/src/cpu/amd/agesa/family15tn/model_15_init.c</span><br><span>+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c</span><br><span>@@ -54,12 +54,12 @@</span><br><span> </span><br><span> // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs</span><br><span> msr.lo = msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr (0x259, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_A0000, msr);</span><br><span> msr.lo = msr.hi = 0x1e1e1e1e;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x250, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x258, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_64K_00000, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_80000, msr);</span><br><span> for (msrno = 0x268; msrno <= 0x26f; msrno++)</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr (msrno, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(msrno, msr);</span><br><span> </span><br><span> msr = rdmsr(SYSCFG_MSR);</span><br><span> msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;</span><br><span>diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c</span><br><span>index 1f22307..c761d6d 100644</span><br><span>--- a/src/cpu/amd/agesa/family16kb/fixme.c</span><br><span>+++ b/src/cpu/amd/agesa/family16kb/fixme.c</span><br><span>@@ -76,7 +76,7 @@</span><br><span> </span><br><span> /* Set ROM cache onto WP to decrease post time */</span><br><span> MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);</span><br><span> MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);</span><br><span> }</span><br><span>diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c</span><br><span>index 286bcc3..3219d8d 100644</span><br><span>--- a/src/cpu/amd/agesa/family16kb/model_16_init.c</span><br><span>+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c</span><br><span>@@ -52,12 +52,12 @@</span><br><span> </span><br><span> // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs</span><br><span> msr.lo = msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr (0x259, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_A0000, msr);</span><br><span> msr.lo = msr.hi = 0x1e1e1e1e;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x250, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x258, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_64K_00000, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_80000, msr);</span><br><span> for (msrno = 0x268; msrno <= 0x26f; msrno++)</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr (msrno, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(msrno, msr);</span><br><span> </span><br><span> msr = rdmsr(SYSCFG_MSR);</span><br><span> msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;</span><br><span>diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c</span><br><span>index 4feb188..11cab62 100644</span><br><span>--- a/src/cpu/amd/pi/00630F01/fixme.c</span><br><span>+++ b/src/cpu/amd/pi/00630F01/fixme.c</span><br><span>@@ -83,9 +83,9 @@</span><br><span> </span><br><span> /* Set ROM cache onto WP to decrease post time */</span><br><span> MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);</span><br><span> MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);</span><br><span> </span><br><span> if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){</span><br><span> LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);</span><br><span>diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c</span><br><span>index 503d531..e05e1fc 100644</span><br><span>--- a/src/cpu/amd/pi/00630F01/model_15_init.c</span><br><span>+++ b/src/cpu/amd/pi/00630F01/model_15_init.c</span><br><span>@@ -54,10 +54,10 @@</span><br><span> * same as OntarioApMtrrSettingsList for APs</span><br><span> */</span><br><span> msr.lo = msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x259, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_A0000, msr);</span><br><span> msr.lo = msr.hi = 0x1e1e1e1e;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x250, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x258, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_64K_00000, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_80000, msr);</span><br><span> for (msrno = 0x268; msrno <= 0x26f; msrno++)</span><br><span> wrmsr(msrno, msr);</span><br><span> </span><br><span>diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c</span><br><span>index 0bad467..ee8728d 100644</span><br><span>--- a/src/cpu/amd/pi/00660F01/fixme.c</span><br><span>+++ b/src/cpu/amd/pi/00660F01/fixme.c</span><br><span>@@ -89,9 +89,9 @@</span><br><span> </span><br><span> /* Set ROM cache onto WP to decrease post time */</span><br><span> MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);</span><br><span> MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);</span><br><span> </span><br><span> if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {</span><br><span> LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);</span><br><span>diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c</span><br><span>index 3f3a1fd..b0a8951 100644</span><br><span>--- a/src/cpu/amd/pi/00660F01/model_15_init.c</span><br><span>+++ b/src/cpu/amd/pi/00660F01/model_15_init.c</span><br><span>@@ -66,10 +66,10 @@</span><br><span> </span><br><span> // BSP: make a0000-bffff UC, c0000-fffff WB</span><br><span> msr.lo = msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x259, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_A0000, msr);</span><br><span> msr.lo = msr.hi = 0x1e1e1e1e;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x250, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x258, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_64K_00000, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_80000, msr);</span><br><span> for (msrno = 0x268; msrno <= 0x26f; msrno++)</span><br><span> wrmsr(msrno, msr);</span><br><span> </span><br><span>diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c</span><br><span>index 9f4c528..4350572 100644</span><br><span>--- a/src/cpu/amd/pi/00730F01/fixme.c</span><br><span>+++ b/src/cpu/amd/pi/00730F01/fixme.c</span><br><span>@@ -94,9 +94,9 @@</span><br><span> </span><br><span> /* Set ROM cache onto WP to decrease post time */</span><br><span> MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);</span><br><span> MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);</span><br><span> </span><br><span> if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {</span><br><span> LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);</span><br><span>diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c</span><br><span>index f5121d1..7d76239 100644</span><br><span>--- a/src/cpu/amd/pi/00730F01/model_16_init.c</span><br><span>+++ b/src/cpu/amd/pi/00730F01/model_16_init.c</span><br><span>@@ -51,10 +51,10 @@</span><br><span> * same as OntarioApMtrrSettingsList for APs</span><br><span> */</span><br><span> msr.lo = msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x259, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_A0000, msr);</span><br><span> msr.lo = msr.hi = 0x1e1e1e1e;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x250, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x258, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_64K_00000, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_80000, msr);</span><br><span> for (msrno = 0x268; msrno <= 0x26f; msrno++)</span><br><span> wrmsr(msrno, msr);</span><br><span> </span><br><span>diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c</span><br><span>index c039abe..20e87c99 100644</span><br><span>--- a/src/drivers/amd/agesa/s3_mtrr.c</span><br><span>+++ b/src/drivers/amd/agesa/s3_mtrr.c</span><br><span>@@ -89,19 +89,19 @@</span><br><span> msrPtr ++;</span><br><span> msr_data.hi = *msrPtr;</span><br><span> msrPtr ++;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x250, msr_data);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_64K_00000, msr_data);</span><br><span> </span><br><span> msr_data.lo = *msrPtr;</span><br><span> msrPtr ++;</span><br><span> msr_data.hi = *msrPtr;</span><br><span> msrPtr ++;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x258, msr_data);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_80000, msr_data);</span><br><span> </span><br><span> msr_data.lo = *msrPtr;</span><br><span> msrPtr ++;</span><br><span> msr_data.hi = *msrPtr;</span><br><span> msrPtr ++;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x259, msr_data);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MTRR_FIX_16K_A0000, msr_data);</span><br><span> </span><br><span> for (msr = 0x268; msr <= 0x26F; msr++) {</span><br><span> msr_data.lo = *msrPtr;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29173">change 29173</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29173"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I315c0b70c552c5dd7f640b18b913350bb88be81b </div>
<div style="display:none"> Gerrit-Change-Number: 29173 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>