<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29161">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Remove unneeded whitespace before and after parenthesis<br><br>Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/commonlib/storage/storage_write.c<br>M src/cpu/amd/family_10h-family_15h/fidvid.c<br>M src/cpu/via/nano/nano_init.c<br>M src/cpu/via/nano/update_ucode.c<br>M src/device/device.c<br>M src/device/hypertransport.c<br>M src/drivers/emulation/qemu/bochs.c<br>M src/drivers/intel/fsp1_0/hob.c<br>M src/drivers/intel/fsp2_0/hand_off_block.c<br>M src/drivers/intel/fsp2_0/hob_display.c<br>M src/drivers/intel/gma/edid.c<br>M src/drivers/intel/wifi/wifi.c<br>M src/drivers/net/ne2k.c<br>M src/drivers/smmstore/store.c<br>M src/drivers/spi/flashconsole.c<br>M src/lib/edid.c<br>M src/lib/stack.c<br>M src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c<br>M src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c<br>M src/mainboard/amd/serengeti_cheetah_fam10/mptable.c<br>M src/mainboard/amd/torpedo/gpio.c<br>M src/mainboard/asus/am1i-a/BiosCallOuts.c<br>M src/mainboard/asus/m4a785-m/mainboard.c<br>M src/mainboard/biostar/am1ml/romstage.c<br>M src/mainboard/esd/atom15/romstage.c<br>M src/mainboard/gigabyte/ma785gmt/mainboard.c<br>M src/mainboard/gizmosphere/gizmo/OemCustomize.c<br>M src/mainboard/google/gru/boardid.c<br>M src/mainboard/google/link/i915.c<br>M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c<br>M src/mainboard/intel/bayleybay_fsp/romstage.c<br>M src/mainboard/lenovo/g505s/buildOpts.c<br>M src/mainboard/lenovo/t60/smihandler.c<br>M src/mainboard/lenovo/z61t/smihandler.c<br>M src/mainboard/lippert/frontrunner-af/mainboard.c<br>M src/mainboard/lippert/toucan-af/mainboard.c<br>M src/mainboard/msi/ms9652_fam10/get_bus_conf.c<br>M src/mainboard/pcengines/alix1c/romstage.c<br>M src/mainboard/pcengines/alix2d/romstage.c<br>M src/mainboard/pcengines/apu1/OemCustomize.c<br>M src/mainboard/pcengines/apu1/gpio_ftns.c<br>M src/mainboard/pcengines/apu2/BiosCallOuts.c<br>M src/mainboard/pcengines/apu2/mainboard.c<br>M src/mainboard/siemens/mc_tcu3/romstage.c<br>M src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c<br>M src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c<br>M src/mainboard/tyan/s2912_fam10/get_bus_conf.c<br>M src/northbridge/amd/agesa/family12/dimmSpd.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c<br>M src/northbridge/amd/pi/00730F01/dimmSpd.c<br>M src/northbridge/intel/e7505/debug.c<br>M src/northbridge/intel/fsp_rangeley/northbridge.c<br>M src/northbridge/intel/pineview/raminit.c<br>M src/northbridge/via/vx900/chrome9hd.c<br>M src/soc/broadcom/cygnus/ddr_init.c<br>M src/soc/broadcom/cygnus/phy_reg_access.c<br>M src/soc/intel/baytrail/perf_power.c<br>M src/soc/intel/braswell/chip.c<br>M src/soc/intel/braswell/cpu.c<br>M src/soc/intel/braswell/emmc.c<br>M src/soc/intel/braswell/gfx.c<br>M src/soc/intel/braswell/lpe.c<br>M src/soc/intel/braswell/lpss.c<br>M src/soc/intel/braswell/pcie.c<br>M src/soc/intel/braswell/sata.c<br>M src/soc/intel/braswell/scc.c<br>M src/soc/intel/braswell/sd.c<br>M src/soc/intel/braswell/southcluster.c<br>M src/soc/intel/fsp_baytrail/bootblock/bootblock.c<br>M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c<br>M src/soc/intel/fsp_baytrail/northcluster.c<br>M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c<br>M src/soc/nvidia/tegra124/sdram_lp0.c<br>M src/soc/nvidia/tegra210/sdram_lp0.c<br>M src/soc/samsung/exynos5250/clock.c<br>M src/soc/samsung/exynos5420/clock.c<br>M src/southbridge/amd/agesa/hudson/sm.c<br>M src/southbridge/amd/amd8111/early_ctrl.c<br>M src/southbridge/amd/amd8132/bridge.c<br>M src/southbridge/amd/cimx/sb800/fan.c<br>M src/southbridge/amd/rs780/early_setup.c<br>M src/southbridge/amd/rs780/gfx.c<br>M src/southbridge/amd/sb700/sata.c<br>M src/southbridge/amd/sb800/sata.c<br>M src/southbridge/amd/sb800/sm.c<br>M src/southbridge/amd/sr5650/pcie.c<br>M src/southbridge/intel/i82371eb/smbus.c<br>M src/southbridge/ricoh/rl5c476/rl5c476.c<br>M src/superio/serverengines/pilot/early_init.c<br>M src/superio/smsc/sch4037/sch4037_early_init.c<br>90 files changed, 305 insertions(+), 305 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/29161/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/commonlib/storage/storage_write.c b/src/commonlib/storage/storage_write.c</span><br><span>index ba60b41..aef8624 100644</span><br><span>--- a/src/commonlib/storage/storage_write.c</span><br><span>+++ b/src/commonlib/storage/storage_write.c</span><br><span>@@ -130,7 +130,7 @@</span><br><span>     uint32_t *buffer = malloc(buffer_bytes);</span><br><span>     uint32_t *ptr = buffer;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-     for ( ; buffer_words ; buffer_words--)</span><br><span style="color: hsl(120, 100%, 40%);">+        for (; buffer_words ; buffer_words--)</span><br><span>                *ptr++ = fill_pattern;</span><br><span> </span><br><span>   uint64_t todo = count;</span><br><span>diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c</span><br><span>index 0882ae5..476ef37 100644</span><br><span>--- a/src/cpu/amd/family_10h-family_15h/fidvid.c</span><br><span>+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c</span><br><span>@@ -54,7 +54,7 @@</span><br><span> </span><br><span> 7.- TODO (Core Performance Boost is only available in revision E cpus, and we</span><br><span>           don't seem to support those yet, at least they don't have any</span><br><span style="color: hsl(0, 100%, 40%);">-   constant in amddefs.h )</span><br><span style="color: hsl(120, 100%, 40%);">+       constant in amddefs.h)</span><br><span> </span><br><span> 8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required</span><br><span>     by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required</span><br><span>@@ -144,7 +144,7 @@</span><br><span>       // BKDG 2.4.2.8</span><br><span>      // Fam10h revision E only, but E is apparently not supported yet, therefore untested</span><br><span>         if ((cpuid_edx(0x80000007) & CPB_MASK)</span><br><span style="color: hsl(0, 100%, 40%);">-              &&  ((cpuid_ecx(0x80000008) & NC_MASK) == 5) ) {</span><br><span style="color: hsl(120, 100%, 40%);">+          &&  ((cpuid_ecx(0x80000008) & NC_MASK) == 5)) {</span><br><span>          u32 core =  get_node_core_id_x().coreid;</span><br><span>             u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3;</span><br><span>            msr_t msr =  rdmsr(PSTATE_0_MSR);</span><br><span>@@ -170,15 +170,15 @@</span><br><span>    uint64_t cpuRev =  mctGetLogicalCPUID(0xFF);</span><br><span>         if (cpuRev & AMD_FAM10_C3) {</span><br><span>             u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK);</span><br><span style="color: hsl(0, 100%, 40%);">-            if ( nbPState){</span><br><span style="color: hsl(120, 100%, 40%);">+               if (nbPState){</span><br><span>                       u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT;</span><br><span>                      u32 i;</span><br><span>                       for (i = nbPState; i < NM_PS_REG; i++) {</span><br><span>                          msr_t msr =  rdmsr(PSTATE_0_MSR + i);</span><br><span style="color: hsl(0, 100%, 40%);">-                           if (msr.hi &  PS_EN_MASK ) {</span><br><span style="color: hsl(120, 100%, 40%);">+                              if (msr.hi &  PS_EN_MASK) {</span><br><span>                              msr.hi |= NB_DID_M_ON;</span><br><span>                               msr.lo &= NB_VID_MASK_OFF;</span><br><span style="color: hsl(0, 100%, 40%);">-                          msr.lo |= ( nbVid1 << NB_VID_POS);</span><br><span style="color: hsl(120, 100%, 40%);">+                              msr.lo |= (nbVid1 << NB_VID_POS);</span><br><span>                              wrmsr(PSTATE_0_MSR + i, msr);</span><br><span>                                }</span><br><span>                    }</span><br><span>@@ -281,7 +281,7 @@</span><br><span>       * voltages instead of a hardcoded 200us.</span><br><span>     * Note: his function is called only from prep_fid_change,</span><br><span>    * and that from init_cpus.c finalize_node_setup()</span><br><span style="color: hsl(0, 100%, 40%);">-       * (after set AMD MSRs and init ht )</span><br><span style="color: hsl(120, 100%, 40%);">+   * (after set AMD MSRs and init ht)</span><br><span>   */</span><br><span> </span><br><span>      /* BKDG r31116 2010-04-22  2.4.1.7 step b F3xD8[VSSlamTime] */</span><br><span>@@ -381,7 +381,7 @@</span><br><span>         uint8_t link0isGen3 = 0;</span><br><span>     uint8_t offset;</span><br><span>      if (AMD_CpuFindCapability(node, 0, &offset)) {</span><br><span style="color: hsl(0, 100%, 40%);">-        link0isGen3 = (AMD_checkLinkType(node, offset) & HTPHY_LINKTYPE_HT3 );</span><br><span style="color: hsl(120, 100%, 40%);">+    link0isGen3 = (AMD_checkLinkType(node, offset) & HTPHY_LINKTYPE_HT3);</span><br><span>  }</span><br><span>    /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package</span><br><span>     S1g3 in link Gen3 mode, but I don't know how to tell</span><br><span>@@ -412,7 +412,7 @@</span><br><span>            uint32_t dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1;</span><br><span>             uint32_t isocEn = 0;</span><br><span>                 int j;</span><br><span style="color: hsl(0, 100%, 40%);">-          for (j=0; (j<4) && (!isocEn); j++ ) {</span><br><span style="color: hsl(120, 100%, 40%);">+              for (j=0; (j<4) && (!isocEn); j++) {</span><br><span>                      u8 offset;</span><br><span>                   if (AMD_CpuFindCapability(node, j, &offset)) {</span><br><span>                           isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1;</span><br><span>@@ -495,12 +495,12 @@</span><br><span>  }</span><br><span>    /* set the rest of A0 since we're at it... */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-   if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) {</span><br><span style="color: hsl(120, 100%, 40%);">+  if (cpuRev & (AMD_DA_Cx | AMD_RB_C3)) {</span><br><span>          dword |= NB_PSTATE_FORCE_ON;</span><br><span>         } // else should we clear it ?</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-  if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) {</span><br><span style="color: hsl(120, 100%, 40%);">+  if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32)) {</span><br><span>          dword |= BP_INS_TRI_EN_ON;</span><br><span>   }</span><br><span> </span><br><span>@@ -522,7 +522,7 @@</span><br><span>     values (min latency) */</span><br><span>   uint32_t nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK;</span><br><span>       uint8_t nbSynPtrAdj;</span><br><span style="color: hsl(0, 100%, 40%);">-    if ((cpuRev & (AMD_DR_Bx | AMD_DA_Cx | AMD_FAM15_ALL) )</span><br><span style="color: hsl(120, 100%, 40%);">+   if ((cpuRev & (AMD_DR_Bx | AMD_DA_Cx | AMD_FAM15_ALL))</span><br><span>           || ((cpuRev & AMD_RB_C3) && (nbPstate != 0))) {</span><br><span>          nbSynPtrAdj = 5;</span><br><span>     } else {</span><br><span>@@ -555,8 +555,8 @@</span><br><span>                       // or should we configure for what we'll set up later ?</span><br><span>                  dword = pci_read_config32(dev, 0x58);</span><br><span>                        uint32_t scrubbingCache = dword &</span><br><span style="color: hsl(0, 100%, 40%);">-                                           ( (0x1F << 16) // DCacheScrub</span><br><span style="color: hsl(0, 100%, 40%);">-                                             | (0x1F << 8) ); // L2Scrub</span><br><span style="color: hsl(120, 100%, 40%);">+                                             ((0x1F << 16) // DCacheScrub</span><br><span style="color: hsl(120, 100%, 40%);">+                                            | (0x1F << 8)); // L2Scrub</span><br><span>                     if (scrubbingCache) {</span><br><span>                                c1 = 0x80;</span><br><span>                   } else {</span><br><span>@@ -582,7 +582,7 @@</span><br><span>               */</span><br><span> </span><br><span>               uint32_t smaf001 = 0xE6;</span><br><span style="color: hsl(0, 100%, 40%);">-                if (cpuRev & AMD_DR_Bx ) {</span><br><span style="color: hsl(120, 100%, 40%);">+                if (cpuRev & AMD_DR_Bx) {</span><br><span>                        smaf001 = 0xA6;</span><br><span>              } else {</span><br><span>             #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ)</span><br><span>@@ -593,7 +593,7 @@</span><br><span>           }</span><br><span>            uint32_t fidvidChange = 0;</span><br><span>           if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX))</span><br><span style="color: hsl(0, 100%, 40%);">-                      || (cpuRev & AMD_RB_C3) ) {</span><br><span style="color: hsl(120, 100%, 40%);">+                       || (cpuRev & AMD_RB_C3)) {</span><br><span>                               fidvidChange=0x0B;</span><br><span>           }</span><br><span>            dword = (0xE6 << 24) | (fidvidChange << 16)</span><br><span>@@ -657,13 +657,13 @@</span><br><span>      * misunderstand this...</span><br><span>      */</span><br><span>   u32 corrected_timeout = ((pstate_msr.lo==1)</span><br><span style="color: hsl(0, 100%, 40%);">-                             && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ?</span><br><span style="color: hsl(120, 100%, 40%);">+                            && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON))) ?</span><br><span>                            WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT;</span><br><span>         msr_t timeout;</span><br><span> </span><br><span>   timeout.lo = initial_msr.lo + corrected_timeout;</span><br><span>     timeout.hi = initial_msr.hi;</span><br><span style="color: hsl(0, 100%, 40%);">-    if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) {</span><br><span style="color: hsl(120, 100%, 40%);">+  if ((((u32)0xffffffff) - initial_msr.lo) < corrected_timeout) {</span><br><span>           timeout.hi++;</span><br><span>        }</span><br><span> </span><br><span>@@ -672,8 +672,8 @@</span><br><span>          pstate_msr = rdmsr(CUR_PSTATE_MSR);</span><br><span>          tsc_msr = rdmsr(TSC_MSR);</span><br><span>            timedout = (tsc_msr.hi > timeout.hi)</span><br><span style="color: hsl(0, 100%, 40%);">-                 || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo ));</span><br><span style="color: hsl(0, 100%, 40%);">-       } while ( (pstate_msr.lo != target_pstate) && (! timedout) );</span><br><span style="color: hsl(120, 100%, 40%);">+                 || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo));</span><br><span style="color: hsl(120, 100%, 40%);">+      } while ((pstate_msr.lo != target_pstate) && (! timedout));</span><br><span> </span><br><span>      if (pstate_msr.lo != target_pstate) {</span><br><span>                msr_t limit_msr = rdmsr(0xc0010061);</span><br><span>@@ -682,7 +682,7 @@</span><br><span> </span><br><span>               do { // should we just go on instead ?</span><br><span>                       pstate_msr = rdmsr(CUR_PSTATE_MSR);</span><br><span style="color: hsl(0, 100%, 40%);">-             } while ( pstate_msr.lo != target_pstate  );</span><br><span style="color: hsl(120, 100%, 40%);">+          } while (pstate_msr.lo != target_pstate );</span><br><span>   }</span><br><span> }</span><br><span> </span><br><span>@@ -765,7 +765,7 @@</span><br><span>     wrmsr(PSTATE_0_MSR, msr);</span><br><span> </span><br><span>        /* missing step 2 from BDKG , F3xDC[PstateMaxVal] =</span><br><span style="color: hsl(0, 100%, 40%);">-      * max(1,F3xDC[PstateMaxVal] ) because it would take</span><br><span style="color: hsl(120, 100%, 40%);">+   * max(1,F3xDC[PstateMaxVal]) because it would take</span><br><span>   * synchronization between cores and we don't think</span><br><span>       * PstatMaxVal is going to be 0 on cold reset anyway ?</span><br><span>        */</span><br><span>@@ -839,12 +839,12 @@</span><br><span>  reg1fc = pci_read_config32(dev, 0x1FC);</span><br><span> </span><br><span>  if (nb_cof_vid_update) {</span><br><span style="color: hsl(0, 100%, 40%);">-                vid_max = (reg1fc &  SINGLE_PLANE_NB_VID_MASK ) >>  SINGLE_PLANE_NB_VID_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">-                fid_max = (reg1fc &  SINGLE_PLANE_NB_FID_MASK ) >>  SINGLE_PLANE_NB_FID_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+              vid_max = (reg1fc &  SINGLE_PLANE_NB_VID_MASK) >>  SINGLE_PLANE_NB_VID_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+               fid_max = (reg1fc &  SINGLE_PLANE_NB_FID_MASK) >>  SINGLE_PLANE_NB_FID_SHIFT;</span><br><span> </span><br><span>          if (!pvimode) { /* SVI, dual power plane */</span><br><span style="color: hsl(0, 100%, 40%);">-                     vid_max = vid_max - ((reg1fc &  DUAL_PLANE_NB_VID_OFF_MASK ) >>  DUAL_PLANE_NB_VID_SHIFT );</span><br><span style="color: hsl(0, 100%, 40%);">-                   fid_max = fid_max +  ((reg1fc &  DUAL_PLANE_NB_FID_OFF_MASK ) >>  DUAL_PLANE_NB_FID_SHIFT );</span><br><span style="color: hsl(120, 100%, 40%);">+                        vid_max = vid_max - ((reg1fc &  DUAL_PLANE_NB_VID_OFF_MASK) >>  DUAL_PLANE_NB_VID_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+                   fid_max = fid_max +  ((reg1fc &  DUAL_PLANE_NB_FID_OFF_MASK) >>  DUAL_PLANE_NB_FID_SHIFT);</span><br><span>                 }</span><br><span>            /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */</span><br><span>          fixPsNbVidBeforeWR(vid_max, coreid, dev, pvimode);</span><br><span>@@ -948,7 +948,7 @@</span><br><span>     for (i = 0; i < 5; i++) {</span><br><span>                 msr = rdmsr(PSTATE_0_MSR + i);</span><br><span>               /*  NbDid (bit 22 of P-state Reg) == 0  or NbVidUpdatedAll = 1 */</span><br><span style="color: hsl(0, 100%, 40%);">-               if (   (msr.hi & PS_IDD_VALUE_MASK)</span><br><span style="color: hsl(120, 100%, 40%);">+               if (  (msr.hi & PS_IDD_VALUE_MASK)</span><br><span>                   && (msr.hi & PS_EN_MASK)</span><br><span>                 &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) {</span><br><span>                   msr.lo &= PS_NB_VID_M_OFF;</span><br><span>diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c</span><br><span>index 985a3c7..2e9d0e2 100644</span><br><span>--- a/src/cpu/via/nano/nano_init.c</span><br><span>+++ b/src/cpu/via/nano/nano_init.c</span><br><span>@@ -71,7 +71,7 @@</span><br><span>      printk(BIOS_INFO, "Voltage ID    : %dx (min %dx; max %dx)\n",</span><br><span>             cur_vid, min_vid, max_vid);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-  if ( (cur_fid != max_fid) || (cur_vid != max_vid) ) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((cur_fid != max_fid) || (cur_vid != max_vid)) {</span><br><span>          /* Set highest frequency and VID */</span><br><span>          msr.lo = msr.hi;</span><br><span>             msr.hi = 0;</span><br><span>@@ -101,7 +101,7 @@</span><br><span>     * This MSR is not documented by VIA docs, other than setting these</span><br><span>   * bits */</span><br><span>   msr = rdmsr(NANO_MYSTERIOUS_MSR);</span><br><span style="color: hsl(0, 100%, 40%);">-       msr.lo |= ( (1 << 7) | (1 << 4) );</span><br><span style="color: hsl(120, 100%, 40%);">+        msr.lo |= ((1 << 7) | (1 << 4));</span><br><span>         /* FIXME: Do we have a 6-bit or 7-bit VRM?</span><br><span>    * set bit [5] for 7-bit, or don't set it for 6 bit VRM</span><br><span>   * This will probably require a Kconfig option</span><br><span>@@ -114,15 +114,15 @@</span><br><span> </span><br><span>   /* Enable TM3 */</span><br><span>     msr = rdmsr(IA32_MISC_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">-  msr.lo |= ( (1 << 3) | (1 << 13) );</span><br><span style="color: hsl(120, 100%, 40%);">+       msr.lo |= ((1 << 3) | (1 << 13));</span><br><span>        wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-       u8 stepping = ( cpuid_eax(0x1) ) &0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+    u8 stepping = (cpuid_eax(0x1)) &0xf;</span><br><span>     if (stepping >= MODEL_NANO_3000_B0) {</span><br><span>             /* Hello Nano 3000. The Terminator needs a CPU upgrade */</span><br><span>            /* Enable C1e, C2e, C3e, and C4e states */</span><br><span>           msr = rdmsr(IA32_MISC_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">-          msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */</span><br><span style="color: hsl(120, 100%, 40%);">+         msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */</span><br><span>                 msr.hi |= (1 << 0); /* C4e */</span><br><span>          wrmsr(IA32_MISC_ENABLE, msr);</span><br><span>        }</span><br><span>diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c</span><br><span>index b8bfd7d..efabac6 100644</span><br><span>--- a/src/cpu/via/nano/update_ucode.c</span><br><span>+++ b/src/cpu/via/nano/update_ucode.c</span><br><span>@@ -43,9 +43,9 @@</span><br><span> static void nano_print_ucode_info(const nano_ucode_header *ucode)</span><br><span> {</span><br><span>     printk(BIOS_SPEW, "Microcode update information:\n");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "Name: %8s\n", ucode->name );</span><br><span style="color: hsl(120, 100%, 40%);">+  printk(BIOS_SPEW, "Name: %8s\n", ucode->name);</span><br><span>  printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month,</span><br><span style="color: hsl(0, 100%, 40%);">-               ucode->day, ucode->year );</span><br><span style="color: hsl(120, 100%, 40%);">+              ucode->day, ucode->year);</span><br><span> }</span><br><span> </span><br><span> static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)</span><br><span>@@ -54,7 +54,7 @@</span><br><span>     if (ucode->signature != NANO_UCODE_SIGNATURE)</span><br><span>             return NANO_UCODE_SIGNATURE_ERROR;</span><br><span>   /* The size of the head must be exactly 12 double words */</span><br><span style="color: hsl(0, 100%, 40%);">-      if ( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)</span><br><span style="color: hsl(120, 100%, 40%);">+       if ((ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)</span><br><span>               return NANO_UCODE_WRONG_SIZE;</span><br><span> </span><br><span>    /* How about a checksum ? Checksum must be 0</span><br><span>@@ -119,7 +119,7 @@</span><br><span>   /* We might do a lot of loops searching for the microcode updates, but</span><br><span>        * keep in mind, nano_ucode_is_valid searches for the signature before</span><br><span>        * doing anything else. */</span><br><span style="color: hsl(0, 100%, 40%);">-      for ( i = 0; i < (ucode_len >> 2); /* don't increment i here */ )</span><br><span style="color: hsl(120, 100%, 40%);">+        for (i = 0; i < (ucode_len >> 2); /* don't increment i here */)</span><br><span>         {</span><br><span>            ucode_update_status stat;</span><br><span>            const nano_ucode_header * ucode = (void *)(&ucode_data[i]);</span><br><span>diff --git a/src/device/device.c b/src/device/device.c</span><br><span>index dcbaef1..7836af1 100644</span><br><span>--- a/src/device/device.c</span><br><span>+++ b/src/device/device.c</span><br><span>@@ -123,7 +123,7 @@</span><br><span>       struct device *dev, *child;</span><br><span> </span><br><span>      /* Find the last child of our parent. */</span><br><span style="color: hsl(0, 100%, 40%);">-        for (child = parent->children; child && child->sibling; /* */ )</span><br><span style="color: hsl(120, 100%, 40%);">+ for (child = parent->children; child && child->sibling; /* */)</span><br><span>                 child = child->sibling;</span><br><span> </span><br><span>       dev = malloc(sizeof(*dev));</span><br><span>diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c</span><br><span>index 66ff9d2..4a4609d 100644</span><br><span>--- a/src/device/hypertransport.c</span><br><span>+++ b/src/device/hypertransport.c</span><br><span>@@ -61,7 +61,7 @@</span><br><span> </span><br><span>                 /* Now add the device to the list of devices on the bus. */</span><br><span>          /* Find the last child of our parent. */</span><br><span style="color: hsl(0, 100%, 40%);">-                for (child = first->bus->children; child && child->sibling; )</span><br><span style="color: hsl(120, 100%, 40%);">+                for (child = first->bus->children; child && child->sibling;)</span><br><span>                        child = child->sibling;</span><br><span> </span><br><span>               /* Place the chain on the list of children of their parent. */</span><br><span>diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c</span><br><span>index 3fcbb7c..cdd2c20 100644</span><br><span>--- a/src/drivers/emulation/qemu/bochs.c</span><br><span>+++ b/src/drivers/emulation/qemu/bochs.c</span><br><span>@@ -99,7 +99,7 @@</span><br><span>              return;</span><br><span> </span><br><span>  printk(BIOS_DEBUG, "QEMU VGA: bochs dispi interface found, "</span><br><span style="color: hsl(0, 100%, 40%);">-         "%d MiB video memory\n", mem / ( 1024 * 1024));</span><br><span style="color: hsl(120, 100%, 40%);">+             "%d MiB video memory\n", mem / (1024 * 1024));</span><br><span>      printk(BIOS_DEBUG, "QEMU VGA: framebuffer @ %x (pci bar %d)\n",</span><br><span>           addr, bar);</span><br><span> </span><br><span>diff --git a/src/drivers/intel/fsp1_0/hob.c b/src/drivers/intel/fsp1_0/hob.c</span><br><span>index 9334893..9cf6f60 100644</span><br><span>--- a/src/drivers/intel/fsp1_0/hob.c</span><br><span>+++ b/src/drivers/intel/fsp1_0/hob.c</span><br><span>@@ -33,7 +33,7 @@</span><br><span>                      guid->Data4[0], guid->Data4[1],</span><br><span>                        guid->Data4[2], guid->Data4[3],</span><br><span>                        guid->Data4[4], guid->Data4[5],</span><br><span style="color: hsl(0, 100%, 40%);">-                   guid->Data4[6], guid->Data4[7] );</span><br><span style="color: hsl(120, 100%, 40%);">+                       guid->Data4[6], guid->Data4[7]);</span><br><span> }</span><br><span> </span><br><span> void print_hob_mem_attributes(void *Hobptr)</span><br><span>diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c</span><br><span>index ee44250..4070a1f 100644</span><br><span>--- a/src/drivers/intel/fsp2_0/hand_off_block.c</span><br><span>+++ b/src/drivers/intel/fsp2_0/hand_off_block.c</span><br><span>@@ -139,7 +139,7 @@</span><br><span> {</span><br><span>   const struct hob_resource *res;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-     for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST;</span><br><span style="color: hsl(120, 100%, 40%);">+     for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;</span><br><span>             hob = fsp_next_hob(hob)) {</span><br><span> </span><br><span>               if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR)</span><br><span>@@ -202,7 +202,7 @@</span><br><span>      if (!hob)</span><br><span>            return NULL;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-        for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST;</span><br><span style="color: hsl(120, 100%, 40%);">+     for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;</span><br><span>             hob = fsp_next_hob(hob)) {</span><br><span> </span><br><span>               if (hob->type != HOB_TYPE_GUID_EXTENSION)</span><br><span>@@ -281,7 +281,7 @@</span><br><span>   if (!hob)</span><br><span>            return;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-     for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST;</span><br><span style="color: hsl(120, 100%, 40%);">+     for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;</span><br><span>                     hob = fsp_next_hob(hob)) {</span><br><span>           if (hob->type != HOB_TYPE_GUID_EXTENSION)</span><br><span>                         continue;</span><br><span>diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c</span><br><span>index 24a340f..10c2f12 100644</span><br><span>--- a/src/drivers/intel/fsp2_0/hob_display.c</span><br><span>+++ b/src/drivers/intel/fsp2_0/hob_display.c</span><br><span>@@ -116,7 +116,7 @@</span><br><span> {</span><br><span>    const struct hob_header *hob = fsp_get_hob_list();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-  for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST;</span><br><span style="color: hsl(120, 100%, 40%);">+     for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;</span><br><span>             hob = fsp_next_hob(hob)) {</span><br><span>           if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR)</span><br><span>                    fsp_print_resource_descriptor(hob);</span><br><span>diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c</span><br><span>index 13b301f..74bb6c6 100644</span><br><span>--- a/src/drivers/intel/gma/edid.c</span><br><span>+++ b/src/drivers/intel/gma/edid.c</span><br><span>@@ -46,15 +46,15 @@</span><br><span>       wait_rdy(mmio);</span><br><span>      write32(GMBUS5_ADDR, 0);</span><br><span>     write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX</span><br><span style="color: hsl(0, 100%, 40%);">-                | GMBUS_CYCLE_STOP | ( 0x4 << GMBUS_BYTE_COUNT_SHIFT )</span><br><span style="color: hsl(0, 100%, 40%);">-            | GMBUS_SLAVE_READ | (AT24_ADDR << 1) );</span><br><span style="color: hsl(120, 100%, 40%);">+                | GMBUS_CYCLE_STOP | (0x4 << GMBUS_BYTE_COUNT_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+            | GMBUS_SLAVE_READ | (AT24_ADDR << 1));</span><br><span>        wait_rdy(mmio);</span><br><span>      write32(GMBUS5_ADDR, 0);</span><br><span>     write32(GMBUS1_ADDR, GMBUS_SW_CLR_INT);</span><br><span>      write32(GMBUS1_ADDR, 0);</span><br><span>     wait_rdy(mmio);</span><br><span>      write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP | GMBUS_SLAVE_WRITE</span><br><span style="color: hsl(0, 100%, 40%);">-                | (AT24_ADDR << 1) );</span><br><span style="color: hsl(120, 100%, 40%);">+           | (AT24_ADDR << 1));</span><br><span>   wait_rdy(mmio);</span><br><span>      write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP);</span><br><span>       write32(GMBUS2_ADDR, GMBUS_INUSE);</span><br><span>@@ -80,13 +80,13 @@</span><br><span>     /* Ensure index bits are disabled.  */</span><br><span>       write32(GMBUS5_ADDR, 0);</span><br><span>     write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX</span><br><span style="color: hsl(0, 100%, 40%);">-                | (slave << 1) );</span><br><span style="color: hsl(120, 100%, 40%);">+               | (slave << 1));</span><br><span>       wait_rdy(mmio);</span><br><span>      /* Ensure index bits are disabled.  */</span><br><span>       write32(GMBUS5_ADDR, 0);</span><br><span>     write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_SLAVE_READ | GMBUS_CYCLE_WAIT</span><br><span>              | GMBUS_CYCLE_STOP</span><br><span style="color: hsl(0, 100%, 40%);">-              | (edid_size << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) );</span><br><span style="color: hsl(120, 100%, 40%);">+         | (edid_size << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1));</span><br><span>         for (i = 0; i < edid_size / 4; i++) {</span><br><span>             u32 reg32;</span><br><span>           wait_rdy(mmio);</span><br><span>@@ -99,9 +99,9 @@</span><br><span>  wait_rdy(mmio);</span><br><span>      write32(GMBUS1_ADDR, GMBUS_SW_RDY</span><br><span>            | GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP</span><br><span style="color: hsl(0, 100%, 40%);">-               | (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) );</span><br><span style="color: hsl(120, 100%, 40%);">+               | (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1));</span><br><span>       wait_rdy(mmio);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP );</span><br><span style="color: hsl(120, 100%, 40%);">+       write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP);</span><br><span>       write32(GMBUS2_ADDR, GMBUS_INUSE);</span><br><span> </span><br><span>       printk (BIOS_SPEW, "EDID:\n");</span><br><span>diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c</span><br><span>index 97c97a2..e197114 100644</span><br><span>--- a/src/drivers/intel/wifi/wifi.c</span><br><span>+++ b/src/drivers/intel/wifi/wifi.c</span><br><span>@@ -173,7 +173,7 @@</span><br><span>      acpigen_write_package(2);</span><br><span>    acpigen_write_dword(wgds->version);</span><br><span>       /* Emit 'Domain Type' +</span><br><span style="color: hsl(0, 100%, 40%);">-  * Group specific delta of power ( 6 bytes * NUM_WGDS_SAR_GROUPS )</span><br><span style="color: hsl(120, 100%, 40%);">+     * Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS)</span><br><span>      */</span><br><span>  package_size = sizeof(sar_limits.wgds.group) + 1;</span><br><span>    acpigen_write_package(package_size);</span><br><span>diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c</span><br><span>index 75f3357..e02a331 100644</span><br><span>--- a/src/drivers/net/ne2k.c</span><br><span>+++ b/src/drivers/net/ne2k.c</span><br><span>@@ -287,7 +287,7 @@</span><br><span>      if (dev == PCI_DEV_INVALID)</span><br><span>          return 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-   pci_write_config32(dev, 0x10, eth_nic_base | 1 );</span><br><span style="color: hsl(120, 100%, 40%);">+     pci_write_config32(dev, 0x10, eth_nic_base | 1);</span><br><span>     pci_write_config8(dev, 0x4, 0x1);</span><br><span> </span><br><span>        c = inb(eth_nic_base + NE_ASIC_OFFSET + NE_RESET);</span><br><span>diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c</span><br><span>index 67d38ee..4463bad 100644</span><br><span>--- a/src/drivers/smmstore/store.c</span><br><span>+++ b/src/drivers/smmstore/store.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span>  *    uint8_t value[value_sz]</span><br><span>  *    uint8_t active</span><br><span>  *    align to 4 bytes</span><br><span style="color: hsl(0, 100%, 40%);">- *   )*</span><br><span style="color: hsl(120, 100%, 40%);">+ *  )*</span><br><span>  *   uint32le_t endmarker = 0xffffffff</span><br><span>  *</span><br><span>  * active needs to be set to 0x00 for the entry to be valid. This satisfies</span><br><span>diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c</span><br><span>index aea6872..2626ec5 100644</span><br><span>--- a/src/drivers/spi/flashconsole.c</span><br><span>+++ b/src/drivers/spi/flashconsole.c</span><br><span>@@ -55,7 +55,7 @@</span><br><span>         * the sector is already erased, so we would need to read</span><br><span>     * anyways to check if it's all 0xff).</span><br><span>    */</span><br><span style="color: hsl(0, 100%, 40%);">-     for (i = 0; i < len && offset < size; ) {</span><br><span style="color: hsl(120, 100%, 40%);">+       for (i = 0; i < len && offset < size;) {</span><br><span>               // Fill the buffer on first iteration</span><br><span>                if (i == 0) {</span><br><span>                        len = min(READ_BUFFER_SIZE, size - offset);</span><br><span>diff --git a/src/lib/edid.c b/src/lib/edid.c</span><br><span>index 37939eb..fbd8ef6 100644</span><br><span>--- a/src/lib/edid.c</span><br><span>+++ b/src/lib/edid.c</span><br><span>@@ -155,7 +155,7 @@</span><br><span>               printk(BIOS_SPEW, "    (broken)\n");</span><br><span>       } else {</span><br><span>             printk(BIOS_SPEW,</span><br><span style="color: hsl(0, 100%, 40%);">-                       "    %dx%d @ ( %s%s%s%s%s) Hz (%s%s preferred)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+                  "    %dx%d @ (%s%s%s%s%s) Hz (%s%s preferred)\n",</span><br><span>                 width, height,</span><br><span>                       fifty ? "50 " : "",</span><br><span>                      sixty ? "60 " : "",</span><br><span>diff --git a/src/lib/stack.c b/src/lib/stack.c</span><br><span>index a66b6a1..ef45e2a 100644</span><br><span>--- a/src/lib/stack.c</span><br><span>+++ b/src/lib/stack.c</span><br><span>@@ -1,5 +1,5 @@</span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">-This software and ancillary information (herein called SOFTWARE )</span><br><span style="color: hsl(120, 100%, 40%);">+This software and ancillary information (herein called SOFTWARE)</span><br><span> called LinuxBIOS          is made available under the terms described</span><br><span> here.  The SOFTWARE has been approved for release with associated</span><br><span> LA-CC Number 00-34   .  Unless otherwise indicated, this SOFTWARE has</span><br><span>diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c</span><br><span>index e355aae..5f3cd82 100644</span><br><span>--- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c</span><br><span>+++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c</span><br><span>@@ -49,7 +49,7 @@</span><br><span>                       res = find_resource(dev, PCI_BASE_ADDRESS_0);</span><br><span>                        if (res) {</span><br><span>                           current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1,</span><br><span style="color: hsl(0, 100%, 40%);">-                                  res->base, gsi_base );</span><br><span style="color: hsl(120, 100%, 40%);">+                                     res->base, gsi_base);</span><br><span>                             gsi_base+=7;</span><br><span>                         }</span><br><span>            }</span><br><span>@@ -58,7 +58,7 @@</span><br><span>                        res = find_resource(dev, PCI_BASE_ADDRESS_0);</span><br><span>                        if (res) {</span><br><span>                           current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2,</span><br><span style="color: hsl(0, 100%, 40%);">-                                  res->base, gsi_base );</span><br><span style="color: hsl(120, 100%, 40%);">+                                     res->base, gsi_base);</span><br><span>                             gsi_base+=7;</span><br><span>                         }</span><br><span>            }</span><br><span>@@ -68,7 +68,7 @@</span><br><span> </span><br><span>            for(i = 1; i < sysconf.hc_possible_num; i++) {</span><br><span>                    u32 d = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-                      if(!(sysconf.pci1234[i] & 0x1) ) continue;</span><br><span style="color: hsl(120, 100%, 40%);">+                        if(!(sysconf.pci1234[i] & 0x1)) continue;</span><br><span>                        /* 8131 need to use +4 */</span><br><span>                    switch (sysconf.hcid[i]) {</span><br><span>                   case 1:</span><br><span>@@ -86,7 +86,7 @@</span><br><span>                                  res = find_resource(dev, PCI_BASE_ADDRESS_0);</span><br><span>                                        if (res) {</span><br><span>                                           current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],</span><br><span style="color: hsl(0, 100%, 40%);">-                                                     res->base, gsi_base );</span><br><span style="color: hsl(120, 100%, 40%);">+                                                     res->base, gsi_base);</span><br><span>                                             gsi_base+=d;</span><br><span>                                         }</span><br><span>                            }</span><br><span>@@ -95,7 +95,7 @@</span><br><span>                                        res = find_resource(dev, PCI_BASE_ADDRESS_0);</span><br><span>                                        if (res) {</span><br><span>                                           current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],</span><br><span style="color: hsl(0, 100%, 40%);">-                                                     res->base, gsi_base );</span><br><span style="color: hsl(120, 100%, 40%);">+                                                     res->base, gsi_base);</span><br><span>                                             gsi_base+=d;</span><br><span>                                         }</span><br><span>                            }</span><br><span>@@ -105,7 +105,7 @@</span><br><span>              }</span><br><span>    }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-   current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) current, 0, 0, 2, 5 );</span><br><span style="color: hsl(120, 100%, 40%);">+   current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5);</span><br><span>            /* 0: mean bus 0--->ISA */</span><br><span>                /* 0: PIC 0 */</span><br><span>               /* 2: APIC 2 */</span><br><span>@@ -137,7 +137,7 @@</span><br><span> </span><br><span>    for(i = 1; i < sysconf.hc_possible_num; i++) {  /* 0: is hc sblink */</span><br><span>             const char *file_name;</span><br><span style="color: hsl(0, 100%, 40%);">-          if((sysconf.pci1234[i] & 1) != 1 ) continue;</span><br><span style="color: hsl(120, 100%, 40%);">+              if((sysconf.pci1234[i] & 1) != 1) continue;</span><br><span>              u8 c;</span><br><span>                if(i < 7) {</span><br><span>                       c  = (u8) ('4' + i - 1);</span><br><span>diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c</span><br><span>index 97a06ab..0c0e773 100644</span><br><span>--- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c</span><br><span>+++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c</span><br><span>@@ -145,7 +145,7 @@</span><br><span>   /* HT chain 1 */</span><br><span>    j = 0;</span><br><span>       for(i = 1; i< sysconf.hc_possible_num; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                if(!(sysconf.pci1234[i] & 0x1) ) continue;</span><br><span style="color: hsl(120, 100%, 40%);">+                if(!(sysconf.pci1234[i] & 0x1)) continue;</span><br><span> </span><br><span>            /* check hcid type here */</span><br><span>           sysconf.hcid[i] = get_hcid(i);</span><br><span>diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c</span><br><span>index 0927199..f8d9021 100644</span><br><span>--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c</span><br><span>+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c</span><br><span>@@ -68,7 +68,7 @@</span><br><span>          j = 0;</span><br><span> </span><br><span>           for(i = 1; i< sysconf.hc_possible_num; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                        if(!(sysconf.pci1234[i] & 0x1) ) continue;</span><br><span style="color: hsl(120, 100%, 40%);">+                        if(!(sysconf.pci1234[i] & 0x1)) continue;</span><br><span> </span><br><span>                    switch(sysconf.hcid[i]) {</span><br><span>                    case 1:</span><br><span>@@ -131,7 +131,7 @@</span><br><span>        j = 0;</span><br><span> </span><br><span>   for(i = 1; i< sysconf.hc_possible_num; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                if(!(sysconf.pci1234[i] & 0x1) ) continue;</span><br><span style="color: hsl(120, 100%, 40%);">+                if(!(sysconf.pci1234[i] & 0x1)) continue;</span><br><span>                int ii;</span><br><span>              int jj;</span><br><span>              struct device *dev;</span><br><span>diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c</span><br><span>index e26052a..da05002 100644</span><br><span>--- a/src/mainboard/amd/torpedo/gpio.c</span><br><span>+++ b/src/mainboard/amd/torpedo/gpio.c</span><br><span>@@ -91,7 +91,7 @@</span><br><span>                                 Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);</span><br><span>                   }</span><br><span>                    if (Index == GPIO_65) {</span><br><span style="color: hsl(0, 100%, 40%);">-                         if ( BoardType == 0 ) {</span><br><span style="color: hsl(120, 100%, 40%);">+                               if (BoardType == 0) {</span><br><span>                                        Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3);         // function 3</span><br><span>                                }</span><br><span>                    }</span><br><span>diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c</span><br><span>index 6b25d38..f70b88d 100644</span><br><span>--- a/src/mainboard/asus/am1i-a/BiosCallOuts.c</span><br><span>+++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c</span><br><span>@@ -125,7 +125,7 @@</span><br><span>         /* Read SATA controller mode from CMOS */</span><br><span>    enum cb_err ret;</span><br><span>     ret = get_option(&FchParams_env->Sata.SataClass, "sata_mode");</span><br><span style="color: hsl(0, 100%, 40%);">- if ( ret != CB_SUCCESS) {</span><br><span style="color: hsl(120, 100%, 40%);">+     if (ret != CB_SUCCESS) {</span><br><span>             FchParams_env->Sata.SataClass = 0;</span><br><span>                printk(BIOS_DEBUG, "ERROR: cannot read CMOS setting, falling back to default. Error code: %x\n", (int)ret);</span><br><span>        }</span><br><span>diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c</span><br><span>index 00a12cc..992cfcc 100644</span><br><span>--- a/src/mainboard/asus/m4a785-m/mainboard.c</span><br><span>+++ b/src/mainboard/asus/m4a785-m/mainboard.c</span><br><span>@@ -172,7 +172,7 @@</span><br><span>      * pm_iowrite(0x55, byte);</span><br><span>    *</span><br><span>    * byte = pm_ioread(0x67);</span><br><span style="color: hsl(0, 100%, 40%);">-       * byte &= ~( 1 << 6);</span><br><span style="color: hsl(120, 100%, 40%);">+       * byte &= ~(1 << 6);</span><br><span>       * pm_iowrite(0x67, byte);</span><br><span>    */</span><br><span> }</span><br><span>diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c</span><br><span>index 7caa4dc..3dcc6c5 100644</span><br><span>--- a/src/mainboard/biostar/am1ml/romstage.c</span><br><span>+++ b/src/mainboard/biostar/am1ml/romstage.c</span><br><span>@@ -59,36 +59,36 @@</span><br><span> static void ite_evc_conf(pnp_devfn_t dev)</span><br><span> {</span><br><span>        ite_enter_conf(dev);</span><br><span style="color: hsl(0, 100%, 40%);">-    it_sio_write(dev, 0xf1 , 0x40 );</span><br><span style="color: hsl(0, 100%, 40%);">-        it_sio_write(dev, 0xf4 , 0x80 );</span><br><span style="color: hsl(0, 100%, 40%);">-        it_sio_write(dev, 0xf5 , 0x00 );</span><br><span style="color: hsl(0, 100%, 40%);">-        it_sio_write(dev, 0xf6 , 0xf0 );</span><br><span style="color: hsl(0, 100%, 40%);">-        it_sio_write(dev, 0xf9 , 0x48 );</span><br><span style="color: hsl(0, 100%, 40%);">-        it_sio_write(dev, 0xfa , 0x00 );</span><br><span style="color: hsl(0, 100%, 40%);">-        it_sio_write(dev, 0xfb , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write(dev, 0xf1 , 0x40);</span><br><span style="color: hsl(120, 100%, 40%);">+       it_sio_write(dev, 0xf4 , 0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+       it_sio_write(dev, 0xf5 , 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+       it_sio_write(dev, 0xf6 , 0xf0);</span><br><span style="color: hsl(120, 100%, 40%);">+       it_sio_write(dev, 0xf9 , 0x48);</span><br><span style="color: hsl(120, 100%, 40%);">+       it_sio_write(dev, 0xfa , 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+       it_sio_write(dev, 0xfb , 0x00);</span><br><span>      ite_exit_conf(dev);</span><br><span> }</span><br><span> </span><br><span> static void ite_gpio_conf(pnp_devfn_t dev)</span><br><span> {</span><br><span>      ite_enter_conf (dev);</span><br><span style="color: hsl(0, 100%, 40%);">-   it_sio_write (dev, 0x25 , 0x80 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0x26 , 0x07 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0x28 , 0x81 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0x2c , 0x06 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0x72 , 0x00 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0x73 , 0x00 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0xb3 , 0x01 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0xb8 , 0x00 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0xc0 , 0x00 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0xc3 , 0x00 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0xc8 , 0x00 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0xc9 , 0x07 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0xcb , 0x01 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0xf0 , 0x10 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0xf4 , 0x27 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0xf8 , 0x20 );</span><br><span style="color: hsl(0, 100%, 40%);">-       it_sio_write (dev, 0xf9 , 0x01 );</span><br><span style="color: hsl(120, 100%, 40%);">+     it_sio_write (dev, 0x25 , 0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0x26 , 0x07);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0x28 , 0x81);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0x2c , 0x06);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0x72 , 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0x73 , 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0xb3 , 0x01);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0xb8 , 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0xc0 , 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0xc3 , 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0xc8 , 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0xc9 , 0x07);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0xcb , 0x01);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0xf0 , 0x10);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0xf4 , 0x27);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0xf8 , 0x20);</span><br><span style="color: hsl(120, 100%, 40%);">+      it_sio_write (dev, 0xf9 , 0x01);</span><br><span>     ite_exit_conf (dev);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/esd/atom15/romstage.c b/src/mainboard/esd/atom15/romstage.c</span><br><span>index 3aa02d8..c89a1e2 100644</span><br><span>--- a/src/mainboard/esd/atom15/romstage.c</span><br><span>+++ b/src/mainboard/esd/atom15/romstage.c</span><br><span>@@ -57,7 +57,7 @@</span><br><span>                   read_ssus_gpio(27),</span><br><span>                  read_ssus_gpio(28),</span><br><span>                  read_ssus_gpio(29),</span><br><span style="color: hsl(0, 100%, 40%);">-                     read_ssus_gpio(30) );</span><br><span style="color: hsl(120, 100%, 40%);">+                 read_ssus_gpio(30));</span><br><span> </span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c</span><br><span>index de90fda..a0e9631 100644</span><br><span>--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c</span><br><span>+++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c</span><br><span>@@ -226,7 +226,7 @@</span><br><span>      * pm_iowrite(0x55, byte);</span><br><span>    *</span><br><span>    * byte = pm_ioread(0x67);</span><br><span style="color: hsl(0, 100%, 40%);">-       * byte &= ~( 1 << 6);</span><br><span style="color: hsl(120, 100%, 40%);">+       * byte &= ~(1 << 6);</span><br><span>       * pm_iowrite(0x67, byte);</span><br><span>    */</span><br><span> }</span><br><span>diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c</span><br><span>index c07465c..e1850d2 100644</span><br><span>--- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c</span><br><span>+++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c</span><br><span>@@ -123,7 +123,7 @@</span><br><span> #define WLSEED 0x08</span><br><span> #define RXSEED 0x40</span><br><span>    WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),</span><br><span style="color: hsl(0, 100%, 40%);">-   HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),</span><br><span style="color: hsl(120, 100%, 40%);">+       HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),</span><br><span> </span><br><span>   PSO_END</span><br><span> };</span><br><span>diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c</span><br><span>index aaa8ae7..5b2985a 100644</span><br><span>--- a/src/mainboard/google/gru/boardid.c</span><br><span>+++ b/src/mainboard/google/gru/boardid.c</span><br><span>@@ -65,7 +65,7 @@</span><br><span>               }</span><br><span>    }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-   die("Read impossible value ( > 1023) from 10-bit ADC!");</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Read impossible value (> 1023) from 10-bit ADC!");</span><br><span> }</span><br><span> </span><br><span> uint32_t board_id(void)</span><br><span>diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c</span><br><span>index 8b8000c..8bd758b 100644</span><br><span>--- a/src/mainboard/google/link/i915.c</span><br><span>+++ b/src/mainboard/google/link/i915.c</span><br><span>@@ -295,7 +295,7 @@</span><br><span>  index = run(index);</span><br><span>  auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8;</span><br><span>       auxout[1] = 0x0a840000;</span><br><span style="color: hsl(0, 100%, 40%);">- /*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/</span><br><span style="color: hsl(120, 100%, 40%);">+     /*(DP_LINK_BW_2_7 &0xa)|0x0000840a*/</span><br><span>     auxout[2] = 0x00000000;</span><br><span>      auxout[3] = 0x01000000;</span><br><span>      intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0);</span><br><span>diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c</span><br><span>index ed79dad..7ab5eb1 100644</span><br><span>--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c</span><br><span>+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c</span><br><span>@@ -365,9 +365,9 @@</span><br><span> #define SCI_MAP_PWRBTN               0x73</span><br><span> </span><br><span> SCI_MAP_CONTROL m6_1035dx_sci_map[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-     {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE},</span><br><span style="color: hsl(0, 100%, 40%);">-      {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE},</span><br><span style="color: hsl(0, 100%, 40%);">-      {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE},</span><br><span style="color: hsl(120, 100%, 40%);">+        {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE},</span><br><span style="color: hsl(120, 100%, 40%);">+      {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE},</span><br><span style="color: hsl(120, 100%, 40%);">+      {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE},</span><br><span>         {SCI_MAP_OHCI_12_0, PME_GPE},</span><br><span>        {SCI_MAP_OHCI_13_0, PME_GPE},</span><br><span>        {SCI_MAP_XHCI_10_0, PME_GPE},</span><br><span>diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c</span><br><span>index d988023..199a15e 100644</span><br><span>--- a/src/mainboard/intel/bayleybay_fsp/romstage.c</span><br><span>+++ b/src/mainboard/intel/bayleybay_fsp/romstage.c</span><br><span>@@ -65,67 +65,67 @@</span><br><span> /*</span><br><span>  *ALC262 Verb Table - 10EC0262</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Pin Complex (NID 0x11 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x11) */</span><br><span>         0x01171CF0,</span><br><span>  0x01171D11,</span><br><span>  0x01171E11,</span><br><span>  0x01171F41,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x12 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x12) */</span><br><span>         0x01271CF0,</span><br><span>  0x01271D11,</span><br><span>  0x01271E11,</span><br><span>  0x01271F41,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x14 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x14) */</span><br><span>         0x01471C10,</span><br><span>  0x01471D40,</span><br><span>  0x01471E01,</span><br><span>  0x01471F01,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x15 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x15) */</span><br><span>         0x01571CF0,</span><br><span>  0x01571D11,</span><br><span>  0x01571E11,</span><br><span>  0x01571F41,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x16 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x16) */</span><br><span>         0x01671CF0,</span><br><span>  0x01671D11,</span><br><span>  0x01671E11,</span><br><span>  0x01671F41,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x18 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x18) */</span><br><span>         0x01871C20,</span><br><span>  0x01871D98,</span><br><span>  0x01871EA1,</span><br><span>  0x01871F01,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x19 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x19) */</span><br><span>         0x01971C21,</span><br><span>  0x01971D98,</span><br><span>  0x01971EA1,</span><br><span>  0x01971F02,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x1A ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1A) */</span><br><span>         0x01A71C2F,</span><br><span>  0x01A71D30,</span><br><span>  0x01A71E81,</span><br><span>  0x01A71F01,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x1B ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1B) */</span><br><span>         0x01B71C1F,</span><br><span>  0x01B71D40,</span><br><span>  0x01B71E21,</span><br><span>  0x01B71F02,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x1C ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1C) */</span><br><span>         0x01C71CF0,</span><br><span>  0x01C71D11,</span><br><span>  0x01C71E11,</span><br><span>  0x01C71F41,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x1D ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1D) */</span><br><span>         0x01D71C01,</span><br><span>  0x01D71DC6,</span><br><span>  0x01D71E14,</span><br><span>  0x01D71F40,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x1E ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1E) */</span><br><span>         0x01E71CF0,</span><br><span>  0x01E71D11,</span><br><span>  0x01E71E11,</span><br><span>  0x01E71F41,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x1F ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1F) */</span><br><span>         0x01F71CF0,</span><br><span>  0x01F71D11,</span><br><span>  0x01F71E11,</span><br><span>diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c</span><br><span>index 9ef46d5..3eaa8b0 100644</span><br><span>--- a/src/mainboard/lenovo/g505s/buildOpts.c</span><br><span>+++ b/src/mainboard/lenovo/g505s/buildOpts.c</span><br><span>@@ -365,9 +365,9 @@</span><br><span> #define SCI_MAP_PWRBTN                0x73</span><br><span> </span><br><span> SCI_MAP_CONTROL lenovo_g505s_sci_map[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-  {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE},</span><br><span style="color: hsl(0, 100%, 40%);">-      {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE},</span><br><span style="color: hsl(0, 100%, 40%);">-      {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE},</span><br><span style="color: hsl(120, 100%, 40%);">+        {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE},</span><br><span style="color: hsl(120, 100%, 40%);">+      {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE},</span><br><span style="color: hsl(120, 100%, 40%);">+      {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE},</span><br><span>         {SCI_MAP_OHCI_12_0, PME_GPE},</span><br><span>        {SCI_MAP_OHCI_13_0, PME_GPE},</span><br><span>        {SCI_MAP_XHCI_10_0, PME_GPE},</span><br><span>diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c</span><br><span>index 7707d62..bccb7f1 100644</span><br><span>--- a/src/mainboard/lenovo/t60/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/t60/smihandler.c</span><br><span>@@ -49,7 +49,7 @@</span><br><span> {</span><br><span>      u8 *bar;</span><br><span>     if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {</span><br><span style="color: hsl(0, 100%, 40%);">-          printk(BIOS_DEBUG, "bar: %08X, level %02X\n",  (unsigned int )bar, *(bar+LVTMA_BL_MOD_LEVEL));</span><br><span style="color: hsl(120, 100%, 40%);">+              printk(BIOS_DEBUG, "bar: %08X, level %02X\n",  (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL));</span><br><span>              *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f;</span><br><span>           if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0)</span><br><span>                     *(bar+LVTMA_BL_MOD_LEVEL) += 0x10;</span><br><span>diff --git a/src/mainboard/lenovo/z61t/smihandler.c b/src/mainboard/lenovo/z61t/smihandler.c</span><br><span>index d98a809..b93f48e 100644</span><br><span>--- a/src/mainboard/lenovo/z61t/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/z61t/smihandler.c</span><br><span>@@ -50,7 +50,7 @@</span><br><span> {</span><br><span>     u8 *bar;</span><br><span>     if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {</span><br><span style="color: hsl(0, 100%, 40%);">-          printk(BIOS_DEBUG, "bar: %08X, level %02X\n",  (unsigned int )bar,</span><br><span style="color: hsl(120, 100%, 40%);">+          printk(BIOS_DEBUG, "bar: %08X, level %02X\n",  (unsigned int)bar,</span><br><span>                  *(bar+LVTMA_BL_MOD_LEVEL));</span><br><span>          *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f;</span><br><span>           if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0)</span><br><span>diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c</span><br><span>index 80810cc..4254859 100644</span><br><span>--- a/src/mainboard/lippert/frontrunner-af/mainboard.c</span><br><span>+++ b/src/mainboard/lippert/frontrunner-af/mainboard.c</span><br><span>@@ -65,19 +65,19 @@</span><br><span> </span><br><span>      /* Init Hudson GPIOs. */</span><br><span>     printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);</span><br><span style="color: hsl(0, 100%, 40%);">-    FCH_IOMUX( 50) = 2;    // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices</span><br><span style="color: hsl(0, 100%, 40%);">-      FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed</span><br><span style="color: hsl(120, 100%, 40%);">+  FCH_IOMUX(50) = 2;    // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices</span><br><span style="color: hsl(120, 100%, 40%);">+     FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed</span><br><span>  FCH_IOMUX(197) = 2;    // GPIO197: BIOS_DEFAULTS# = input (int. PU)</span><br><span style="color: hsl(0, 100%, 40%);">-     FCH_IOMUX( 56) = 1;    // GPIO58-56: REV_ID2-0</span><br><span style="color: hsl(0, 100%, 40%);">-  FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups</span><br><span style="color: hsl(0, 100%, 40%);">-       FCH_IOMUX( 57) = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-     FCH_GPIO ( 57) = 0x28;</span><br><span style="color: hsl(0, 100%, 40%);">-  FCH_IOMUX( 58) = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-     FCH_GPIO ( 58) = 0x28;</span><br><span style="color: hsl(0, 100%, 40%);">-  FCH_IOMUX( 96) = 1;    // "Gpio96": GEVENT0# signal on X2 connector (int. PU)</span><br><span style="color: hsl(0, 100%, 40%);">- FCH_IOMUX( 52) = 1;    // GPIO52,61,62,187-192 free to use on X2 connector</span><br><span style="color: hsl(0, 100%, 40%);">-      FCH_IOMUX( 61) = 2;    // default to inputs with int. PU</span><br><span style="color: hsl(0, 100%, 40%);">-        FCH_IOMUX( 62) = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+   FCH_IOMUX(56) = 1;    // GPIO58-56: REV_ID2-0</span><br><span style="color: hsl(120, 100%, 40%);">+ FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups</span><br><span style="color: hsl(120, 100%, 40%);">+      FCH_IOMUX(57) = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+    FCH_GPIO (57) = 0x28;</span><br><span style="color: hsl(120, 100%, 40%);">+ FCH_IOMUX(58) = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+    FCH_GPIO (58) = 0x28;</span><br><span style="color: hsl(120, 100%, 40%);">+ FCH_IOMUX(96) = 1;    // "Gpio96": GEVENT0# signal on X2 connector (int. PU)</span><br><span style="color: hsl(120, 100%, 40%);">+        FCH_IOMUX(52) = 1;    // GPIO52,61,62,187-192 free to use on X2 connector</span><br><span style="color: hsl(120, 100%, 40%);">+     FCH_IOMUX(61) = 2;    // default to inputs with int. PU</span><br><span style="color: hsl(120, 100%, 40%);">+       FCH_IOMUX(62) = 2;</span><br><span>   FCH_IOMUX(187) = 2;</span><br><span>  FCH_IOMUX(188) = 2;</span><br><span>  FCH_IOMUX(189) = 1;</span><br><span>diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c</span><br><span>index c6ab265..5168228 100644</span><br><span>--- a/src/mainboard/lippert/toucan-af/mainboard.c</span><br><span>+++ b/src/mainboard/lippert/toucan-af/mainboard.c</span><br><span>@@ -33,16 +33,16 @@</span><br><span> </span><br><span>       /* Init Hudson GPIOs. */</span><br><span>     printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);</span><br><span style="color: hsl(0, 100%, 40%);">-    FCH_IOMUX( 50) = 2;    // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices</span><br><span style="color: hsl(0, 100%, 40%);">-      FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed</span><br><span style="color: hsl(120, 100%, 40%);">+  FCH_IOMUX(50) = 2;    // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices</span><br><span style="color: hsl(120, 100%, 40%);">+     FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed</span><br><span>  FCH_IOMUX(197) = 2;    // GPIO197: BIOS_DEFAULTS#</span><br><span>    FCH_GPIO (197) = 0x28; // = input, disable int. pull-up</span><br><span style="color: hsl(0, 100%, 40%);">- FCH_IOMUX( 56) = 1;    // GPIO58-56: REV_ID2-0</span><br><span style="color: hsl(0, 100%, 40%);">-  FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups</span><br><span style="color: hsl(0, 100%, 40%);">-       FCH_IOMUX( 57) = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-     FCH_GPIO ( 57) = 0x28;</span><br><span style="color: hsl(0, 100%, 40%);">-  FCH_IOMUX( 58) = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-     FCH_GPIO ( 58) = 0x28;</span><br><span style="color: hsl(120, 100%, 40%);">+        FCH_IOMUX(56) = 1;    // GPIO58-56: REV_ID2-0</span><br><span style="color: hsl(120, 100%, 40%);">+ FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups</span><br><span style="color: hsl(120, 100%, 40%);">+      FCH_IOMUX(57) = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+    FCH_GPIO (57) = 0x28;</span><br><span style="color: hsl(120, 100%, 40%);">+ FCH_IOMUX(58) = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+    FCH_GPIO (58) = 0x28;</span><br><span>        FCH_IOMUX(187) = 2;    // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector</span><br><span>    FCH_GPIO (187) = 0x08; // = outputs, disable PUs, default to 0</span><br><span>       FCH_IOMUX(188) = 2;</span><br><span>diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c</span><br><span>index c5ceb75..5b7b9c0 100644</span><br><span>--- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c</span><br><span>+++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c</span><br><span>@@ -106,7 +106,7 @@</span><br><span>                           m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);</span><br><span>                       }</span><br><span>                    else {</span><br><span style="color: hsl(0, 100%, 40%);">-                          printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );</span><br><span style="color: hsl(120, 100%, 40%);">+                           printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);</span><br><span>                   }</span><br><span>            }</span><br><span> </span><br><span>diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c</span><br><span>index 8fe2dc0..e482840 100644</span><br><span>--- a/src/mainboard/pcengines/alix1c/romstage.c</span><br><span>+++ b/src/mainboard/pcengines/alix1c/romstage.c</span><br><span>@@ -44,7 +44,7 @@</span><br><span>  * 4banks (2)</span><br><span>  * SSTL_2 (2)</span><br><span>  * 4th GEN die (C)</span><br><span style="color: hsl(0, 100%, 40%);">- * Normal Power Consumption (<blank> )</span><br><span style="color: hsl(120, 100%, 40%);">+ * Normal Power Consumption (<blank>)</span><br><span>  * TSOP (T)</span><br><span>  * Single Die (<blank>)</span><br><span>  * Lead Free (P)</span><br><span>diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c</span><br><span>index da3913d..9bb9c00 100644</span><br><span>--- a/src/mainboard/pcengines/alix2d/romstage.c</span><br><span>+++ b/src/mainboard/pcengines/alix2d/romstage.c</span><br><span>@@ -42,7 +42,7 @@</span><br><span>  * 4banks (2)</span><br><span>  * SSTL_2 (2)</span><br><span>  * 4th GEN die (C)</span><br><span style="color: hsl(0, 100%, 40%);">- * Normal Power Consumption (<blank> )</span><br><span style="color: hsl(120, 100%, 40%);">+ * Normal Power Consumption (<blank>)</span><br><span>  * TSOP (T)</span><br><span>  * Single Die (<blank>)</span><br><span>  * Lead Free (P)</span><br><span>diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c</span><br><span>index 330531f..9febec7 100644</span><br><span>--- a/src/mainboard/pcengines/apu1/OemCustomize.c</span><br><span>+++ b/src/mainboard/pcengines/apu1/OemCustomize.c</span><br><span>@@ -108,7 +108,7 @@</span><br><span> #define WLSEED 0x08</span><br><span> #define RXSEED 0x40</span><br><span>       WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),</span><br><span style="color: hsl(0, 100%, 40%);">-   HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),</span><br><span style="color: hsl(120, 100%, 40%);">+       HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),</span><br><span> </span><br><span>   PSO_END</span><br><span> };</span><br><span>diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c</span><br><span>index 018fc0a..8942d9b 100644</span><br><span>--- a/src/mainboard/pcengines/apu1/gpio_ftns.c</span><br><span>+++ b/src/mainboard/pcengines/apu1/gpio_ftns.c</span><br><span>@@ -25,9 +25,9 @@</span><br><span>       uintptr_t base_addr = 0;</span><br><span> </span><br><span>         /* Find the ACPImmioAddr base address */</span><br><span style="color: hsl(0, 100%, 40%);">-        for ( pm_index = 0x27; pm_index > 0x23; pm_index-- ) {</span><br><span style="color: hsl(0, 100%, 40%);">-               outb( pm_index, PM_INDEX );</span><br><span style="color: hsl(0, 100%, 40%);">-             pm_data = inb( PM_DATA );</span><br><span style="color: hsl(120, 100%, 40%);">+     for (pm_index = 0x27; pm_index > 0x23; pm_index--) {</span><br><span style="color: hsl(120, 100%, 40%);">+               outb(pm_index, PM_INDEX);</span><br><span style="color: hsl(120, 100%, 40%);">+             pm_data = inb(PM_DATA);</span><br><span>              base_addr <<= 8;</span><br><span>               base_addr |= (u32)pm_data;</span><br><span>   }</span><br><span>diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c</span><br><span>index 8e2636b..1c7b4fd 100644</span><br><span>--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c</span><br><span>+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c</span><br><span>@@ -99,7 +99,7 @@</span><br><span>                       FchParams->Usb.Ehci1Enable = TRUE;</span><br><span>                }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-           // Enable EHCI 1 ( port 4 to 7)</span><br><span style="color: hsl(120, 100%, 40%);">+               // Enable EHCI 1 (port 4 to 7)</span><br><span>               // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.</span><br><span>            FchParams->Usb.Ehci2Enable = TRUE;</span><br><span> </span><br><span>diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c</span><br><span>index 9434b93..c6b9b8e 100644</span><br><span>--- a/src/mainboard/pcengines/apu2/mainboard.c</span><br><span>+++ b/src/mainboard/pcengines/apu2/mainboard.c</span><br><span>@@ -167,12 +167,12 @@</span><br><span>       //</span><br><span>   // Enable the RTC output</span><br><span>     //</span><br><span style="color: hsl(0, 100%, 40%);">-      pm_write16 ( PM_RTC_CONTROL, pm_read16( PM_RTC_CONTROL ) | (1 << 11));</span><br><span style="color: hsl(120, 100%, 40%);">+  pm_write16 (PM_RTC_CONTROL, pm_read16(PM_RTC_CONTROL) | (1 << 11));</span><br><span> </span><br><span>        //</span><br><span>   // Enable power on from WAKE#</span><br><span>        //</span><br><span style="color: hsl(0, 100%, 40%);">-      pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14));</span><br><span style="color: hsl(120, 100%, 40%);">+  pm_write16 (PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14));</span><br><span> </span><br><span>        /* Initialize the PIRQ data structures for consumption */</span><br><span>    pirq_setup();</span><br><span>diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c</span><br><span>index 628e88b..ef07f7e 100644</span><br><span>--- a/src/mainboard/siemens/mc_tcu3/romstage.c</span><br><span>+++ b/src/mainboard/siemens/mc_tcu3/romstage.c</span><br><span>@@ -66,67 +66,67 @@</span><br><span> /*</span><br><span>  *ALC262 Verb Table - 10EC0262</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Pin Complex (NID 0x11 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x11) */</span><br><span>         0x01171CF0,</span><br><span>  0x01171D11,</span><br><span>  0x01171E11,</span><br><span>  0x01171F41,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x12 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x12) */</span><br><span>         0x01271CF0,</span><br><span>  0x01271D11,</span><br><span>  0x01271E11,</span><br><span>  0x01271F41,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x14 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x14) */</span><br><span>         0x01471C10,</span><br><span>  0x01471D40,</span><br><span>  0x01471E01,</span><br><span>  0x01471F01,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x15 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x15) */</span><br><span>         0x01571CF0,</span><br><span>  0x01571D11,</span><br><span>  0x01571E11,</span><br><span>  0x01571F41,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x16 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x16) */</span><br><span>         0x01671CF0,</span><br><span>  0x01671D11,</span><br><span>  0x01671E11,</span><br><span>  0x01671F41,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x18 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x18) */</span><br><span>         0x01871C20,</span><br><span>  0x01871D98,</span><br><span>  0x01871EA1,</span><br><span>  0x01871F01,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x19 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x19) */</span><br><span>         0x01971C21,</span><br><span>  0x01971D98,</span><br><span>  0x01971EA1,</span><br><span>  0x01971F02,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x1A ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1A) */</span><br><span>         0x01A71C2F,</span><br><span>  0x01A71D30,</span><br><span>  0x01A71E81,</span><br><span>  0x01A71F01,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x1B ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1B) */</span><br><span>         0x01B71C1F,</span><br><span>  0x01B71D40,</span><br><span>  0x01B71E21,</span><br><span>  0x01B71F02,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x1C ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1C) */</span><br><span>         0x01C71CF0,</span><br><span>  0x01C71D11,</span><br><span>  0x01C71E11,</span><br><span>  0x01C71F41,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x1D ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1D) */</span><br><span>         0x01D71C01,</span><br><span>  0x01D71DC6,</span><br><span>  0x01D71E14,</span><br><span>  0x01D71F40,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x1E ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1E) */</span><br><span>         0x01E71CF0,</span><br><span>  0x01E71D11,</span><br><span>  0x01E71E11,</span><br><span>  0x01E71F41,</span><br><span style="color: hsl(0, 100%, 40%);">-     /* Pin Complex (NID 0x1F ) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1F) */</span><br><span>         0x01F71CF0,</span><br><span>  0x01F71D11,</span><br><span>  0x01F71E11,</span><br><span>diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c</span><br><span>index b2bc0dd..1015a7a 100644</span><br><span>--- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c</span><br><span>+++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c</span><br><span>@@ -104,7 +104,7 @@</span><br><span>                           m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);</span><br><span>                       }</span><br><span>                    else {</span><br><span style="color: hsl(0, 100%, 40%);">-                          printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );</span><br><span style="color: hsl(120, 100%, 40%);">+                           printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);</span><br><span>                   }</span><br><span>            }</span><br><span> </span><br><span>diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c</span><br><span>index 75b1347..5bdbe29 100644</span><br><span>--- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c</span><br><span>+++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c</span><br><span>@@ -110,7 +110,7 @@</span><br><span>                                 m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);</span><br><span>                       }</span><br><span>                    else {</span><br><span style="color: hsl(0, 100%, 40%);">-                          printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );</span><br><span style="color: hsl(120, 100%, 40%);">+                           printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);</span><br><span>                   }</span><br><span>            }</span><br><span> </span><br><span>diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c</span><br><span>index 09704f8..7da31d7 100644</span><br><span>--- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c</span><br><span>+++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c</span><br><span>@@ -103,7 +103,7 @@</span><br><span>                                 m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);</span><br><span>                       }</span><br><span>                    else {</span><br><span style="color: hsl(0, 100%, 40%);">-                          printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );</span><br><span style="color: hsl(120, 100%, 40%);">+                           printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);</span><br><span>                   }</span><br><span>            }</span><br><span> </span><br><span>diff --git a/src/northbridge/amd/agesa/family12/dimmSpd.c b/src/northbridge/amd/agesa/family12/dimmSpd.c</span><br><span>index 2f0af59..a0a1aea 100644</span><br><span>--- a/src/northbridge/amd/agesa/family12/dimmSpd.c</span><br><span>+++ b/src/northbridge/amd/agesa/family12/dimmSpd.c</span><br><span>@@ -55,7 +55,7 @@</span><br><span>   IN UINT32 Func,</span><br><span>   IN UINTN Data,</span><br><span>   IN OUT AGESA_READ_SPD_PARAMS *SpdData</span><br><span style="color: hsl(0, 100%, 40%);">-  )</span><br><span style="color: hsl(120, 100%, 40%);">+ )</span><br><span> {</span><br><span>       UINT8  SmBusAddress = 0;</span><br><span>     UINTN  Index;</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c</span><br><span>index f62aa15..b62661b 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c</span><br><span>@@ -684,7 +684,7 @@</span><br><span>                         {tempW = bitTestSet(tempW, 7);}</span><br><span>                      if (bitTest(tempW1,18))</span><br><span>                      {tempW = bitTestSet(tempW, 6);}</span><br><span style="color: hsl(0, 100%, 40%);">-                 /* tempW = tempW|(((tempW1 >> 20) & 0x7 )<< 3); */</span><br><span style="color: hsl(120, 100%, 40%);">+                    /* tempW = tempW|(((tempW1 >> 20) & 0x7)<< 3); */</span><br><span>                    tempW = tempW|((tempW1&0x00700000) >> 17);</span><br><span>                         /* workaround for DR-B0 */</span><br><span>                   if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED]))</span><br><span>diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c</span><br><span>index fdeefab..4df2cbd 100644</span><br><span>--- a/src/northbridge/amd/pi/00730F01/dimmSpd.c</span><br><span>+++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c</span><br><span>@@ -34,9 +34,9 @@</span><br><span>        if ((dev == 0) || (config == 0))</span><br><span>             return AGESA_ERROR;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (info->SocketId     >= DIMENSION(config->spdAddrLookup      ))</span><br><span style="color: hsl(120, 100%, 40%);">+    if (info->SocketId     >= DIMENSION(config->spdAddrLookup     ))</span><br><span>            return AGESA_ERROR;</span><br><span style="color: hsl(0, 100%, 40%);">-     if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0]   ))</span><br><span style="color: hsl(120, 100%, 40%);">+    if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0]  ))</span><br><span>            return AGESA_ERROR;</span><br><span>  if (info->DimmId       >= DIMENSION(config->spdAddrLookup[0][0]))</span><br><span>           return AGESA_ERROR;</span><br><span>diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c</span><br><span>index c085c87..da12abd 100644</span><br><span>--- a/src/northbridge/intel/e7505/debug.c</span><br><span>+++ b/src/northbridge/intel/e7505/debug.c</span><br><span>@@ -148,7 +148,7 @@</span><br><span>   printk(BIOS_DEBUG, "\n");</span><br><span>  for (device = 1; device < 0x80; device++) {</span><br><span>               int j;</span><br><span style="color: hsl(0, 100%, 40%);">-          if ( spd_read_byte(device, 0) < 0 ) continue;</span><br><span style="color: hsl(120, 100%, 40%);">+              if (spd_read_byte(device, 0) < 0) continue;</span><br><span>               printk(BIOS_DEBUG, "smbus: %02x", device);</span><br><span>                 for (j = 0; j < 256; j++) {</span><br><span>                       int status;</span><br><span>diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c</span><br><span>index 72b2761..94855cf 100644</span><br><span>--- a/src/northbridge/intel/fsp_rangeley/northbridge.c</span><br><span>+++ b/src/northbridge/intel/fsp_rangeley/northbridge.c</span><br><span>@@ -131,7 +131,7 @@</span><br><span>       mmio_resource(dev, index++, tomlow >> 10, (bmbound - bsmmrrl) >> 10);</span><br><span> </span><br><span>        if (bmbound_hi > 0x100000000) {</span><br><span style="color: hsl(0, 100%, 40%);">-              ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10 );</span><br><span style="color: hsl(120, 100%, 40%);">+         ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10);</span><br><span>                 printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (bmbound_hi - 0x100000000) >> 20);</span><br><span>  }</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c</span><br><span>index 5adf865..778b2f7 100644</span><br><span>--- a/src/northbridge/intel/pineview/raminit.c</span><br><span>+++ b/src/northbridge/intel/pineview/raminit.c</span><br><span>@@ -57,13 +57,13 @@</span><br><span> </span><br><span> #define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0)</span><br><span> #define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \</span><br><span style="color: hsl(120, 100%, 40%);">+#define ONLY_DIMMA_IS_POPULATED(dimms, ch) (\</span><br><span>       (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \</span><br><span>    !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))</span><br><span style="color: hsl(0, 100%, 40%);">-#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \</span><br><span style="color: hsl(120, 100%, 40%);">+#define ONLY_DIMMB_IS_POPULATED(dimms, ch) (\</span><br><span>  (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \</span><br><span>    !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2)))</span><br><span style="color: hsl(0, 100%, 40%);">-#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \</span><br><span style="color: hsl(120, 100%, 40%);">+#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) (\</span><br><span>        (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \</span><br><span>    (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))))</span><br><span> #define FOR_EACH_DIMM(idx) \</span><br><span>@@ -905,11 +905,11 @@</span><br><span>      reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9);</span><br><span>    reg32 |= ((u32) pll->dbsel[f][clk]) << dqs;</span><br><span>         MCHBAR32(0x5b4+rank*4) = (MCHBAR32(0x5b4+rank*4) &</span><br><span style="color: hsl(0, 100%, 40%);">-          ~( (1 << (dqs+9))|(1 << dqs) )) | reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+          ~((1 << (dqs+9))|(1 << dqs))) | reg32;</span><br><span> </span><br><span>       reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs*2) + 16);</span><br><span>    MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) &</span><br><span style="color: hsl(0, 100%, 40%);">-          ~( (1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)) )) | reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+            ~((1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)))) | reg32;</span><br><span> </span><br><span>         reg8 = pll->pi[f][clk];</span><br><span>   MCHBAR8(0x520+j) = (MCHBAR8(0x520+j) & ~0x3f) | reg8;</span><br><span>@@ -930,11 +930,11 @@</span><br><span>    reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9);</span><br><span>     reg32 |= ((u32) pll->dbsel[f][clk]) << dq;</span><br><span>  MCHBAR32(0x5a4+rank*4) = (MCHBAR32(0x5a4+rank*4) &</span><br><span style="color: hsl(0, 100%, 40%);">-          ~( (1 << (dq+9))|(1 << dq) )) | reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+            ~((1 << (dq+9))|(1 << dq))) | reg32;</span><br><span> </span><br><span>         reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2);</span><br><span>    MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) &</span><br><span style="color: hsl(0, 100%, 40%);">-          ~( (1 << (dq*2 + 1))|(1 << (dq*2)) )) | reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+            ~((1 << (dq*2 + 1))|(1 << (dq*2)))) | reg32;</span><br><span> </span><br><span>         reg8 = pll->pi[f][clk];</span><br><span>   MCHBAR8(0x500+j) = (MCHBAR8(0x500+j) & ~0x3f) | reg8;</span><br><span>diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c</span><br><span>index 254be7b..494d78a 100644</span><br><span>--- a/src/northbridge/via/vx900/chrome9hd.c</span><br><span>+++ b/src/northbridge/via/vx900/chrome9hd.c</span><br><span>@@ -105,15 +105,15 @@</span><br><span>    * 0000: 66MHz</span><br><span>        * 0001: 100MHz</span><br><span>       * 0010: 133MHz</span><br><span style="color: hsl(0, 100%, 40%);">-  * 0011: 200MHz ( DDR200 )</span><br><span style="color: hsl(0, 100%, 40%);">-       * 0100: 266MHz ( DDR266 )</span><br><span style="color: hsl(0, 100%, 40%);">-       * 0101: 333MHz ( DDR333 )</span><br><span style="color: hsl(0, 100%, 40%);">-       * 0110: 400MHz ( DDR400 )</span><br><span style="color: hsl(0, 100%, 40%);">-       * 0111: 533MHz ( DDR I/II 533)</span><br><span style="color: hsl(0, 100%, 40%);">-  * 1000: 667MHz ( DDR I/II 667)</span><br><span style="color: hsl(0, 100%, 40%);">-  * 1001: 800MHz  ( DDR3 800)</span><br><span style="color: hsl(0, 100%, 40%);">-     * 1010: 1066MHz ( DDR3 1066)</span><br><span style="color: hsl(0, 100%, 40%);">-    * 1011: 1333MHz ( DDR3 1333)</span><br><span style="color: hsl(120, 100%, 40%);">+  * 0011: 200MHz (DDR200)</span><br><span style="color: hsl(120, 100%, 40%);">+       * 0100: 266MHz (DDR266)</span><br><span style="color: hsl(120, 100%, 40%);">+       * 0101: 333MHz (DDR333)</span><br><span style="color: hsl(120, 100%, 40%);">+       * 0110: 400MHz (DDR400)</span><br><span style="color: hsl(120, 100%, 40%);">+       * 0111: 533MHz (DDR I/II 533)</span><br><span style="color: hsl(120, 100%, 40%);">+         * 1000: 667MHz (DDR I/II 667)</span><br><span style="color: hsl(120, 100%, 40%);">+         * 1001: 800MHz  (DDR3 800)</span><br><span style="color: hsl(120, 100%, 40%);">+    * 1010: 1066MHz (DDR3 1066)</span><br><span style="color: hsl(120, 100%, 40%);">+   * 1011: 1333MHz (DDR3 1333)</span><br><span>          * Bit[3:0]</span><br><span>   * N:  Frame Buffer Size 2^N  MB</span><br><span>      */</span><br><span>diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c</span><br><span>index ff5dc87..ea9400e 100644</span><br><span>--- a/src/soc/broadcom/cygnus/ddr_init.c</span><br><span>+++ b/src/soc/broadcom/cygnus/ddr_init.c</span><br><span>@@ -71,31 +71,31 @@</span><br><span> </span><br><span>   // Disable low power receivers:  bit 0 of the byte lane STATIC_PAD_CTL register</span><br><span>      readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL);</span><br><span style="color: hsl(0, 100%, 40%);">-      reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R)));</span><br><span style="color: hsl(120, 100%, 40%);">+      reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R)));</span><br><span> </span><br><span>  // Turn off ZQ_CAL drivers: bits 0,1, and 17 of the ZQ_CAL register (other bits 0 & 1 are set to 1)</span><br><span>      readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL);</span><br><span style="color: hsl(0, 100%, 40%);">-      reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ)));</span><br><span style="color: hsl(120, 100%, 40%);">+        reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ)));</span><br><span> </span><br><span>    // Byte lane 0 power up</span><br><span>      readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);</span><br><span style="color: hsl(0, 100%, 40%);">-     reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE)));</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE)));</span><br><span> </span><br><span>     readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);</span><br><span style="color: hsl(0, 100%, 40%);">-     reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f));</span><br><span style="color: hsl(120, 100%, 40%);">+       reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & 0xffff800f));</span><br><span> </span><br><span>   readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);</span><br><span style="color: hsl(0, 100%, 40%);">-     reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ)));</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ)));</span><br><span> </span><br><span>     // Byte lane 1 power up</span><br><span>      readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);</span><br><span style="color: hsl(0, 100%, 40%);">-     reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE)));</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE)));</span><br><span> </span><br><span>     readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);</span><br><span style="color: hsl(0, 100%, 40%);">-     reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f));</span><br><span style="color: hsl(120, 100%, 40%);">+       reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & 0xffff800f));</span><br><span> </span><br><span>   readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);</span><br><span style="color: hsl(0, 100%, 40%);">-     reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ)));</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ)));</span><br><span> </span><br><span>     // Turn on PHY_CONTROL AUTO_OEB C not required</span><br><span>       // Enable byte lane AUTO_DQ_RXENB_MODE: bits 18 and 19 of the byte lane IDLE_PAD_CONTROL C already set 180114c8: 000f000a</span><br><span>@@ -108,7 +108,7 @@</span><br><span>      printk(BIOS_INFO, "\n....poll lock..\n");</span><br><span>  // Poll lock</span><br><span>         readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS);</span><br><span style="color: hsl(0, 100%, 40%);">-   while ( ( readvalue & 0x1) == 0x0 )</span><br><span style="color: hsl(120, 100%, 40%);">+       while ((readvalue & 0x1) == 0x0)</span><br><span>         {</span><br><span>            printk(BIOS_INFO, "\n....DDR_PHY_CONTROL_REGS_PLL_STATUS = %8x..\n",readvalue);</span><br><span>            readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS);</span><br><span>@@ -143,7 +143,7 @@</span><br><span> {</span><br><span>     uint32_t val;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define SET_OVR_STEP(v) ( 0x30000 | ( (v) & 0x3F ) )    /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F))    /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */</span><br><span> </span><br><span>      val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN);</span><br><span>    val = SET_OVR_STEP(val & 0xff);</span><br><span>@@ -441,27 +441,27 @@</span><br><span> /*DDR_SHMOO_RELATED_CHANGE*/</span><br><span> </span><br><span> #ifdef CONFIG_RUN_DDR_SHMOO</span><br><span style="color: hsl(0, 100%, 40%);">-int ReWriteModeRegisters( void )</span><br><span style="color: hsl(120, 100%, 40%);">+int ReWriteModeRegisters(void)</span><br><span> {</span><br><span>  int nRet = 0;</span><br><span>        int j = 100;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-        reg32_clear_bits( (volatile uint32_t *)DDR_DENALI_CTL_89 , 1 << 18 );</span><br><span style="color: hsl(120, 100%, 40%);">+   reg32_clear_bits((volatile uint32_t *)DDR_DENALI_CTL_89 , 1 << 18);</span><br><span> </span><br><span>        /* Set mode register for MR0, MR1, MR2 and MR3 write for all chip selects */</span><br><span style="color: hsl(0, 100%, 40%);">-    reg32_write( (volatile uint32_t *)DDR_DENALI_CTL_43 , (1 << 17) | (1 << 24) | (1 << 25) );</span><br><span style="color: hsl(120, 100%, 40%);">+  reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43 , (1 << 17) | (1 << 24) | (1 << 25));</span><br><span> </span><br><span>       /* Trigger Mode Register Write(MRW) sequence */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32_set_bits( (volatile uint32_t *)DDR_DENALI_CTL_43 , 1 << 25 );</span><br><span style="color: hsl(120, 100%, 40%);">+     reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_43 , 1 << 25);</span><br><span> </span><br><span>  do {</span><br><span style="color: hsl(0, 100%, 40%);">-            if ( reg32_read( (volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18) ) {</span><br><span style="color: hsl(120, 100%, 40%);">+            if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) {</span><br><span>                      break;</span><br><span>               }</span><br><span>            --j;</span><br><span style="color: hsl(0, 100%, 40%);">-    } while ( j );</span><br><span style="color: hsl(120, 100%, 40%);">+        } while (j);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-        if ( j == 0 && (reg32_read( (volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18) ) == 0 ) {</span><br><span style="color: hsl(120, 100%, 40%);">+  if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) {</span><br><span>             printk(BIOS_ERR, "Error: DRAM mode registers write failed\n");</span><br><span>             nRet = 1;</span><br><span>    };</span><br><span>@@ -965,7 +965,7 @@</span><br><span>     for (i=0; i<pairs; i++) {</span><br><span>         reg = (uint32_t *)(*flptr++);</span><br><span>         val = (uint32_t *)(*flptr++);</span><br><span style="color: hsl(0, 100%, 40%);">-  if ( (((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114)))</span><br><span style="color: hsl(120, 100%, 40%);">+   if ((((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114)))</span><br><span> #if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS)</span><br><span>                 || (((uint32_t)reg >= DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + 0x114)))</span><br><span> #endif</span><br><span>@@ -983,7 +983,7 @@</span><br><span>     printk(BIOS_INFO, "done\n");</span><br><span> </span><br><span>     /* Perform memory test to see if the parameters work */</span><br><span style="color: hsl(0, 100%, 40%);">-    if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0 ) {</span><br><span style="color: hsl(120, 100%, 40%);">+    if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) {</span><br><span>         printk(BIOS_INFO, "Running simple memory test ..... ");</span><br><span>         i = simple_memory_test(</span><br><span>             (void *)CONFIG_SHMOO_REUSE_MEMTEST_START,</span><br><span>@@ -1118,7 +1118,7 @@</span><br><span> </span><br><span>     reg32_write((uint32_t *)DDR_BistConfig,reg32_read((uint32_t *)DDR_BistConfig) & ~0x1);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-    for ( i = 0; i < 1000; i++);</span><br><span style="color: hsl(120, 100%, 40%);">+    for (i = 0; i < 1000; i++);</span><br><span> </span><br><span> #if !defined(CONFIG_IPROC_P7)</span><br><span>   reg32_write((volatile uint32_t *)DDR_DENALI_CTL_213, 0x00FFFFFF);</span><br><span>@@ -1377,7 +1377,7 @@</span><br><span>    /* Wait for DDR PHY up */</span><br><span>    for (i=0; i < 0x19000; i++) {</span><br><span>             val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);</span><br><span style="color: hsl(0, 100%, 40%);">-           if ( val != 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+              if (val != 0) {</span><br><span>             printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val);</span><br><span>                   break; /* DDR PHY is up */</span><br><span>         }</span><br><span>@@ -1484,7 +1484,7 @@</span><br><span>      /* Enable auto self-refresh */</span><br><span>       reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57,</span><br><span>            0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R |</span><br><span style="color: hsl(0, 100%, 40%);">-             0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R );</span><br><span style="color: hsl(120, 100%, 40%);">+         0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R);</span><br><span> </span><br><span>     reg32_set_bits((unsigned int *)DDR_DENALI_CTL_58,</span><br><span>            DDR_AUTO_SELF_REFRESH_IDLE_COUNT << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R);</span><br><span>@@ -1495,9 +1495,9 @@</span><br><span>     /* Disable auto-self refresh */</span><br><span>      reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_57,</span><br><span>          0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R |</span><br><span style="color: hsl(0, 100%, 40%);">-             0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R );</span><br><span style="color: hsl(120, 100%, 40%);">+         0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R);</span><br><span>         reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_58,</span><br><span style="color: hsl(0, 100%, 40%);">-             0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R );</span><br><span style="color: hsl(120, 100%, 40%);">+         0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R);</span><br><span> #endif</span><br><span> </span><br><span>   /* Start the DDR */</span><br><span>diff --git a/src/soc/broadcom/cygnus/phy_reg_access.c b/src/soc/broadcom/cygnus/phy_reg_access.c</span><br><span>index eb48133..7965d5b 100644</span><br><span>--- a/src/soc/broadcom/cygnus/phy_reg_access.c</span><br><span>+++ b/src/soc/broadcom/cygnus/phy_reg_access.c</span><br><span>@@ -17,14 +17,14 @@</span><br><span> </span><br><span>   volatile unsigned long data;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-  data = (* (volatile uint32 *) ( ((uint32)GLOBAL_REG_RBUS_START) | (address)));</span><br><span style="color: hsl(120, 100%, 40%);">+  data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address)));</span><br><span>   //printf("REGRD %08X=%08X\n", address, data);</span><br><span>   return data;</span><br><span> }</span><br><span> </span><br><span> uint32 REGWR (uint32 address, uint32 data) {</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-  ((* (volatile uint32 *) ( ((uint32)GLOBAL_REG_RBUS_START) | (address))) = data);</span><br><span style="color: hsl(120, 100%, 40%);">+  ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data);</span><br><span>   //printf("REGWR %08X=%08X\n", address, data);</span><br><span> //  return SOC_E_NONE;</span><br><span>    return 0;</span><br><span>diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c</span><br><span>index 20a0664..6cddf76 100644</span><br><span>--- a/src/soc/intel/baytrail/perf_power.c</span><br><span>+++ b/src/soc/intel/baytrail/perf_power.c</span><br><span>@@ -221,7 +221,7 @@</span><br><span> E(CCU,  0x38,    MASK_VAL(31,    0,    0x0)),    //vlv.ccu.ccu_trunk_clkgate_2</span><br><span> E(CCU,  0x1c,    MASK_VAL(29,   28,    0x0)),    //vlv.ccu.clkgate_en_1.cr_lpe_pri_clkgate_en</span><br><span> E(CCU,  0x1c,    MASK_VAL(25,   24,    0x0)),    //vlv.ccu.clkgate_en_1.cr_lpe_sb_clkgate_en</span><br><span style="color: hsl(0, 100%, 40%);">-E(CCU,  0x1c,    MASK_VAL( 1,    0,    0x0)),    //vlv.ccu.clkgate_en_1.lps_free_clkgate_en</span><br><span style="color: hsl(120, 100%, 40%);">+E(CCU,  0x1c,    MASK_VAL(1,    0,    0x0)),    //vlv.ccu.clkgate_en_1.lps_free_clkgate_en</span><br><span> E(CCU,  0x54,    MASK_VAL(17,   16,    0x0)),    //vlv.ccu.clkgate_en_3.cr_lpe_func_ip_clkgate_en</span><br><span> E(CCU,  0x54,    MASK_VAL(13,   12,    0x0)),    //vlv.ccu.clkgate_en_3.cr_lpe_osc_ip_clk_en</span><br><span> E(CCU,  0x54,    MASK_VAL(15,   14,    0x0)),    //vlv.ccu.clkgate_en_3.cr_lpe_xtal_ip_clkgate_en</span><br><span>diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c</span><br><span>index 4d13539..ccd6c9f 100644</span><br><span>--- a/src/soc/intel/braswell/chip.c</span><br><span>+++ b/src/soc/intel/braswell/chip.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> </span><br><span> static void pci_domain_set_resources(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-  printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span>  assign_resources(dev->link_list);</span><br><span> }</span><br><span>@@ -49,7 +49,7 @@</span><br><span> </span><br><span> static void enable_dev(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    printk(BIOS_SPEW, "----------\n%s/%s ( %s ), type: %d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+   printk(BIOS_SPEW, "----------\n%s/%s (%s), type: %d\n",</span><br><span>                    __FILE__, __func__,</span><br><span>                  dev_name(dev), dev->path.type);</span><br><span>   printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n",</span><br><span>@@ -384,7 +384,7 @@</span><br><span> static void pci_set_subsystem(struct device *dev, unsigned int vendor,</span><br><span>      unsigned int device)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-       printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s, 0x%04x, 0x%04x)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev), vendor, device);</span><br><span>  if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c</span><br><span>index 27903e8..195dba4 100644</span><br><span>--- a/src/soc/intel/braswell/cpu.c</span><br><span>+++ b/src/soc/intel/braswell/cpu.c</span><br><span>@@ -47,7 +47,7 @@</span><br><span> </span><br><span> static void soc_core_init(struct device *cpu)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-     printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(cpu));</span><br><span>  printk(BIOS_DEBUG, "Init Braswell core.\n");</span><br><span> </span><br><span>@@ -219,7 +219,7 @@</span><br><span> {</span><br><span>        struct bus *cpu_bus = dev->link_list;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-    printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> </span><br><span>      if (mp_init_with_smm(cpu_bus, &mp_ops))</span><br><span>diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c</span><br><span>index 44116a8..238f8db 100644</span><br><span>--- a/src/soc/intel/braswell/emmc.c</span><br><span>+++ b/src/soc/intel/braswell/emmc.c</span><br><span>@@ -36,7 +36,7 @@</span><br><span> {</span><br><span>        struct soc_intel_braswell_config *config = dev->chip_info;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-       printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span>  printk(BIOS_DEBUG, "eMMC init\n");</span><br><span>         reg_script_run_on_dev(dev, emmc_ops);</span><br><span>diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c</span><br><span>index b329531..895d2ee 100644</span><br><span>--- a/src/soc/intel/braswell/gfx.c</span><br><span>+++ b/src/soc/intel/braswell/gfx.c</span><br><span>@@ -49,7 +49,7 @@</span><br><span> </span><br><span> static void gfx_pre_vbios_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-   printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span>  printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");</span><br><span>        gfx_run_script(dev, gpu_pre_vbios_script);</span><br><span>@@ -57,7 +57,7 @@</span><br><span> </span><br><span> static void gfx_post_vbios_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-  printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span>  printk(BIOS_INFO, "GFX: Post VBIOS Init\n");</span><br><span>       gfx_run_script(dev, gfx_post_vbios_script);</span><br><span>@@ -65,7 +65,7 @@</span><br><span> </span><br><span> static void gfx_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> </span><br><span>      /* Pre VBIOS Init */</span><br><span>diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c</span><br><span>index 7c9f306..6338878 100644</span><br><span>--- a/src/soc/intel/braswell/lpe.c</span><br><span>+++ b/src/soc/intel/braswell/lpe.c</span><br><span>@@ -153,7 +153,7 @@</span><br><span> {</span><br><span>         struct soc_intel_braswell_config *config = dev->chip_info;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-       printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> </span><br><span>      lpe_stash_firmware_info(dev);</span><br><span>diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c</span><br><span>index aac953b..60ff49f 100644</span><br><span>--- a/src/soc/intel/braswell/lpss.c</span><br><span>+++ b/src/soc/intel/braswell/lpss.c</span><br><span>@@ -143,7 +143,7 @@</span><br><span>         struct soc_intel_braswell_config *config = dev->chip_info;</span><br><span>        int iosf_reg, nvs_index;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-    printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span>  printk(BIOS_SPEW, "%s - %s\n",</span><br><span>                     get_pci_class_name(dev),</span><br><span>diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c</span><br><span>index 1a127f4..efd891a 100644</span><br><span>--- a/src/soc/intel/braswell/pcie.c</span><br><span>+++ b/src/soc/intel/braswell/pcie.c</span><br><span>@@ -41,7 +41,7 @@</span><br><span> </span><br><span> static void pcie_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-     printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> }</span><br><span> </span><br><span>@@ -56,7 +56,7 @@</span><br><span> {</span><br><span>        int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-    printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> </span><br><span>      switch (root_port_offset(dev)) {</span><br><span>@@ -99,7 +99,7 @@</span><br><span> </span><br><span>     static uint32_t rootports_in_use = MAX_ROOT_PORTS_BSW;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-      printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span>  /* Set slot implemented. */</span><br><span>  pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI);</span><br><span>@@ -137,7 +137,7 @@</span><br><span> </span><br><span> static void pcie_enable(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span>  if (is_first_port(dev)) {</span><br><span>            struct soc_intel_braswell_config *config = dev->chip_info;</span><br><span>@@ -162,7 +162,7 @@</span><br><span> static void pcie_root_set_subsystem(struct device *dev, unsigned int vid,</span><br><span>     unsigned int did)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-  printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s, 0x%04x, 0x%04x)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev), vid, did);</span><br><span>        uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff);</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c</span><br><span>index 8052b29..2507641 100644</span><br><span>--- a/src/soc/intel/braswell/sata.c</span><br><span>+++ b/src/soc/intel/braswell/sata.c</span><br><span>@@ -30,7 +30,7 @@</span><br><span> </span><br><span> static void sata_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c</span><br><span>index 122c67e..17fc685 100644</span><br><span>--- a/src/soc/intel/braswell/scc.c</span><br><span>+++ b/src/soc/intel/braswell/scc.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span>        struct resource *bar;</span><br><span>        global_nvs_t *gnvs;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev), iosf_reg, nvs_index);</span><br><span> </span><br><span>         /* Find ACPI NVS to update BARs */</span><br><span>diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c</span><br><span>index 97c39b3..1775ce7 100644</span><br><span>--- a/src/soc/intel/braswell/sd.c</span><br><span>+++ b/src/soc/intel/braswell/sd.c</span><br><span>@@ -35,7 +35,7 @@</span><br><span> {</span><br><span>         struct soc_intel_braswell_config *config = dev->chip_info;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-       printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> </span><br><span>      if (config == NULL)</span><br><span>diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c</span><br><span>index 14b412a..ca87d63 100644</span><br><span>--- a/src/soc/intel/braswell/southcluster.c</span><br><span>+++ b/src/soc/intel/braswell/southcluster.c</span><br><span>@@ -55,14 +55,14 @@</span><br><span> add_mmio_resource(struct device *dev, int i, unsigned long addr,</span><br><span>                 unsigned long size)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-      printk(BIOS_SPEW, "%s/%s ( %s, 0x%016lx, 0x%016lx )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+     printk(BIOS_SPEW, "%s/%s (%s, 0x%016lx, 0x%016lx)\n",</span><br><span>                      __FILE__, __func__, dev_name(dev), addr, size);</span><br><span>      mmio_resource(dev, i, addr >> 10, size >> 10);</span><br><span> }</span><br><span> </span><br><span> static void sc_add_mmio_resources(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-       printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span>  add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);</span><br><span>  add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);</span><br><span>@@ -102,7 +102,7 @@</span><br><span> {</span><br><span>   struct resource *res;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-       printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x, 0x%08x )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x, 0x%08x)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev), base, size, index);</span><br><span> </span><br><span>   if (io_range_in_default(base, size))</span><br><span>@@ -118,7 +118,7 @@</span><br><span> {</span><br><span>      struct resource *res;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-       printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> </span><br><span>      /* Add the default claimed IO range for the LPC device. */</span><br><span>@@ -136,7 +136,7 @@</span><br><span> </span><br><span> static void sc_read_resources(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-  printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> </span><br><span>      /* Get the normal PCI resources of this device. */</span><br><span>@@ -165,7 +165,7 @@</span><br><span>     const struct soc_irq_route *ir = &global_soc_irq_route;</span><br><span>  struct soc_intel_braswell_config *config = dev->chip_info;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-       printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> </span><br><span>      /* Set up the PIRQ PIC routing based on static config. */</span><br><span>@@ -206,7 +206,7 @@</span><br><span>      uint32_t mask = 0;</span><br><span>   uint32_t mask2 = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> </span><br><span> #define SET_DIS_MASK(name_) \</span><br><span>@@ -292,7 +292,7 @@</span><br><span> {</span><br><span>  uint32_t reg8;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-      printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s, 0x%08x)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev), offset);</span><br><span>  printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);</span><br><span>         reg8 = pci_read_config8(dev, offset + 4);</span><br><span>@@ -309,7 +309,7 @@</span><br><span> {</span><br><span>         void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-     printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> </span><br><span>      /* Need to set magic register 0x43 to 0xd7 in config space. */</span><br><span>@@ -331,7 +331,7 @@</span><br><span> {</span><br><span>    unsigned int offset;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-        printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span> </span><br><span>      /*</span><br><span>@@ -410,7 +410,7 @@</span><br><span> {</span><br><span>        uint32_t reg32;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-     printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "%s/%s (%s)\n",</span><br><span>                  __FILE__, __func__, dev_name(dev));</span><br><span>  if (!dev->enabled) {</span><br><span>              int slot = PCI_SLOT(dev->path.pci.devfn);</span><br><span>@@ -461,7 +461,7 @@</span><br><span> </span><br><span> int __weak mainboard_get_spi_config(struct spi_config *cfg)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-      printk(BIOS_SPEW, "%s/%s ( 0x%p )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+       printk(BIOS_SPEW, "%s/%s (0x%p)\n",</span><br><span>                        __FILE__, __func__, (void *)cfg);</span><br><span>    return -1;</span><br><span> }</span><br><span>@@ -475,7 +475,7 @@</span><br><span>        uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS;</span><br><span>  struct spi_config cfg;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-      printk(BIOS_SPEW, "%s/%s ( 0x%p )\n",</span><br><span style="color: hsl(120, 100%, 40%);">+       printk(BIOS_SPEW, "%s/%s (0x%p)\n",</span><br><span>                        __FILE__, __func__, unused);</span><br><span> </span><br><span>     /* Set the lock enable on the BIOS control register. */</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c</span><br><span>index 6f0049f..8ce0a1d 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c</span><br><span>@@ -37,8 +37,8 @@</span><br><span>      * Check if INIT# is asserted by port 0xCF9 and whether RCBA has been set.</span><br><span>    * If either is true, then this is a warm reset so execute a Hard Reset</span><br><span>       */</span><br><span style="color: hsl(0, 100%, 40%);">-     if ( (inb(0xcf9) == 0x04) ||</span><br><span style="color: hsl(0, 100%, 40%);">-                    (pci_io_read_config32(LPC_BDF, RCBA) & RCBA_ENABLE) ) {</span><br><span style="color: hsl(120, 100%, 40%);">+   if ((inb(0xcf9) == 0x04) ||</span><br><span style="color: hsl(120, 100%, 40%);">+                   (pci_io_read_config32(LPC_BDF, RCBA) & RCBA_ENABLE)) {</span><br><span>           outb(0x00, 0xcf9);</span><br><span>           outb(0x06, 0xcf9);</span><br><span>   }</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c</span><br><span>index a7268aa..55bdbf1 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c</span><br><span>@@ -314,7 +314,7 @@</span><br><span> </span><br><span>         if (prev_sleep_state == ACPI_S3) {</span><br><span>           /* S3 resume */</span><br><span style="color: hsl(0, 100%, 40%);">-         if ( pFspInitParams->NvsBufferPtr == NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+               if (pFspInitParams->NvsBufferPtr == NULL) {</span><br><span>                       /* If waking from S3 and no cache then. */</span><br><span>                   printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n");</span><br><span>                   post_code(POST_RESUME_FAILURE);</span><br><span>@@ -322,7 +322,7 @@</span><br><span>                        outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) &</span><br><span>                          ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);</span><br><span>                    /* Reboot */</span><br><span style="color: hsl(0, 100%, 40%);">-                    printk(BIOS_WARNING,"Rebooting..\n" );</span><br><span style="color: hsl(120, 100%, 40%);">+                      printk(BIOS_WARNING,"Rebooting..\n");</span><br><span>                      warm_reset();</span><br><span>                        /* Should not reach here.. */</span><br><span>                        die("Reboot System\n");</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c</span><br><span>index 9f22b25..f909121 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/northcluster.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/northcluster.c</span><br><span>@@ -158,7 +158,7 @@</span><br><span>                     (bmbound - fsp_mem_base) >> 10);</span><br><span> </span><br><span>   if (highmem_size) {</span><br><span style="color: hsl(0, 100%, 40%);">-             ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10 );</span><br><span style="color: hsl(120, 100%, 40%);">+               ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10);</span><br><span>       }</span><br><span>    printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",</span><br><span>                   highmem_size >> 20);</span><br><span>diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c</span><br><span>index 7a25bfe..00fbde4 100644</span><br><span>--- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c</span><br><span>+++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c</span><br><span>@@ -589,9 +589,9 @@</span><br><span>                }</span><br><span> </span><br><span>        } else if (hold < setup) {</span><br><span style="color: hsl(0, 100%, 40%);">-           /* like this: (hold time != 0 )*/</span><br><span style="color: hsl(120, 100%, 40%);">+             /* like this: (hold time != 0)*/</span><br><span>             /* xxxoooooooooooooooooo|ooooooooxxxxxxxxxxxxxxxxx */</span><br><span style="color: hsl(0, 100%, 40%);">-           /* like this: (hold time == 0 ) */</span><br><span style="color: hsl(120, 100%, 40%);">+            /* like this: (hold time == 0) */</span><br><span>            /* xxxoooooooooooooooxxx|xxxxxxxxxxxxxxxxxxxxxxxxx */</span><br><span> </span><br><span>            p->best_dqsdly = 0;</span><br><span>@@ -1121,7 +1121,7 @@</span><br><span>       dramc_dbg_msg("DQ Delay :\n");</span><br><span>     for (i = 0; i < DATA_WIDTH_32BIT; i++) {</span><br><span>          dramc_dbg_msg("DQ%d = %d ", i, dqdqs_perbit_dly[i].best_dqdly);</span><br><span style="color: hsl(0, 100%, 40%);">-               if ( ((i + 1) % 4) == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+              if (((i + 1) % 4) == 0)</span><br><span>                      dramc_dbg_msg("\n");</span><br><span>       }</span><br><span> </span><br><span>diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c</span><br><span>index 536ad31..5cc5889 100644</span><br><span>--- a/src/soc/nvidia/tegra124/sdram_lp0.c</span><br><span>+++ b/src/soc/nvidia/tegra124/sdram_lp0.c</span><br><span>@@ -44,9 +44,9 @@</span><br><span> </span><br><span> #define pack(src, src_bits, dst, dst_bits) { \</span><br><span>     _Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \</span><br><span style="color: hsl(0, 100%, 40%);">-            (0 ? dst_bits), "byte range flipped (must be MSB:LSB)" ); \</span><br><span style="color: hsl(120, 100%, 40%);">+         (0 ? dst_bits), "byte range flipped (must be MSB:LSB)"); \</span><br><span>         _Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \</span><br><span style="color: hsl(0, 100%, 40%);">-            (0 ? dst_bits), "src and dst byte range lengths differ" ); \</span><br><span style="color: hsl(120, 100%, 40%);">+                (0 ? dst_bits), "src and dst byte range lengths differ"); \</span><br><span>        u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \</span><br><span>   dst &= ~(mask << (0 ? dst_bits)); \</span><br><span>        dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \</span><br><span>diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c</span><br><span>index c3a4dd4..9eaf5f0 100644</span><br><span>--- a/src/soc/nvidia/tegra210/sdram_lp0.c</span><br><span>+++ b/src/soc/nvidia/tegra210/sdram_lp0.c</span><br><span>@@ -32,9 +32,9 @@</span><br><span> </span><br><span> #define pack(src, src_bits, dst, dst_bits) { \</span><br><span>      _Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \</span><br><span style="color: hsl(0, 100%, 40%);">-            (0 ? dst_bits), "byte range flipped (must be MSB:LSB)" ); \</span><br><span style="color: hsl(120, 100%, 40%);">+         (0 ? dst_bits), "byte range flipped (must be MSB:LSB)"); \</span><br><span>         _Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \</span><br><span style="color: hsl(0, 100%, 40%);">-            (0 ? dst_bits), "src and dst byte range lengths differ" ); \</span><br><span style="color: hsl(120, 100%, 40%);">+                (0 ? dst_bits), "src and dst byte range lengths differ"); \</span><br><span>        u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \</span><br><span>   dst &= ~(mask << (0 ? dst_bits)); \</span><br><span>        dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \</span><br><span>diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c</span><br><span>index 63e30f6..a6cc3c7 100644</span><br><span>--- a/src/soc/samsung/exynos5250/clock.c</span><br><span>+++ b/src/soc/samsung/exynos5250/clock.c</span><br><span>@@ -617,7 +617,7 @@</span><br><span>      epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;</span><br><span> </span><br><span>     /*</span><br><span style="color: hsl(0, 100%, 40%);">-       * Required period ( in cycles) to generate a stable clock output.</span><br><span style="color: hsl(120, 100%, 40%);">+     * Required period (in cycles) to generate a stable clock output.</span><br><span>     * The maximum clock time can be up to 3000 * PDIV cycles of PLLs</span><br><span>     * frequency input (as per spec)</span><br><span>      */</span><br><span>diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c</span><br><span>index 3c4bb04..04125d9 100644</span><br><span>--- a/src/soc/samsung/exynos5420/clock.c</span><br><span>+++ b/src/soc/samsung/exynos5420/clock.c</span><br><span>@@ -582,7 +582,7 @@</span><br><span>       epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;</span><br><span> </span><br><span>     /*</span><br><span style="color: hsl(0, 100%, 40%);">-       * Required period ( in cycles) to generate a stable clock output.</span><br><span style="color: hsl(120, 100%, 40%);">+     * Required period (in cycles) to generate a stable clock output.</span><br><span>     * The maximum clock time can be up to 3000 * PDIV cycles of PLLs</span><br><span>     * frequency input (as per spec)</span><br><span>      */</span><br><span>diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c</span><br><span>index 1b6f5ae..30fcd37 100644</span><br><span>--- a/src/southbridge/amd/agesa/hudson/sm.c</span><br><span>+++ b/src/southbridge/amd/agesa/hudson/sm.c</span><br><span>@@ -45,8 +45,8 @@</span><br><span> #define BIT6        (1 << 6)</span><br><span> #define BIT7  (1 << 7)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define BIT8  (1 << 8 )</span><br><span style="color: hsl(0, 100%, 40%);">-#define BIT9     (1 << 9 )</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIT8   (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIT9    (1 << 9)</span><br><span> #define BIT10 (1 << 10)</span><br><span> #define BIT11        (1 << 11)</span><br><span> #define BIT12        (1 << 12)</span><br><span>diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c</span><br><span>index f3ba8b6..8a197b8 100644</span><br><span>--- a/src/southbridge/amd/amd8111/early_ctrl.c</span><br><span>+++ b/src/southbridge/amd/amd8111/early_ctrl.c</span><br><span>@@ -68,7 +68,7 @@</span><br><span> </span><br><span>         pci_write_config8(dev, 0x74, 4);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-    /* set VFSMAF ( VID/FID System Management Action Field) to 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+       /* set VFSMAF (VID/FID System Management Action Field) to 2 */</span><br><span>       pci_write_config32(dev, 0x70, 2<<12);</span><br><span> </span><br><span> }</span><br><span>diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c</span><br><span>index 52306ab..4f6b9d9 100644</span><br><span>--- a/src/southbridge/amd/amd8132/bridge.c</span><br><span>+++ b/src/southbridge/amd/amd8132/bridge.c</span><br><span>@@ -213,7 +213,7 @@</span><br><span>      if (chip_rev == 0x01) {</span><br><span>              /* Errata #37 */</span><br><span>             byte = pci_read_config8(dev, 0x0c);</span><br><span style="color: hsl(0, 100%, 40%);">-             if (byte == 0x08 )</span><br><span style="color: hsl(120, 100%, 40%);">+            if (byte == 0x08)</span><br><span>                    pci_write_config8(dev, 0x0c, 0x10);</span><br><span> </span><br><span> #if 0</span><br><span>@@ -385,7 +385,7 @@</span><br><span>       }</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-       if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {</span><br><span style="color: hsl(120, 100%, 40%);">+      if ((chip_rev == 0x11) ||(chip_rev == 0x12)) {</span><br><span>               //for b1 b2</span><br><span>          /* Errata #73 */</span><br><span>             dword = pci_read_config32(dev, 0x80);</span><br><span>diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c</span><br><span>index 977ffb6..db87b6a 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb800/fan.c</span><br><span>+++ b/src/southbridge/amd/cimx/sb800/fan.c</span><br><span>@@ -70,7 +70,7 @@</span><br><span>        *</span><br><span>    * Device 20, Function 3, Reg 0xA4</span><br><span>    * [0]: if 1, the address specified in IMC_PortAddress is used.</span><br><span style="color: hsl(0, 100%, 40%);">-  * [15:1] IMC_PortAddress bits 15:1 (0x17 - address 0x2E )</span><br><span style="color: hsl(120, 100%, 40%);">+     * [15:1] IMC_PortAddress bits 15:1 (0x17 - address 0x2E)</span><br><span>     */</span><br><span> </span><br><span>      pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01);</span><br><span>@@ -102,7 +102,7 @@</span><br><span>    sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00;</span><br><span>     sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0;</span><br><span>        message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2;</span><br><span style="color: hsl(0, 100%, 40%);">-    for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )</span><br><span style="color: hsl(120, 100%, 40%);">+        for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)</span><br><span>                *(message_ptr + i) = sb_chip->imc_zone0_config_vals[i];</span><br><span> </span><br><span>       /* EC LDN9 function 83 zone 0 - Temperature Thresholds */</span><br><span>@@ -110,14 +110,14 @@</span><br><span>    sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0;</span><br><span>        sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00;</span><br><span>     message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2;</span><br><span style="color: hsl(0, 100%, 40%);">-    for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )</span><br><span style="color: hsl(120, 100%, 40%);">+     for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)</span><br><span>             *(message_ptr + i) = sb_chip->imc_zone0_thresholds[i];</span><br><span> </span><br><span>        /*EC LDN9 function 85 zone 0 - Fan Speeds */</span><br><span>         sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00;</span><br><span>     sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0;</span><br><span>        message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2;</span><br><span style="color: hsl(0, 100%, 40%);">-    for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)</span><br><span>                 *(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i];</span><br><span> </span><br><span> }</span><br><span>@@ -133,7 +133,7 @@</span><br><span>      sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00;</span><br><span>     sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1;</span><br><span>        message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2;</span><br><span style="color: hsl(0, 100%, 40%);">-    for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )</span><br><span style="color: hsl(120, 100%, 40%);">+        for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)</span><br><span>                *(message_ptr + i) = sb_chip->imc_zone1_config_vals[i];</span><br><span> </span><br><span>       /* EC LDN9 function 83 zone 1 - Temperature Thresholds */</span><br><span>@@ -141,14 +141,14 @@</span><br><span>    sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1;</span><br><span>        sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00;</span><br><span>     message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2;</span><br><span style="color: hsl(0, 100%, 40%);">-    for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )</span><br><span style="color: hsl(120, 100%, 40%);">+     for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)</span><br><span>             *(message_ptr + i) = sb_chip->imc_zone1_thresholds[i];</span><br><span> </span><br><span>        /* EC LDN9 function 85 zone 1 - Fan Speeds */</span><br><span>        sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00;</span><br><span>     sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1;</span><br><span>        message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2;</span><br><span style="color: hsl(0, 100%, 40%);">-    for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)</span><br><span>                 *(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i];</span><br><span> </span><br><span> }</span><br><span>@@ -165,7 +165,7 @@</span><br><span>      sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00;</span><br><span>     sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2;</span><br><span>        message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2;</span><br><span style="color: hsl(0, 100%, 40%);">-    for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )</span><br><span style="color: hsl(120, 100%, 40%);">+        for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)</span><br><span>                *(message_ptr + i) = sb_chip->imc_zone2_config_vals[i];</span><br><span> </span><br><span>       /* EC LDN9 function 83 zone 2 */</span><br><span>@@ -173,14 +173,14 @@</span><br><span>     sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2;</span><br><span>        sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00;</span><br><span>     message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2;</span><br><span style="color: hsl(0, 100%, 40%);">-    for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )</span><br><span style="color: hsl(120, 100%, 40%);">+     for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)</span><br><span>             *(message_ptr + i) = sb_chip->imc_zone2_thresholds[i];</span><br><span> </span><br><span>        /* EC LDN9 function 85 zone 2 */</span><br><span>     sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00;</span><br><span>     sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2;</span><br><span>        message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2;</span><br><span style="color: hsl(0, 100%, 40%);">-    for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)</span><br><span>                 *(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i];</span><br><span> </span><br><span> }</span><br><span>@@ -197,7 +197,7 @@</span><br><span>      sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00;</span><br><span>     sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3;</span><br><span>        message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2;</span><br><span style="color: hsl(0, 100%, 40%);">-    for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )</span><br><span style="color: hsl(120, 100%, 40%);">+        for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)</span><br><span>                *(message_ptr + i) = sb_chip->imc_zone3_config_vals[i];</span><br><span> </span><br><span>       /* EC LDN9 function 83 zone 3 */</span><br><span>@@ -205,14 +205,14 @@</span><br><span>     sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3;</span><br><span>        sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00;</span><br><span>     message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2;</span><br><span style="color: hsl(0, 100%, 40%);">-    for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )</span><br><span style="color: hsl(120, 100%, 40%);">+     for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)</span><br><span>             *(message_ptr + i) = sb_chip->imc_zone3_thresholds[i];</span><br><span> </span><br><span>        /* EC LDN9 function 85 zone 3 */</span><br><span>     sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00;</span><br><span>     sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3;</span><br><span>        message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2;</span><br><span style="color: hsl(0, 100%, 40%);">-    for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)</span><br><span>                 *(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i];</span><br><span> </span><br><span> }</span><br><span>@@ -231,11 +231,11 @@</span><br><span>    /* EC LDN9 function 89 TEMPIN channel 0 */</span><br><span>   sb_config.Pecstruct.MSGFun89zone0MSGREG0 = 0x00;</span><br><span>     sb_config.Pecstruct.MSGFun89zone0MSGREG1 = 0x00;</span><br><span style="color: hsl(0, 100%, 40%);">-        sb_config.Pecstruct.MSGFun89zone0MSGREG2 = ( sb_chip->imc_tempin0_at & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+  sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff);</span><br><span>  sb_config.Pecstruct.MSGFun89zone0MSGREG3 = ((sb_chip->imc_tempin0_at >> 8)  & 0xff);</span><br><span>    sb_config.Pecstruct.MSGFun89zone0MSGREG4 = ((sb_chip->imc_tempin0_at >> 16) & 0xff);</span><br><span>    sb_config.Pecstruct.MSGFun89zone0MSGREG5 = ((sb_chip->imc_tempin0_at >> 24) & 0xff);</span><br><span style="color: hsl(0, 100%, 40%);">-       sb_config.Pecstruct.MSGFun89zone0MSGREG6 = ( sb_chip->imc_tempin0_ct & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+  sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff);</span><br><span>  sb_config.Pecstruct.MSGFun89zone0MSGREG7 = ((sb_chip->imc_tempin0_ct >> 8)  & 0xff);</span><br><span>    sb_config.Pecstruct.MSGFun89zone0MSGREG8 = ((sb_chip->imc_tempin0_ct >> 16)  & 0xff);</span><br><span>   sb_config.Pecstruct.MSGFun89zone0MSGREG9 = ((sb_chip->imc_tempin0_ct >> 24)  & 0xff);</span><br><span>@@ -249,11 +249,11 @@</span><br><span>   /* EC LDN9 function 89 TEMPIN channel 1 */</span><br><span>   sb_config.Pecstruct.MSGFun89zone1MSGREG0 = 0x00;</span><br><span>     sb_config.Pecstruct.MSGFun89zone1MSGREG1 = 0x01;</span><br><span style="color: hsl(0, 100%, 40%);">-        sb_config.Pecstruct.MSGFun89zone1MSGREG2 = ( sb_chip->imc_tempin1_at & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+  sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff);</span><br><span>  sb_config.Pecstruct.MSGFun89zone1MSGREG3 = ((sb_chip->imc_tempin1_at >> 8)  & 0xff);</span><br><span>    sb_config.Pecstruct.MSGFun89zone1MSGREG4 = ((sb_chip->imc_tempin1_at >> 16) & 0xff);</span><br><span>    sb_config.Pecstruct.MSGFun89zone1MSGREG5 = ((sb_chip->imc_tempin1_at >> 24) & 0xff);</span><br><span style="color: hsl(0, 100%, 40%);">-       sb_config.Pecstruct.MSGFun89zone1MSGREG6 = ( sb_chip->imc_tempin1_ct & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+  sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff);</span><br><span>  sb_config.Pecstruct.MSGFun89zone1MSGREG7 = ((sb_chip->imc_tempin1_ct >> 8)  & 0xff);</span><br><span>    sb_config.Pecstruct.MSGFun89zone1MSGREG8 = ((sb_chip->imc_tempin1_ct >> 16)  & 0xff);</span><br><span>   sb_config.Pecstruct.MSGFun89zone1MSGREG9 = ((sb_chip->imc_tempin1_ct >> 24)  & 0xff);</span><br><span>@@ -267,11 +267,11 @@</span><br><span>   /* EC LDN9 function 89 TEMPIN channel 2 */</span><br><span>   sb_config.Pecstruct.MSGFun89zone2MSGREG0 = 0x00;</span><br><span>     sb_config.Pecstruct.MSGFun89zone2MSGREG1 = 0x02;</span><br><span style="color: hsl(0, 100%, 40%);">-        sb_config.Pecstruct.MSGFun89zone2MSGREG2 = ( sb_chip->imc_tempin2_at & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+  sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff);</span><br><span>  sb_config.Pecstruct.MSGFun89zone2MSGREG3 = ((sb_chip->imc_tempin2_at >> 8)  & 0xff);</span><br><span>    sb_config.Pecstruct.MSGFun89zone2MSGREG4 = ((sb_chip->imc_tempin2_at >> 16) & 0xff);</span><br><span>    sb_config.Pecstruct.MSGFun89zone2MSGREG5 = ((sb_chip->imc_tempin2_at >> 24) & 0xff);</span><br><span style="color: hsl(0, 100%, 40%);">-       sb_config.Pecstruct.MSGFun89zone2MSGREG6 = ( sb_chip->imc_tempin2_ct & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+  sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff);</span><br><span>  sb_config.Pecstruct.MSGFun89zone2MSGREG7 = ((sb_chip->imc_tempin2_ct >> 8)  & 0xff);</span><br><span>    sb_config.Pecstruct.MSGFun89zone2MSGREG8 = ((sb_chip->imc_tempin2_ct >> 16)  & 0xff);</span><br><span>   sb_config.Pecstruct.MSGFun89zone2MSGREG9 = ((sb_chip->imc_tempin2_ct >> 24)  & 0xff);</span><br><span>@@ -285,11 +285,11 @@</span><br><span>   /* EC LDN9 function 89 TEMPIN channel 3 */</span><br><span>   sb_config.Pecstruct.MSGFun89zone3MSGREG0 = 0x00;</span><br><span>     sb_config.Pecstruct.MSGFun89zone3MSGREG1 = 0x03;</span><br><span style="color: hsl(0, 100%, 40%);">-        sb_config.Pecstruct.MSGFun89zone3MSGREG2 = ( sb_chip->imc_tempin3_at & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+  sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff);</span><br><span>  sb_config.Pecstruct.MSGFun89zone3MSGREG3 = ((sb_chip->imc_tempin3_at >> 8)  & 0xff);</span><br><span>    sb_config.Pecstruct.MSGFun89zone3MSGREG4 = ((sb_chip->imc_tempin3_at >> 16) & 0xff);</span><br><span>    sb_config.Pecstruct.MSGFun89zone3MSGREG5 = ((sb_chip->imc_tempin3_at >> 24) & 0xff);</span><br><span style="color: hsl(0, 100%, 40%);">-       sb_config.Pecstruct.MSGFun89zone3MSGREG6 = ( sb_chip->imc_tempin3_ct & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+  sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff);</span><br><span>  sb_config.Pecstruct.MSGFun89zone3MSGREG7 = ((sb_chip->imc_tempin3_ct >> 8)  & 0xff);</span><br><span>    sb_config.Pecstruct.MSGFun89zone3MSGREG8 = ((sb_chip->imc_tempin3_ct >> 16)  & 0xff);</span><br><span>   sb_config.Pecstruct.MSGFun89zone3MSGREG9 = ((sb_chip->imc_tempin3_ct >> 24)  & 0xff);</span><br><span>diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c</span><br><span>index 865b577..017c764 100644</span><br><span>--- a/src/southbridge/amd/rs780/early_setup.c</span><br><span>+++ b/src/southbridge/amd/rs780/early_setup.c</span><br><span>@@ -35,7 +35,7 @@</span><br><span> </span><br><span> static void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-     pci_write_config32(dev, index_reg, index /* | 0x80 */ );</span><br><span style="color: hsl(120, 100%, 40%);">+      pci_write_config32(dev, index_reg, index /* | 0x80 */);</span><br><span>      pci_write_config32(dev, index_reg + 0x4, data);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c</span><br><span>index 43bfb02..a765655 100644</span><br><span>--- a/src/southbridge/amd/rs780/gfx.c</span><br><span>+++ b/src/southbridge/amd/rs780/gfx.c</span><br><span>@@ -247,7 +247,7 @@</span><br><span>                      }</span><br><span>            }</span><br><span>            if (pMMIO[k].Limit != 0) {</span><br><span style="color: hsl(0, 100%, 40%);">-                      if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 ) {</span><br><span style="color: hsl(120, 100%, 40%);">+                        if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) {</span><br><span>                                Base = 0;</span><br><span>                    }</span><br><span>                    else</span><br><span>diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c</span><br><span>index 1d1ac13..57dd7bc 100644</span><br><span>--- a/src/southbridge/amd/sb700/sata.c</span><br><span>+++ b/src/southbridge/amd/sb700/sata.c</span><br><span>@@ -461,7 +461,7 @@</span><br><span>                      else</span><br><span>                                 printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",</span><br><span>                                             (i / 2) ? "Secondary" : "Primary",</span><br><span style="color: hsl(0, 100%, 40%);">-                                          (i % 2 ) ? "Slave" : "Master",</span><br><span style="color: hsl(120, 100%, 40%);">+                                            (i % 2) ? "Slave" : "Master",</span><br><span>                                            (j == 10) ? "not " : "",</span><br><span>                                                 (j == 10) ? j : j + 1);</span><br><span>              } else {</span><br><span>@@ -470,7 +470,7 @@</span><br><span>                       else</span><br><span>                                 printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",</span><br><span>                                              (i / 2) ? "Secondary" : "Primary",</span><br><span style="color: hsl(0, 100%, 40%);">-                                          (i % 2 ) ? "Slave" : "Master", i);</span><br><span style="color: hsl(120, 100%, 40%);">+                                                (i % 2) ? "Slave" : "Master", i);</span><br><span>                }</span><br><span>    }</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c</span><br><span>index 15b2527..8e6009a 100644</span><br><span>--- a/src/southbridge/amd/sb800/sata.c</span><br><span>+++ b/src/southbridge/amd/sb800/sata.c</span><br><span>@@ -177,7 +177,7 @@</span><br><span>             byte = read8(sata_bar5 + 0x128 + 0x80 * i);</span><br><span>          printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);</span><br><span>          byte &= 0xF;</span><br><span style="color: hsl(0, 100%, 40%);">-                if ( byte == 0x1 ) {</span><br><span style="color: hsl(120, 100%, 40%);">+          if (byte == 0x1) {</span><br><span>                   /* If the drive status is 0x1 then we see it but we aren't talking to it. */</span><br><span>                     /* Try to do something about it. */</span><br><span>                  printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");</span><br><span>@@ -212,13 +212,13 @@</span><br><span>                  }</span><br><span>                    printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",</span><br><span>                                     (i / 2) ? "Secondary" : "Primary",</span><br><span style="color: hsl(0, 100%, 40%);">-                                  (i % 2 ) ? "Slave" : "Master",</span><br><span style="color: hsl(120, 100%, 40%);">+                                    (i % 2) ? "Slave" : "Master",</span><br><span>                                    (j == 10) ? "not " : "",</span><br><span>                                         (j == 10) ? j : j + 1);</span><br><span>              } else {</span><br><span>                     printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",</span><br><span>                                      (i / 2) ? "Secondary" : "Primary",</span><br><span style="color: hsl(0, 100%, 40%);">-                                  (i % 2 ) ? "Slave" : "Master", i);</span><br><span style="color: hsl(120, 100%, 40%);">+                                        (i % 2) ? "Slave" : "Master", i);</span><br><span>                }</span><br><span>    }</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c</span><br><span>index d4ed3cc..fdb6283 100644</span><br><span>--- a/src/southbridge/amd/sb800/sm.c</span><br><span>+++ b/src/southbridge/amd/sb800/sm.c</span><br><span>@@ -45,8 +45,8 @@</span><br><span> #define BIT6  (1 << 6)</span><br><span> #define BIT7  (1 << 7)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define BIT8  (1 << 8 )</span><br><span style="color: hsl(0, 100%, 40%);">-#define BIT9     (1 << 9 )</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIT8   (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIT9    (1 << 9)</span><br><span> #define BIT10 (1 << 10)</span><br><span> #define BIT11        (1 << 11)</span><br><span> #define BIT12        (1 << 12)</span><br><span>diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c</span><br><span>index 8986e67..159f3e4 100644</span><br><span>--- a/src/southbridge/amd/sr5650/pcie.c</span><br><span>+++ b/src/southbridge/amd/sr5650/pcie.c</span><br><span>@@ -665,7 +665,7 @@</span><br><span>       /* CIMx CommonPortInit settings that are not set above. */</span><br><span>   pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1 << 0); /* LINK_CRTL2 */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-     if ( port == 8 )</span><br><span style="color: hsl(120, 100%, 40%);">+      if (port == 8)</span><br><span>               set_pcie_enable_bits(dev, 0xA0, 0, 1 << 23);</span><br><span> </span><br><span> #if 0 //SR56x0 pcie Gen2 code is not tested yet, we should enable it again when test finished.</span><br><span>@@ -687,7 +687,7 @@</span><br><span>       pci_ext_write_config32(nb_dev, dev, 0x74, 1 << 3, 1 << 3);</span><br><span> </span><br><span>   /* 5.12.9.3 step 2 - PCIEP_PORT_CNTL - enable hotplug messages */</span><br><span style="color: hsl(0, 100%, 40%);">-       if ( port != 8)</span><br><span style="color: hsl(120, 100%, 40%);">+       if (port != 8)</span><br><span>               set_pcie_enable_bits(dev, 0x10, 1 << 2, 1 << 2);</span><br><span> </span><br><span>     /* Not sure about this PME setup */</span><br><span>@@ -806,7 +806,7 @@</span><br><span>    set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 1 << 6, 1 << 6);</span><br><span> </span><br><span>     /* Step 20: Disables immediate RCB timeout on link down */</span><br><span style="color: hsl(0, 100%, 40%);">-      if (!((pci_read_config32(dev, 0x6C ) >> 6) & 0x01)) {</span><br><span style="color: hsl(120, 100%, 40%);">+       if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) {</span><br><span>               set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19);</span><br><span>       }</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c</span><br><span>index 3477c52..5b95c57 100644</span><br><span>--- a/src/southbridge/intel/i82371eb/smbus.c</span><br><span>+++ b/src/southbridge/intel/i82371eb/smbus.c</span><br><span>@@ -68,7 +68,7 @@</span><br><span>        * power-on default is 0x7fffbfffh */</span><br><span>        if (gpo) {</span><br><span>           /* only 8bit access allowed */</span><br><span style="color: hsl(0, 100%, 40%);">-          outb( gpo        & 0xff, DEFAULT_PMBASE + GPO0);</span><br><span style="color: hsl(120, 100%, 40%);">+          outb(gpo        & 0xff, DEFAULT_PMBASE + GPO0);</span><br><span>          outb((gpo >>  8) & 0xff, DEFAULT_PMBASE + GPO1);</span><br><span>           outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2);</span><br><span>           outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3);</span><br><span>diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c</span><br><span>index bdbcba7..361bed3 100644</span><br><span>--- a/src/southbridge/ricoh/rl5c476/rl5c476.c</span><br><span>+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c</span><br><span>@@ -166,7 +166,7 @@</span><br><span>    /* For CF socket we need an extra memory window for</span><br><span>   * the control structure of the CF itself</span><br><span>     */</span><br><span style="color: hsl(0, 100%, 40%);">-     if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){</span><br><span style="color: hsl(120, 100%, 40%);">+      if (enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){</span><br><span>              /* fake index as it isn't in PCI config space */</span><br><span>                 resource = new_resource(dev, 1);</span><br><span>             resource->flags |= IORESOURCE_MEM;</span><br><span>@@ -181,9 +181,9 @@</span><br><span> {</span><br><span>     struct resource *resource;</span><br><span>   printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev));</span><br><span style="color: hsl(0, 100%, 40%);">-    if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){</span><br><span style="color: hsl(120, 100%, 40%);">+      if (enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){</span><br><span>              resource = find_resource(dev,1);</span><br><span style="color: hsl(0, 100%, 40%);">-                if ( !(resource->flags & IORESOURCE_STORED) ){</span><br><span style="color: hsl(120, 100%, 40%);">+         if (!(resource->flags & IORESOURCE_STORED)){</span><br><span>                  resource->flags |= IORESOURCE_STORED;</span><br><span>                     printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base);</span><br><span>                        cf_base = resource->base;</span><br><span>diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c</span><br><span>index acd2ab4..82438e4 100644</span><br><span>--- a/src/superio/serverengines/pilot/early_init.c</span><br><span>+++ b/src/superio/serverengines/pilot/early_init.c</span><br><span>@@ -59,7 +59,7 @@</span><br><span>        pnp_set_logical_device(PNP_DEV(port, 0x4));</span><br><span>  pnp_exit_ext_func_mode(dev);</span><br><span>         pnp_enter_ext_func_mode(dev);</span><br><span style="color: hsl(0, 100%, 40%);">-   pnp_set_enable( PNP_DEV(port, 0x4), 0);</span><br><span style="color: hsl(120, 100%, 40%);">+       pnp_set_enable(PNP_DEV(port, 0x4), 0);</span><br><span>       pnp_exit_ext_func_mode(dev);</span><br><span> </span><br><span>     pnp_enter_ext_func_mode(dev);</span><br><span>diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c</span><br><span>index eea9dce..0ebd207 100644</span><br><span>--- a/src/superio/smsc/sch4037/sch4037_early_init.c</span><br><span>+++ b/src/superio/smsc/sch4037/sch4037_early_init.c</span><br><span>@@ -41,7 +41,7 @@</span><br><span> </span><br><span>       /* Auto power management */</span><br><span>  pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */</span><br><span style="color: hsl(0, 100%, 40%);">- pnp_write_config(dev, 0x23, 0 );</span><br><span style="color: hsl(120, 100%, 40%);">+      pnp_write_config(dev, 0x23, 0);</span><br><span> </span><br><span>  /* Enable SMSC UART 0 */</span><br><span>     dev = PNP_DEV(port, SMSCSUPERIO_SP1);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29161">change 29161</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29161"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d </div>
<div style="display:none"> Gerrit-Change-Number: 29161 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>