<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29169">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel: Use CF9 reset (part 2)<br><br>Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also<br>implement board_reset() as a "full reset" (aka. cold reset) as that<br>is what was used here for hard_reset().<br><br>We leave some comments to remind us that a system_reset() should<br>be enough, where a full_reset() is called now to retain current<br>behaviour.<br><br>Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/drivers/intel/fsp1_1/raminit.c<br>M src/drivers/intel/fsp1_1/romstage.c<br>M src/drivers/intel/fsp2_0/memory_init.c<br>M src/drivers/intel/fsp2_0/util.c<br>D src/include/cpu/intel/reset.h<br>M src/include/reset.h<br>M src/lib/reset.c<br>M src/soc/intel/apollolake/Kconfig<br>M src/soc/intel/apollolake/reset.c<br>M src/soc/intel/apollolake/romstage.c<br>M src/soc/intel/braswell/Kconfig<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/reset.c<br>M src/soc/intel/common/Kconfig<br>M src/soc/intel/common/block/acpi/acpi.c<br>M src/soc/intel/common/reset.c<br>M src/soc/intel/denverton_ns/Kconfig<br>M src/soc/intel/denverton_ns/reset.c<br>M src/soc/intel/denverton_ns/romstage.c<br>M src/soc/intel/quark/Kconfig<br>M src/soc/intel/quark/reset.c<br>M src/soc/intel/skylake/Kconfig<br>M src/soc/intel/skylake/reset.c<br>23 files changed, 52 insertions(+), 107 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29169/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c</span><br><span>index 407a0b6..344fc84 100644</span><br><span>--- a/src/drivers/intel/fsp1_1/raminit.c</span><br><span>+++ b/src/drivers/intel/fsp1_1/raminit.c</span><br><span>@@ -15,12 +15,12 @@</span><br><span> </span><br><span> #include <arch/acpi.h></span><br><span> #include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span> #include <console/console.h></span><br><span> #include <fsp/memmap.h></span><br><span> #include <fsp/romstage.h></span><br><span> #include <fsp/util.h></span><br><span> #include <lib.h> /* hexdump */</span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <string.h></span><br><span> #include <timestamp.h></span><br><span> #include <security/vboot/vboot_common.h></span><br><span>@@ -164,7 +164,8 @@</span><br><span> #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)</span><br><span> printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");</span><br><span> /* Failed S3 resume, reset to come up cleanly */</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FIXME: A "system" reset is likely enough: */</span><br><span style="color: hsl(120, 100%, 40%);">+ full_reset();</span><br><span> #endif</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c</span><br><span>index b239d86..4cd98a9 100644</span><br><span>--- a/src/drivers/intel/fsp1_1/romstage.c</span><br><span>+++ b/src/drivers/intel/fsp1_1/romstage.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <assert.h></span><br><span> #include <console/console.h></span><br><span> #include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span> #include <cpu/intel/microcode.h></span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <ec/google/chromeec/ec.h></span><br><span>@@ -29,7 +30,6 @@</span><br><span> #include <elog.h></span><br><span> #include <fsp/romstage.h></span><br><span> #include <mrc_cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <program_loading.h></span><br><span> #include <romstage_handoff.h></span><br><span> #include <smbios.h></span><br><span>@@ -134,7 +134,8 @@</span><br><span> printk(BIOS_DEBUG,</span><br><span> "No MRC cache found in S3 resume path.\n");</span><br><span> post_code(POST_RESUME_FAILURE);</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FIXME: A "system" reset is likely enough: */</span><br><span style="color: hsl(120, 100%, 40%);">+ full_reset();</span><br><span> } else {</span><br><span> printk(BIOS_DEBUG, "No MRC cache found.\n");</span><br><span> }</span><br><span>@@ -164,7 +165,8 @@</span><br><span> /* Create romstage handof information */</span><br><span> if (romstage_handoff_init(</span><br><span> params->power_state->prev_sleep_state == ACPI_S3) < 0)</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FIXME: A "system" reset is likely enough: */</span><br><span style="color: hsl(120, 100%, 40%);">+ full_reset();</span><br><span> }</span><br><span> </span><br><span> void after_cache_as_ram_stage(void)</span><br><span>diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c</span><br><span>index dc37eaa..fbd69d1 100644</span><br><span>--- a/src/drivers/intel/fsp2_0/memory_init.c</span><br><span>+++ b/src/drivers/intel/fsp2_0/memory_init.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> #include <assert.h></span><br><span> #include <cbfs.h></span><br><span> #include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span> #include <console/console.h></span><br><span> #include <elog.h></span><br><span> #include <fsp/api.h></span><br><span>@@ -25,7 +26,6 @@</span><br><span> #include <memrange.h></span><br><span> #include <mrc_cache.h></span><br><span> #include <program_loading.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <romstage_handoff.h></span><br><span> #include <string.h></span><br><span> #include <symbols.h></span><br><span>@@ -80,7 +80,8 @@</span><br><span> printk(BIOS_ERR,</span><br><span> "Failed to recover CBMEM in S3 resume.\n");</span><br><span> /* Failed S3 resume, reset to come up cleanly */</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FIXME: A "system" reset is likely enough: */</span><br><span style="color: hsl(120, 100%, 40%);">+ full_reset();</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>@@ -214,7 +215,8 @@</span><br><span> * returning error. Invoking a reset here saves time.</span><br><span> */</span><br><span> if (!arch_upd->NvsBufferPtr)</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FIXME: A "system" reset is likely enough: */</span><br><span style="color: hsl(120, 100%, 40%);">+ full_reset();</span><br><span> arch_upd->BootMode = FSP_BOOT_ON_S3_RESUME;</span><br><span> } else {</span><br><span> if (arch_upd->NvsBufferPtr)</span><br><span>diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c</span><br><span>index f84d69c..98026f3 100644</span><br><span>--- a/src/drivers/intel/fsp2_0/util.c</span><br><span>+++ b/src/drivers/intel/fsp2_0/util.c</span><br><span>@@ -13,10 +13,10 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <cbfs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span> #include <console/console.h></span><br><span> #include <fsp/util.h></span><br><span> #include <lib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <string.h></span><br><span> </span><br><span> static bool looks_like_fsp_header(const uint8_t *raw_hdr)</span><br><span>@@ -109,10 +109,10 @@</span><br><span> </span><br><span> switch (status) {</span><br><span> case FSP_STATUS_RESET_REQUIRED_COLD:</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ full_reset();</span><br><span> break;</span><br><span> case FSP_STATUS_RESET_REQUIRED_WARM:</span><br><span style="color: hsl(0, 100%, 40%);">- soft_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ system_reset();</span><br><span> break;</span><br><span> case FSP_STATUS_RESET_REQUIRED_3:</span><br><span> case FSP_STATUS_RESET_REQUIRED_4:</span><br><span>diff --git a/src/include/cpu/intel/reset.h b/src/include/cpu/intel/reset.h</span><br><span>deleted file mode 100644</span><br><span>index 9cf6168..0000000</span><br><span>--- a/src/include/cpu/intel/reset.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,26 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corp.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef CPU_INTEL_RESET_H</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_INTEL_RESET_H</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Reset control port */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_CNT 0xcf9</span><br><span style="color: hsl(0, 100%, 40%);">-#define FULL_RST (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_CPU (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SYS_RST (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* CPU_INTEL_RESET_H */</span><br><span>diff --git a/src/include/reset.h b/src/include/reset.h</span><br><span>index fe6328d..3eec193 100644</span><br><span>--- a/src/include/reset.h</span><br><span>+++ b/src/include/reset.h</span><br><span>@@ -39,8 +39,6 @@</span><br><span> */</span><br><span> void do_board_reset(void);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Super-hard reset specific to some Intel SoCs. */</span><br><span style="color: hsl(0, 100%, 40%);">-__noreturn void global_reset(void);</span><br><span> /* Full board reset. Resets SoC and most/all board components (e.g. DRAM). */</span><br><span> __noreturn void hard_reset(void);</span><br><span> /* Board reset. Resets SoC some board components (e.g. TPM but not DRAM). */</span><br><span>@@ -48,19 +46,7 @@</span><br><span> </span><br><span> /* Reset implementations. Implement these in SoC or mainboard code. Implement</span><br><span> at least hard_reset() if possible, others fall back to it if necessary. */</span><br><span style="color: hsl(0, 100%, 40%);">-void do_global_reset(void);</span><br><span> void do_hard_reset(void);</span><br><span> void do_soft_reset(void);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-enum reset_type { /* listed in order of softness */</span><br><span style="color: hsl(0, 100%, 40%);">- GLOBAL_RESET,</span><br><span style="color: hsl(0, 100%, 40%);">- HARD_RESET,</span><br><span style="color: hsl(0, 100%, 40%);">- SOFT_RESET,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Callback that an SoC may override to perform special actions before reset.</span><br><span style="color: hsl(0, 100%, 40%);">- Take into account that softer resets may fall back to harder resets if not</span><br><span style="color: hsl(0, 100%, 40%);">- implemented... this will *not* trigger another callback! */</span><br><span style="color: hsl(0, 100%, 40%);">-void soc_reset_prepare(enum reset_type reset_type);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #endif</span><br><span>diff --git a/src/lib/reset.c b/src/lib/reset.c</span><br><span>index 283f72c..4b19e1e 100644</span><br><span>--- a/src/lib/reset.c</span><br><span>+++ b/src/lib/reset.c</span><br><span>@@ -51,24 +51,11 @@</span><br><span> }</span><br><span> </span><br><span> /* Not all platforms implement all reset types. Fall back to hard_reset. */</span><br><span style="color: hsl(0, 100%, 40%);">-__weak void do_global_reset(void) { __hard_reset(); }</span><br><span> __weak void do_soft_reset(void) { __hard_reset(); }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-__weak void soc_reset_prepare(enum reset_type rt) { /* no-op */ }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void global_reset(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "%s() called!\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">- soc_reset_prepare(GLOBAL_RESET);</span><br><span style="color: hsl(0, 100%, 40%);">- dcache_clean_all();</span><br><span style="color: hsl(0, 100%, 40%);">- do_global_reset();</span><br><span style="color: hsl(0, 100%, 40%);">- halt();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void hard_reset(void)</span><br><span> {</span><br><span> printk(BIOS_INFO, "%s() called!\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">- soc_reset_prepare(HARD_RESET);</span><br><span> dcache_clean_all();</span><br><span> __hard_reset();</span><br><span> }</span><br><span>@@ -76,7 +63,6 @@</span><br><span> void soft_reset(void)</span><br><span> {</span><br><span> printk(BIOS_INFO, "%s() called!\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">- soc_reset_prepare(SOFT_RESET);</span><br><span> dcache_clean_all();</span><br><span> do_soft_reset();</span><br><span> halt();</span><br><span>diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig</span><br><span>index fbc81ce..e70e8ae 100644</span><br><span>--- a/src/soc/intel/apollolake/Kconfig</span><br><span>+++ b/src/soc/intel/apollolake/Kconfig</span><br><span>@@ -104,7 +104,8 @@</span><br><span> select PLATFORM_USES_FSP2_0</span><br><span> select UDK_2015_BINDING if !SOC_INTEL_GLK</span><br><span> select UDK_2017_BINDING if SOC_INTEL_GLK</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_RESET</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CF9_RESET_PREPARE</span><br><span> select INTEL_GMA_ADD_VBT if RUN_FSP_GOP</span><br><span> select HAVE_FSP_GOP</span><br><span> select NO_UART_ON_SUPERIO</span><br><span>@@ -130,10 +131,6 @@</span><br><span> TPM part is conntected on Fast SPI interface, but the LPC MMIO</span><br><span> TPM transactions are decoded and serialized over the SPI interface.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config SOC_INTEL_COMMON_RESET</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">- default y</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config PCR_BASE_ADDRESS</span><br><span> hex</span><br><span> default 0xd0000000</span><br><span>diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c</span><br><span>index 6ea7a59..36bf77b 100644</span><br><span>--- a/src/soc/intel/apollolake/reset.c</span><br><span>+++ b/src/soc/intel/apollolake/reset.c</span><br><span>@@ -13,12 +13,13 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span> #include <console/console.h></span><br><span> #include <delay.h></span><br><span> #include <fsp/util.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <soc/heci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/common/reset.h></span><br><span> #include <soc/pm.h></span><br><span> #include <timer.h></span><br><span> </span><br><span>@@ -27,10 +28,10 @@</span><br><span> void do_global_reset(void)</span><br><span> {</span><br><span> pmc_global_reset_enable(1);</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ do_full_reset();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void soc_reset_prepare(enum reset_type reset_type)</span><br><span style="color: hsl(120, 100%, 40%);">+void cf9_reset_prepare(void)</span><br><span> {</span><br><span> struct stopwatch sw;</span><br><span> </span><br><span>diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c</span><br><span>index 995564d..d2ec6c1 100644</span><br><span>--- a/src/soc/intel/apollolake/romstage.c</span><br><span>+++ b/src/soc/intel/apollolake/romstage.c</span><br><span>@@ -24,6 +24,7 @@</span><br><span> #include <bootmode.h></span><br><span> #include <cbfs.h></span><br><span> #include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span> #include <console/console.h></span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/x86/pae.h></span><br><span>@@ -38,7 +39,6 @@</span><br><span> #include <intelblocks/systemagent.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span> #include <mrc_cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <soc/cpu.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/meminit.h></span><br><span>@@ -285,7 +285,7 @@</span><br><span> </span><br><span> if (ps->gen_pmcon1 & WARM_RESET_STS) {</span><br><span> printk(BIOS_INFO, "Full retrain unsupported on warm reboot.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ full_reset();</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig</span><br><span>index 2799e5b..2ba7992 100644</span><br><span>--- a/src/soc/intel/braswell/Kconfig</span><br><span>+++ b/src/soc/intel/braswell/Kconfig</span><br><span>@@ -20,7 +20,6 @@</span><br><span> select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED</span><br><span> select HAVE_MONOTONIC_TIMER</span><br><span> select HAVE_SMI_HANDLER</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> select NO_FIXED_XIP_ROM_SIZE</span><br><span> select PARALLEL_MP</span><br><span> select PCIEXP_ASPM</span><br><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index 256cf1b..baf9b23 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -35,7 +35,6 @@</span><br><span> select CPU_INTEL_FIRMWARE_INTERFACE_TABLE</span><br><span> select GENERIC_GPIO_LIB</span><br><span> select HAVE_FSP_GOP</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> select INTEL_DESCRIPTOR_MODE_CAPABLE</span><br><span> select HAVE_MONOTONIC_TIMER</span><br><span> select HAVE_SMI_HANDLER</span><br><span>diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c</span><br><span>index eae94cf..a6f8092 100644</span><br><span>--- a/src/soc/intel/cannonlake/reset.c</span><br><span>+++ b/src/soc/intel/cannonlake/reset.c</span><br><span>@@ -13,11 +13,12 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span> #include <console/console.h></span><br><span> #include <intelblocks/cse.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span> #include <fsp/util.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/common/reset.h></span><br><span> #include <string.h></span><br><span> #include <timer.h></span><br><span> #include <soc/pci_devs.h></span><br><span>@@ -85,7 +86,7 @@</span><br><span> </span><br><span> /* global reset if CSE fail to reset */</span><br><span> pmc_global_reset_enable(1);</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ do_full_reset();</span><br><span> }</span><br><span> </span><br><span> void chipset_handle_reset(uint32_t status)</span><br><span>@@ -93,7 +94,7 @@</span><br><span> switch (status) {</span><br><span> case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */</span><br><span> printk(BIOS_DEBUG, "GLOBAL RESET!!\n");</span><br><span style="color: hsl(0, 100%, 40%);">- do_global_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ global_reset();</span><br><span> break;</span><br><span> default:</span><br><span> printk(BIOS_ERR, "unhandled reset type %x\n", status);</span><br><span>diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig</span><br><span>index ea6f10e..42043d7 100644</span><br><span>--- a/src/soc/intel/common/Kconfig</span><br><span>+++ b/src/soc/intel/common/Kconfig</span><br><span>@@ -25,6 +25,7 @@</span><br><span> config SOC_INTEL_COMMON_RESET</span><br><span> bool</span><br><span> default n</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CF9_RESET</span><br><span> </span><br><span> config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE</span><br><span> bool</span><br><span>diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c</span><br><span>index c2f0594..870e371 100644</span><br><span>--- a/src/soc/intel/common/block/acpi/acpi.c</span><br><span>+++ b/src/soc/intel/common/block/acpi/acpi.c</span><br><span>@@ -18,7 +18,7 @@</span><br><span> #include <arch/smp/mpspec.h></span><br><span> #include <bootstate.h></span><br><span> #include <cbmem.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span> #include <cpu/intel/turbo.h></span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <cpu/x86/smm.h></span><br><span>diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c</span><br><span>index bdd7d91..8f17bca 100644</span><br><span>--- a/src/soc/intel/common/reset.c</span><br><span>+++ b/src/soc/intel/common/reset.c</span><br><span>@@ -1,9 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017 Google, Inc.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -15,21 +13,22 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/hlt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/reset.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <halt.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/common/reset.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_HAVE_HARD_RESET)</span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+__noreturn void global_reset(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* S0->S5->S0 trip. */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "%s() called!\n", __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ cf9_reset_prepare();</span><br><span style="color: hsl(120, 100%, 40%);">+ dcache_clean_all();</span><br><span style="color: hsl(120, 100%, 40%);">+ do_global_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ halt();</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_soft_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* PMC_PLTRST# asserted. */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(RST_CPU | SYS_RST, RST_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ full_reset();</span><br><span> }</span><br><span>diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig</span><br><span>index e22b8ee..736d567 100644</span><br><span>--- a/src/soc/intel/denverton_ns/Kconfig</span><br><span>+++ b/src/soc/intel/denverton_ns/Kconfig</span><br><span>@@ -33,7 +33,6 @@</span><br><span> select SOC_INTEL_COMMON</span><br><span> select SOC_INTEL_COMMON_RESET</span><br><span> select PLATFORM_USES_FSP2_0</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> select POSTCAR_STAGE</span><br><span> select C_ENVIRONMENT_BOOTBLOCK</span><br><span> select IOAPIC</span><br><span>diff --git a/src/soc/intel/denverton_ns/reset.c b/src/soc/intel/denverton_ns/reset.c</span><br><span>index 97955a5..577f1c4 100644</span><br><span>--- a/src/soc/intel/denverton_ns/reset.c</span><br><span>+++ b/src/soc/intel/denverton_ns/reset.c</span><br><span>@@ -15,13 +15,12 @@</span><br><span> </span><br><span> #include <console/console.h></span><br><span> #include <fsp/util.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> </span><br><span> void chipset_handle_reset(uint32_t status)</span><br><span> {</span><br><span> switch (status) {</span><br><span> case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */</span><br><span style="color: hsl(0, 100%, 40%);">- global_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Global Reset not implemented!\n");</span><br><span> break;</span><br><span> default:</span><br><span> printk(BIOS_ERR, "unhandled reset type %x\n", status);</span><br><span>diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c</span><br><span>index cf4ae7c..617b64a 100644</span><br><span>--- a/src/soc/intel/denverton_ns/romstage.c</span><br><span>+++ b/src/soc/intel/denverton_ns/romstage.c</span><br><span>@@ -15,9 +15,9 @@</span><br><span> */</span><br><span> </span><br><span> #include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span> #include <console/console.h></span><br><span> #include <cpu/x86/mtrr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <soc/fiamux.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/pci_devs.h></span><br><span>@@ -93,7 +93,7 @@</span><br><span> pci_write_config32(dev, PMC_ETR3,</span><br><span> pci_read_config32(dev, PMC_ETR3)</span><br><span> | PMC_ETR3_CF9GR);</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ full_reset();</span><br><span> }</span><br><span> }</span><br><span> }</span><br><span>diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig</span><br><span>index 30bb6a2..232dc4f 100644</span><br><span>--- a/src/soc/intel/quark/Kconfig</span><br><span>+++ b/src/soc/intel/quark/Kconfig</span><br><span>@@ -28,7 +28,6 @@</span><br><span> select ARCH_VERSTAGE_X86_32</span><br><span> select BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP</span><br><span> select C_ENVIRONMENT_BOOTBLOCK</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> select HAVE_MONOTONIC_TIMER</span><br><span> select NO_MMCONF_SUPPORT</span><br><span> select REG_SCRIPT</span><br><span>diff --git a/src/soc/intel/quark/reset.c b/src/soc/intel/quark/reset.c</span><br><span>index b5b86f3..fe13366 100644</span><br><span>--- a/src/soc/intel/quark/reset.c</span><br><span>+++ b/src/soc/intel/quark/reset.c</span><br><span>@@ -13,13 +13,13 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span> #include <console/console.h></span><br><span> #include <fsp/util.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> </span><br><span> void chipset_handle_reset(uint32_t status)</span><br><span> {</span><br><span> /* Do a hard reset if Quark FSP ever requests a reset */</span><br><span> printk(BIOS_ERR, "Unknown reset type %x\n", status);</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ full_reset();</span><br><span> }</span><br><span>diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig</span><br><span>index e368dec..89cf47d 100644</span><br><span>--- a/src/soc/intel/skylake/Kconfig</span><br><span>+++ b/src/soc/intel/skylake/Kconfig</span><br><span>@@ -31,7 +31,6 @@</span><br><span> select C_ENVIRONMENT_BOOTBLOCK</span><br><span> select GENERIC_GPIO_LIB</span><br><span> select HAVE_FSP_GOP</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> select INTEL_DESCRIPTOR_MODE_CAPABLE</span><br><span> select HAVE_MONOTONIC_TIMER</span><br><span> select HAVE_SMI_HANDLER</span><br><span>diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c</span><br><span>index d9e3ea5..f73563e 100644</span><br><span>--- a/src/soc/intel/skylake/reset.c</span><br><span>+++ b/src/soc/intel/skylake/reset.c</span><br><span>@@ -13,10 +13,11 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span> #include <console/console.h></span><br><span> #include <fsp/util.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/common/reset.h></span><br><span> #include <soc/me.h></span><br><span> #include <soc/pm.h></span><br><span> #include <timer.h></span><br><span>@@ -32,7 +33,7 @@</span><br><span> </span><br><span> /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port</span><br><span> * to global reset platform */</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ do_full_reset();</span><br><span> }</span><br><span> </span><br><span> void do_global_reset(void)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29169">change 29169</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29169"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53 </div>
<div style="display:none"> Gerrit-Change-Number: 29169 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>