<p>Aamir Bohra would like Subrata Banik to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/29164">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/intel/icelake_rvp: Initial mainboard commit<br><br>Clone entirely from mainboard/intel/cannonlake_rvp<br>commit id: af89f49b83260a04dece84b34e97560fb85d29ae<br><br>List of changes on top off initial cannonlake_rvp clone<br> 1. Rename "Cannonlake" with "Icelake".<br> 2. Replace "cannonlake_rvp" with "icelake_rvp".<br> 3. Rename "cnl" with "icl".<br> 4. Remove unwanted SPD file, will add correct SPD with mainboard<br> patches.<br> 5. Remove NHLT related implementation.<br> 6. Remove FSP configs, will add once FSP headers are available.<br><br>Change-Id: I875972d1fb2f630bf5eb29bd955c484e7f9aa415<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>---<br>A src/mainboard/intel/icelake_rvp/Kconfig<br>A src/mainboard/intel/icelake_rvp/Kconfig.name<br>A src/mainboard/intel/icelake_rvp/Makefile.inc<br>A src/mainboard/intel/icelake_rvp/acpi_tables.c<br>A src/mainboard/intel/icelake_rvp/board_info.txt<br>A src/mainboard/intel/icelake_rvp/bootblock.c<br>A src/mainboard/intel/icelake_rvp/chromeos.c<br>A src/mainboard/intel/icelake_rvp/chromeos.fmd<br>A src/mainboard/intel/icelake_rvp/dsdt.asl<br>A src/mainboard/intel/icelake_rvp/mainboard.c<br>A src/mainboard/intel/icelake_rvp/romstage_fsp_params.c<br>A src/mainboard/intel/icelake_rvp/smihandler.c<br>A src/mainboard/intel/icelake_rvp/spd/Makefile.inc<br>A src/mainboard/intel/icelake_rvp/spd/empty.spd.hex<br>A src/mainboard/intel/icelake_rvp/spd/spd.h<br>A src/mainboard/intel/icelake_rvp/spd/spd_util.c<br>A src/mainboard/intel/icelake_rvp/variants/baseboard/Makefile.inc<br>A src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c<br>A src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h<br>A src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h<br>A src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb<br>A src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h<br>A src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb<br>A src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h<br>24 files changed, 1,257 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/29164/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig</span><br><span>new file mode 100755</span><br><span>index 0000000..66957aa</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/Kconfig</span><br><span>@@ -0,0 +1,51 @@</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_INTEL_ICELAKE_RVPU || BOARD_INTEL_ICELAKE_RVPY</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_16384</span><br><span style="color: hsl(120, 100%, 40%);">+ select GENERIC_SPD_BIN</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+ select GENERIC_SPD_BIN</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_HID</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_GENERIC</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_ICELAKE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "intel/icelake_rvp"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VARIANT_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "icl_u" if BOARD_INTEL_ICELAKE_RVPU</span><br><span style="color: hsl(120, 100%, 40%);">+ default "icl_y" if BOARD_INTEL_ICELAKE_RVPY</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Icelake RVP"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_VENDOR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Intel"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_FAMILY</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Intel_icelake_rvp"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DIMM_SPD_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 512</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_LID_SWITCH</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_MOCK_SECDATA</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/Kconfig.name b/src/mainboard/intel/icelake_rvp/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..9ba17a6</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/Kconfig.name</span><br><span>@@ -0,0 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_INTEL_ICELAKE_RVPU</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Icelake U DDR4/LPDDR4 RVP"</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_INTEL_ICELAKE_RVPY</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Icelake Y LPDDR4 RVP"</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc</span><br><span>new file mode 100755</span><br><span>index 0000000..a47f497</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/Makefile.inc</span><br><span>@@ -0,0 +1,34 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += spd</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += romstage_fsp_params.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += mainboard.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += variants/baseboard</span><br><span style="color: hsl(120, 100%, 40%);">+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += variants/$(VARIANT_DIR)</span><br><span style="color: hsl(120, 100%, 40%);">+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/acpi_tables.c b/src/mainboard/intel/icelake_rvp/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..3b44754</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/acpi_tables.c</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/* Nothing here */</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/board_info.txt b/src/mainboard/intel/icelake_rvp/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..48ec997</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/board_info.txt</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor name: Intel</span><br><span style="color: hsl(120, 100%, 40%);">+Board name: Icelake rvp</span><br><span style="color: hsl(120, 100%, 40%);">+Category: eval</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/bootblock.c b/src/mainboard/intel/icelake_rvp/bootblock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..8655947</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/bootblock.c</span><br><span>@@ -0,0 +1,28 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_mainboard_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct pad_config *pads;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pads = variant_early_gpio_table(&num);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure_pads(pads, num);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c</span><br><span>new file mode 100644</span><br><span>index 0000000..f060091</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/chromeos.c</span><br><span>@@ -0,0 +1,64 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <rules.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if ENV_RAMSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+#include <boot/coreboot_tables.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void fill_lb_gpios(struct lb_gpios *gpios)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct lb_gpio chromeos_gpios[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, 0, "power"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* ENV_RAMSTAGE */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int get_lid_switch(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Lid always open */</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int get_recovery_mode_switch(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int get_write_protect_state(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* No write protect */</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_chromeos_acpi_generate(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct cros_gpio *gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpios = variant_cros_gpios(&num);</span><br><span style="color: hsl(120, 100%, 40%);">+ chromeos_acpi_gpio_generate(gpios, num);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/chromeos.fmd b/src/mainboard/intel/icelake_rvp/chromeos.fmd</span><br><span>new file mode 100755</span><br><span>index 0000000..65d22c3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/chromeos.fmd</span><br><span>@@ -0,0 +1,45 @@</span><br><span style="color: hsl(120, 100%, 40%);">+FLASH@0xff000000 0x1000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_ALL@0x0 0x380000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_DESC@0x0 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_EC@0x01000 0x80000</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_ME@0x81000 0x2ff000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_BIOS@0x380000 0xc80000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SECTION_A@0x0 0x368000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_A@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ FW_MAIN_A(CBFS)@0x10000 0x357fc0</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_FWID_A@0x367fc0 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SECTION_B@0x368000 0x368000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_B@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ FW_MAIN_B(CBFS)@0x10000 0x357fc0</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_FWID_B@0x367fc0 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_MISC@0x6d0000 0x30000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ UNIFIED_MRC_CACHE@0x0 0x20000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RECOVERY_MRC_CACHE@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_MRC_CACHE@0x10000 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_ELOG@0x20000 0x4000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SHARED@0x24000 0x4000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHARED_DATA@0x0 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_DEV@0x2000 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_VPD@0x28000 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_NVRAM@0x2a000 0x6000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ SMMSTORE@0x700000 0x40000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_LEGACY(CBFS)@0x740000 0x1c0000</span><br><span style="color: hsl(120, 100%, 40%);">+ WP_RO@0x900000 0x380000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_VPD@0x0 0x4000</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_UNUSED@0x4000 0xc000</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_SECTION@0x10000 0x370000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ FMAP@0x0 0x800</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_FRID@0x800 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_FRID_PAD@0x840 0x7c0</span><br><span style="color: hsl(120, 100%, 40%);">+ GBB@0x1000 0xef000</span><br><span style="color: hsl(120, 100%, 40%);">+ COREBOOT(CBFS)@0xf0000 0x280000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..47ca7e70</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/dsdt.asl</span><br><span>@@ -0,0 +1,47 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x05, // DSDT revision: ACPI v5.0</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", // OEM id</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", // OEM table id</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20110725 // OEM revision</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ // Some generic macros</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/icelake/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // global NVS and variables</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/icelake/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/icelake/acpi/northbridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/icelake/acpi/southbridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #if IS_ENABLED(CONFIG_CHROMEOS)</span><br><span style="color: hsl(120, 100%, 40%);">+ // Chrome OS specific</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <vendorcode/google/chromeos/acpi/chromeos.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Chipset specific sleep states</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/icelake/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..36d6a3e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/mainboard.c</span><br><span>@@ -0,0 +1,52 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_init(void *chip_info)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct pad_config *pads;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pads = variant_gpio_table(&num);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure_pads(pads, num);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static unsigned long mainboard_write_acpi_tables(struct device *device,</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned long current,</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_rsdp_t *rsdp)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t start_addr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ start_addr = current;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return start_addr;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->ops->write_acpi_tables = mainboard_write_acpi_tables;</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .init = mainboard_init,</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c</span><br><span>new file mode 100755</span><br><span>index 0000000..3ee98a1</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c</span><br><span>@@ -0,0 +1,27 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/byteorder.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbfs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "spd/spd.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <spd_bin.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_memory_init_params(FSPM_UPD *mupd)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/smihandler.c b/src/mainboard/intel/icelake_rvp/smihandler.c</span><br><span>new file mode 100644</span><br><span>index 0000000..7deabed</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/smihandler.c</span><br><span>@@ -0,0 +1,41 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/smihandler.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int mainboard_io_trap_handler(int smif)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (smif) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x99:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Sample\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_get_gnvs()->smif = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* On success, the IO Trap Handler returns 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * On failure, the IO Trap Handler returns a value != 0</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * For now, we force the return value to 0 and log all traps to</span><br><span style="color: hsl(120, 100%, 40%);">+ * see what's going on.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..854a491</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc</span><br><span>@@ -0,0 +1,27 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += spd_util.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_BIN = $(obj)/spd.bin</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES = empty # 0b000</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += empty # 0b001</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += empty # 0b001</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += empty # 0b011</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += empty # 0b100</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += empty # 0b101</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += empty # 0b110</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += empty # 0b111</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/spd/empty.spd.hex b/src/mainboard/intel/icelake_rvp/spd/empty.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..67b46cd</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/spd/empty.spd.hex</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/spd/spd.h b/src/mainboard/intel/icelake_rvp/spd/spd.h</span><br><span>new file mode 100644</span><br><span>index 0000000..9b55563</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/spd/spd.h</span><br><span>@@ -0,0 +1,27 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MAINBOARD_SPD_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_SPD_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCOMP_TARGET_PARAMS 0x5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_dq_map_ch0(void *dq_map_ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_dq_map_ch1(void *dq_map_ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/spd/spd_util.c b/src/mainboard/intel/icelake_rvp/spd/spd_util.c</span><br><span>new file mode 100644</span><br><span>index 0000000..f0a357f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/spd/spd_util.c</span><br><span>@@ -0,0 +1,81 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/byteorder.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbfs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "spd.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_dq_map_ch0(void *dq_map_ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQ byte map Ch0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dq_map[12] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 ,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_dq_map_ch1(void *dq_map_ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dq_map[12] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQS CPU<>DRAM map Ch0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_BOARD_INTEL_ICELAKE_RVPU))</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQS CPU<>DRAM map Ch1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_BOARD_INTEL_ICELAKE_RVPU))</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rcomp resistor */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u16 RcompResistor[3] = { 100, 100, 100 };</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rcomp target */</span><br><span style="color: hsl(120, 100%, 40%);">+ static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 80, 40, 40, 40, 30 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/Makefile.inc b/src/mainboard/intel/icelake_rvp/variants/baseboard/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..9fb63f5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/Makefile.inc</span><br><span>@@ -0,0 +1,3 @@</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..b0d6049</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c</span><br><span>@@ -0,0 +1,321 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Pad configuration in ramstage*/</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPPC */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A0 : RCINB_TIME_SYNC_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A1 : ESPI_IO_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A2 : ESPI_IO_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A3 : ESPI_IO_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A4 : ESPI_IO_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A5 : ESPI_CSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A6 : SERIRQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A7 : PRIQAB_GSP10_CS1B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_HIGH(GPP_A7, UP_20K, DEEP, EDGE_SINGLE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A8 : CLKRUNB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_A8, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A9 : CLKOUT_LPC_0_ESPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A10 : CLKOUT_LPC_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A11 : PMEB_GSP11_CS1B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_A11, UP_20K, DEEP, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A12 : BM_BUSYB_ISH__GP_6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A13 : SUSWARNB_SUSPWRDNACK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_A13, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A14 : SUS_STATB_ESPI_RESETB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A15 : SUSACKB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_A15, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A16 : SD_1P8_SEL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_A16, 0, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A18 : ISH_GP_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A19 : ISH_GP_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A20 : aduio codec irq */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A21 : ISH_GP_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A22 : ISH_GP_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A22, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A23 : ISH_GP_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B0 : CORE_VID_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B1 : CORE_VID_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B2 : VRALERTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP, LEVEL, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B3 : CPU_GP_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, LEVEL, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B4 : CPU_GP_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B4, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B5 : SRCCLKREQB_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B6 : SRCCLKREQB_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B7 : SRCCLKREQB_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B8 : SRCCLKREQB_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B9 : SRCCLKREQB_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B10 : SRCCLKREQB_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B11 : EXT_PWR_GATEB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B12 : SLP_S0B */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B13 : PLTRSTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B14 : SPKR */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B14, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B15 : GSPI0_CS0B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B15, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B16 : GSPI0_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B17 : GSPI0_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B17, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B18 : GSPI0_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B18, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B19 : GSPI1_CS0B */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B20 : GSPI1_CLK_NFC_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B21 : GSPI1_MISO_NFC_CLKREQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B22 : GSP1_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B23 : SML1ALERTB_PCHHOTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B23, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C0 : SMBCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C1 : SMBDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C2 : SMBALERTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C2, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C3 : SML0CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C4 : SML0DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C5 : SML0ALERTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C6 : SML1CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C7 : SML1DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C8 : UART0_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_C8, UP_20K, DEEP, LEVEL, INVERT),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C9 : UART0_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C10 : UART0_RTSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C10, 0, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C11 : UART0_CTSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_C11, UP_20K, DEEP, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C12 : UART1_RXD_ISH_UART1_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C12, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C13 : UART1_RXD_ISH_UART1_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C14 : UART1_RXD_ISH_UART1_RTSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C15 : UART1_RXD_ISH_UART1_CTSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C15, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C16 : I2C0_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C17 : I2C0_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C18 : I2C1_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C19 : I2C1_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C20 : UART2_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C21 : UART2_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C22 : UART2_RTSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C23 : UART2_CTSB */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D0 : SPI1_CSB_BK_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D1 : SPI1_CLK_BK_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D2 : SPI1_MISO_IO_1_BK_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D3 : SPI1_MOSI_IO_0_BK_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D4 : IMGCLKOUT_0_BK_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D5 : ISH_I2C0_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D6 : ISH_I2C0_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D7 : ISH_I2C1_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D8 : ISH_I2C1_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D9 : ISH_SPI_CSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_D9, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D10 : ISH_SPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST, EDGE_SINGLE, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D11 : ISH_SPI_MISO_GP_BSSB_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D12 : ISH_SPI_MOSI_GP_BSSB_DI */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D13 : ISH_UART0_RXD_SML0BDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_D13, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D14 : ISH_UART0_TXD_SML0BCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_D14, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D16 : ISH_UART0_CTSB_SML0BALERTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D17 : DMIC_CLK_1_SNDW3_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D18 : DMIC_DATA_1_SNDW3_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D19 : DMIC_CLK_0_SNDW4_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D20 : DMIC_DATA_0_SNDW4_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D21 : SPI1_IO_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D22 : SPI1_IO_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D23 : SPP_MCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E0 : SATAXPCIE_0_SATAGP_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_BOARD_INTEL_ICELAKE_RVPY)</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E1 : SATAXPCIE_1_SATAGP_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E2 : SATAXPCIE_2_SATAGP_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E3 : CPU_GP_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E4 : SATA_DEVSLP_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E5 : SATA_DEVSLP_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E6 : SATA_DEVSLP_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E7 : CPU_GP_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E8 : SATA_LEDB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E9 : USB2_OCB_0_GP_BSSB_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E10 : USB2_OCB_1_GP_BSSB_DI */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E11 : USB2_OCB_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E12 : USB2_OCB_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E13 : DDSP_HPD_0_DISP_MISC_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E14 : DDSP_HPD_0_DISP_MISC_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E15 : DDSP_HPD_0_DISP_MISC_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E16 : EMMC_EN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_E16, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E17 : EDP_HPD_DISP_MISC_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E18 : DDPB_CTRLCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E19 : DDPB_CTRLDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E20 : DDPC_CTRLCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E21 : DDPC_CTRLDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E22 : DDPD_CTRLCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E23 : DDPD_CTRLDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F0 : CNV_GNSS_PA_BLANKING */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPP_F0, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F1 : CNV_GNSS_FAT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_TERM_GPO(GPP_F1, 1, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F2 : CNV_GNSS_SYSCK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F3 : GPP_F_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F4 : CNV_BRI_DT_UART0_RTSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F5 : CNV_BRI_RSP_UART0_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F6 : CNV_RGI_DT_UART0_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F7 : CNV_RGI_DT_RSP_UART9_CTSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F8 : CNV_MFUART2_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F8, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F9 : CNV_MFUART2_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F9, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F10 : GPP_F_10 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_F10, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F11 : EMMC_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F12 : EMMC_DATA0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F13 : EMMC_DATA1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F14 : EMMC_DATA2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F15 : EMMC_DATA3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F16 : EMMC_DATA4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F17 : EMMC_DATA5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F18 : EMMC_DATA6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F19 : EMMC_DATA9 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F20 : EMMC_RCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F21 : EMMC_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F22 : EMMC_RESETB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F23 : BIOS_REC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPP_F23, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G0 : SD3_D2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G1 : SD3_D0_SD4_RCLK_P */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G2 : SD3_D1_SD4_RCLK_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G3 : SD3_D2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G4 : SD3_D3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G5 : SD3_CDB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G5, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G6 : SD3_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G7 : SD3_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H0 : SSP2_SCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H1 : SSP2_SFRM */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H2 : SSP2_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H3 : SSP2_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H4 : I2C2_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H5 : I2C2_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H6 : I2C3_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_H6, UP_2K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H7 : I2C3_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_H7, UP_2K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H8 : I2C4_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H9 : I2C4_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H10 : I2C5_SDA_ISH_I2C2_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H10, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H11 : I2C5_SCL_ISH_I2C2_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H11, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H12 : M2_SKT2_CFG_0_DFLEXIO_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H12, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H13 : M2_SKT2_CFG_1_DFLEXIO_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H13, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H14 : M2_SKT2_CFG_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H14, 0, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H15 : M2_SKT2_CFG_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H15, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H16 : CAM5_PWR_EN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H16, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H17 : CAM5_FLASH_STROBE */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H17, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H18 : BOOTMPC */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H19 : TIMESYNC_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H19, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H20 : IMGCLKOUT_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H21 : GPPC_H_21 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H22 : GPPC_H_22 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H22, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H23 : GPPC_H_23 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_0 : BATLOWB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_1 : ACPRESENT */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_2 : LAN_WAKEB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_3 : PWRBTNB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_4 : SLP_S3B */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_5 : SLP_S4B */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_6 : SLP_AB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_7 : GPD_7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD-8 : SUSCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD-9 : SLP_WLANB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD-10 : SLP_5B */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_11 : LANPHYPC */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Early pad configuration in bootblock */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *__weak variant_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *__weak</span><br><span style="color: hsl(120, 100%, 40%);">+ variant_early_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(early_gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return early_gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct cros_gpio cros_gpios[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cros_gpio * __weak variant_cros_gpios(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(cros_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ return cros_gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..36318d5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __BASEBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __BASEBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __BASEBOARD_GPIO_H__ */</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h</span><br><span>new file mode 100644</span><br><span>index 0000000..12d16bc</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __BASEBOARD_VARIANTS_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __BASEBOARD_VARIANTS_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* The next set of functions return the gpio table and fill in the number of</span><br><span style="color: hsl(120, 100%, 40%);">+ * entries for each table. */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_gpio_table(size_t *num);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_early_gpio_table(size_t *num);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cros_gpio *variant_cros_gpios(size_t *num);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /*__BASEBOARD_VARIANTS_H__ */</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..426436e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb</span><br><span>@@ -0,0 +1,144 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/icelake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SmbusEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaDspEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaAudioLinkHda" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[9]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[12]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[13]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[14]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[15]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[1]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[3]" = "13"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[4]" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[5]" = "14"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[0]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[2]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[3]" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[4]" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[5]" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable "Intel Speed Shift Technology"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "speed_shift_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPIO for SD card detect</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdcard_cd_gpio" = "GPP_G5"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable S0ix</span><br><span style="color: hsl(120, 100%, 40%);">+ register "s0ix_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Intel Common SoC Config</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Field | Value |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| I2C3 | Audio |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "common_soc_config" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .i2c[3] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_STANDARD,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rise_time_ns = 104,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fall_time_ns = 52,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 on end # SA Thermal device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.5 off end # UFS SCS</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.6 off end # GSPI #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # USB xHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.3 on end # CNVi wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.5 on end # SDCard</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # I2C #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 on end # I2C #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 off end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 on end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.5 off end # Management Engine Interface 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 off end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on end # I2C #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 off end # I2C #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 on end # UART #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # PCI Express Port 9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.4 off end # PCI Express Port 13</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.5 off end # PCI Express Port 14</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.6 off end # PCI Express Port 15</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.7 off end # PCI Express Port 16</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # UART #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 off end # GSPI #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..c34a9b3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __MAINBOARD_GPIO_H__ */</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..55b5aa3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb</span><br><span>@@ -0,0 +1,128 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/icelake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SmbusEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_EMPTY"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[7]" = "USB2_PORT_EMPTY"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_EMPTY"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaDspEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaAudioLinkHda" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaAudioLinkSsp0" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaAudioLinkSsp1" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[9]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[12]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[13]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[1]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[3]" = "14"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[0]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[2]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[3]" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[4]" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[5]" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable "Intel Speed Shift Technology"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "speed_shift_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPIO for SD card detect</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdcard_cd_gpio" = "GPP_G5"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable S0ix</span><br><span style="color: hsl(120, 100%, 40%);">+ register "s0ix_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 on end # SA Thermal device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.5 off end # UFS SCS</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.6 off end # GSPI #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # USB xHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.3 on end # CNVi wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.5 on end # SDCard</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # I2C 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 on end # I2C #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 off end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 on end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.5 off end # Management Engine Interface 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 off end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on end # I2C #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 off end # I2C #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 on end # UART #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # PCI Express Port 9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.4 off end # PCI Express Port 13</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.5 off end # PCI Express Port 14</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.6 off end # PCI Express Port 15</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.7 off end # PCI Express Port 16</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # UART #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 off end # GSPI #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..c34a9b3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __MAINBOARD_GPIO_H__ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29164">change 29164</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29164"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I875972d1fb2f630bf5eb29bd955c484e7f9aa415 </div>
<div style="display:none"> Gerrit-Change-Number: 29164 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>