<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29175">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Replace double defined MISC MMIO reg. 0x40<br><br>Register 0x40 of miscellaneous MMIO is double defined, with different names,<br>which makes it confusing. Eliminate MISC_MISC_CLK_CNTL_1, and move its only<br>bit definition to MISC_CLK_CNTL1 (which is correctly placed among MMIO<br>registers.<br><br>BUG=b:117818431<br>TEST=Build grunt.<br><br>Change-Id: I5ca5045498b8a81943282e0d6ecfbaecbd600d19<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 2 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/29175/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 3d0df68..681f149 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -132,6 +132,7 @@</span><br><span> #define   CG1PLL_LF_MODE_MASK           (0x1ff << CG1PLL_LF_MODE_SHIFT)</span><br><span> #define MISC_CLK_CNTL1                 0x40</span><br><span> #define   CG1PLL_FBDIV_TEST             BIT(26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define   OSCOUT1_CLK_OUTPUT_ENB       BIT(2)  /* 0 = Enabled, 1 = Disabled */</span><br><span> </span><br><span> /* XHCI_PM Registers:  0xfed81c00 */</span><br><span> #define XHCI_PM_INDIRECT_INDEX           0x48</span><br><span>@@ -370,9 +371,6 @@</span><br><span> #define SPI100_HOST_PREF_CONFIG           0x2c</span><br><span> #define   SPI_RD4DW_EN_HOST             BIT(15)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_MISC_CLK_CNTL_1         0x40</span><br><span style="color: hsl(0, 100%, 40%);">-#define   OSCOUT1_CLK_OUTPUT_ENB    BIT(2)  /* 0 = Enabled, 1 = Disabled */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Platform Security Processor D8F0 */</span><br><span> #define PSP_MAILBOX_BAR                    PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */</span><br><span> #define PSP_BAR_ENABLES                      0x48</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 33330a8..37ebdc1 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -395,7 +395,7 @@</span><br><span> {</span><br><span>     u32 ctrl;</span><br><span>    u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE</span><br><span style="color: hsl(0, 100%, 40%);">-                            + MISC_MISC_CLK_CNTL_1);</span><br><span style="color: hsl(120, 100%, 40%);">+                              + MISC_CLK_CNTL1);</span><br><span> </span><br><span>       /*</span><br><span>    * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29175">change 29175</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29175"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5ca5045498b8a81943282e0d6ecfbaecbd600d19 </div>
<div style="display:none"> Gerrit-Change-Number: 29175 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>