<p>Felix Held <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/29100">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/i82801jx: Use macros for LPC_EN<br><br>Change-Id: I4a9a9366c85206fa460519a26f48b3aada5bc7c3<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>Reviewed-on: https://review.coreboot.org/29100<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Felix Held <felix-coreboot@felixheld.de><br>---<br>M src/mainboard/intel/dg43gt/romstage.c<br>M src/southbridge/intel/i82801jx/i82801jx.h<br>2 files changed, 14 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c</span><br><span>index 64b462f..36aa149 100644</span><br><span>--- a/src/mainboard/intel/dg43gt/romstage.c</span><br><span>+++ b/src/mainboard/intel/dg43gt/romstage.c</span><br><span>@@ -60,7 +60,10 @@</span><br><span> {</span><br><span> /* Configure serial IRQs.*/</span><br><span> pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ | COMB_LPC_EN | COMA_LPC_EN);</span><br><span> pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0xfc0601);</span><br><span> pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xfc0291);</span><br><span> pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0);</span><br><span>diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h</span><br><span>index 2e2d719..3c09746 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/i82801jx.h</span><br><span>+++ b/src/southbridge/intel/i82801jx/i82801jx.h</span><br><span>@@ -99,6 +99,16 @@</span><br><span> #define D31F0_PIRQH_ROUT 0x6b</span><br><span> #define D31F0_LPC_IODEC 0x80</span><br><span> #define D31F0_LPC_EN 0x82</span><br><span style="color: hsl(120, 100%, 40%);">+#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */</span><br><span style="color: hsl(120, 100%, 40%);">+#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */</span><br><span style="color: hsl(120, 100%, 40%);">+#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */</span><br><span> #define D31F0_GEN1_DEC 0x84</span><br><span> #define D31F0_GEN2_DEC 0x88</span><br><span> #define D31F0_GEN3_DEC 0x8c</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29100">change 29100</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29100"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I4a9a9366c85206fa460519a26f48b3aada5bc7c3 </div>
<div style="display:none"> Gerrit-Change-Number: 29100 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Felix Held <felix-coreboot@felixheld.de> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>