<p>Felix Held <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/29102">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/asus/p5q_pro: Add mainboard<br><br>This mainboard is quite similar to the p5qc. The main differences being a second<br>PEG slot, the IDE slot and being DDR2 only.<br><br>The following was tested:<br>- both PEG slots populated (coreboot sets legacy VGA decoding on the GPU in the<br>black slot)<br>- USB<br>- Ethernet NIC<br>- PS2 Keyboard<br>- COM1<br>- S3 resume<br><br>Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>Reviewed-on: https://review.coreboot.org/29102<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Felix Held <felix-coreboot@felixheld.de><br>---<br>M src/mainboard/asus/p5qc/Kconfig<br>M src/mainboard/asus/p5qc/Kconfig.name<br>A src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb<br>R src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb<br>4 files changed, 143 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig</span><br><span>index cf71b64..2bcee16 100644</span><br><span>--- a/src/mainboard/asus/p5qc/Kconfig</span><br><span>+++ b/src/mainboard/asus/p5qc/Kconfig</span><br><span>@@ -14,7 +14,7 @@</span><br><span> # GNU General Public License for more details.</span><br><span> #</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_ASUS_P5QC</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO</span><br><span> </span><br><span> config BOARD_SPECIFIC_OPTIONS</span><br><span> def_bool y</span><br><span>@@ -34,9 +34,20 @@</span><br><span> string</span><br><span> default "asus/p5qc"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config VARIANT_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "p5qc" if BOARD_ASUS_P5QC</span><br><span style="color: hsl(120, 100%, 40%);">+ default "p5q_pro" if BOARD_ASUS_P5Q_PRO</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span style="color: hsl(0, 100%, 40%);">- default "P5QC"</span><br><span style="color: hsl(120, 100%, 40%);">+ default "P5QC" if BOARD_ASUS_P5QC</span><br><span style="color: hsl(120, 100%, 40%);">+ default "P5Q-PRO" if BOARD_ASUS_P5Q_PRO</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/p5qc/devicetree.cb" if BOARD_ASUS_P5QC</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/p5q_pro/devicetree.cb" if BOARD_ASUS_P5Q_PRO</span><br><span> </span><br><span> config MAX_CPUS</span><br><span> int</span><br><span>diff --git a/src/mainboard/asus/p5qc/Kconfig.name b/src/mainboard/asus/p5qc/Kconfig.name</span><br><span>index d764867..a4c6e48 100644</span><br><span>--- a/src/mainboard/asus/p5qc/Kconfig.name</span><br><span>+++ b/src/mainboard/asus/p5qc/Kconfig.name</span><br><span>@@ -1,2 +1,5 @@</span><br><span> config BOARD_ASUS_P5QC</span><br><span> bool "P5QC"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_ASUS_P5Q_PRO</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "P5Q PRO"</span><br><span>diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..f7088fc</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb</span><br><span>@@ -0,0 +1,127 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+# (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/x4x # Northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on # APIC cluster</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_LGA775</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_1067x # CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xACAC off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on # PCI domain</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1.0 on end # PEG</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.0 off end # Integrated graphics controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.1 off end # Integrated graphics controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.0 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.1 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.2 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.3 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 6.0 on end # PEG 2</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/i82801jx # Southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_en" = "0x40"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set AHCI mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x3f"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_clock_request" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_traffic_monitor" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable PCIe ports 0,2,3 as slots.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_slot_implemented" = "0x31"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 off end # GBE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.1 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.2 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.7 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on end # Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCIe 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off end # PCIe 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCIe 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCIe 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on end # PCIe 5 MARVEL IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 on end # PCIe 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.7 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/winbond/w83667hg-a # Super I/O</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 on # FDC</span><br><span style="color: hsl(120, 100%, 40%);">+ # Global registers</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x2a = 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x2c = 0x22</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x2d = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f0</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0x06</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 off end # LPT1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 on # COM1</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 off end # COM2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # PS/2 keyboard & mouse</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x72 = 12</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.106 off end # SPI1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.107 off end # GIPO6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.207 off end # GIPO7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.307 on # GIPO8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xe4 = 0xfb</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xe5 = 0x82</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.407 off end # GIPO9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.8 off end # WDT</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.108 off end # GPIO 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.9 off end # GPIO2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.109 on end # GPIO3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.209 on # GPIO4</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0xff</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xfe = 0x07</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.309 on end # GPIO5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.a on # ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xe4 = 0x10 # 3VSBSW# enable</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xe5 = 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf2 = 0xfc</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.b on # HW Monitor</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x290</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ # IRQ purposefully not assigned to prevent lockups</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.c on end # PECI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.d on end # VID_BUSSEL</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.f on end # GPIO_PP_OD</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 off end # PATA/IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # SMbus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/asus/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/asus/p5qc/devicetree.cb</span><br><span>rename to src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29102">change 29102</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1 </div>
<div style="display:none"> Gerrit-Change-Number: 29102 </div>
<div style="display:none"> Gerrit-PatchSet: 5 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Felix Held <felix-coreboot@felixheld.de> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>