<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29075">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Define PM USB Enable register<br><br>Make #define definitions for PMxEF and replace the hardcoded values.<br><br>Note that this doesn't change the current functionality of the source.<br>The existing code has been propogated from the sb//hudson port, which<br>seems to attempt to enable 100% of all OHCI and EHCI controllers that<br>may be present in the system.<br><br>Change-Id: I6018b0062730de19e3283a010144dfedc2b11423<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/enable_usbdebug.c<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>2 files changed, 4 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/29075/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c</span><br><span>index 0a0c3ec..27ac61f 100644</span><br><span>--- a/src/soc/amd/stoneyridge/enable_usbdebug.c</span><br><span>+++ b/src/soc/amd/stoneyridge/enable_usbdebug.c</span><br><span>@@ -26,8 +26,8 @@</span><br><span> pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)</span><br><span> {</span><br><span>   /* Enable all of the USB controllers */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0xef, PM_INDEX);</span><br><span style="color: hsl(0, 100%, 40%);">-   outb(0x7f, PM_DATA);</span><br><span style="color: hsl(120, 100%, 40%);">+  outb(PM_USB_ENABLE, PM_INDEX);</span><br><span style="color: hsl(120, 100%, 40%);">+        outb(PM_USB_ALL_CONTROLLERS, PM_DATA);</span><br><span> </span><br><span>   return SOC_EHCI1_DEV;</span><br><span> }</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index ce0af95..b9dc62a 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -101,6 +101,8 @@</span><br><span> #define   PM_LPC_AB_NO_BYPASS_EN   BIT(2)</span><br><span> #define   PM_LPC_A20_EN                       BIT(1)</span><br><span> #define   PM_LPC_ENABLE                       BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM_USB_ENABLE                   0xef</span><br><span style="color: hsl(120, 100%, 40%);">+#define   PM_USB_ALL_CONTROLLERS  0x7f</span><br><span> </span><br><span> /* FCH MISC Registers 0xfed80e00 */</span><br><span> #define GPP_CLK_CNTRL                        0x00</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29075">change 29075</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29075"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6018b0062730de19e3283a010144dfedc2b11423 </div>
<div style="display:none"> Gerrit-Change-Number: 29075 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>