<p>PraveenX Hodagatta Pranesh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29066">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/intel/coffeelake_rvp: Add support for new coffee lake RVP8<br><br>- Add new mainboard variant coffee lake RVP8, which is CRB for<br> coffee lake-s processor, support U-DIMM DDR4 memory module.<br><br>- Modify cfl_h devicetree to enable IO devices, configure PCIE root<br> port clock source, usb over current pin as per board schematics.<br><br>- Select cannonlake PCH-H chipset config for both cfl_h & cfl_s.<br><br>- Add GPIO table as per board schematics.<br><br>BUG= None<br>TEST= Build and flash, confirm boot into yocoto & windows OS on both<br> cfl RVP11 & RVP8 platform. verified PCI, USB, ethernet, SATA,<br> display, power functionalities.<br><br>Change-Id: Iabd32eb43ee8e6b1a3993ba4e083a80c62485b14<br>Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com><br>---<br>M src/mainboard/intel/coffeelake_rvp/Kconfig<br>M src/mainboard/intel/coffeelake_rvp/Kconfig.name<br>M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c<br>M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb<br>A src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb<br>5 files changed, 531 insertions(+), 42 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29066/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig</span><br><span>index 311f6d1..83ab9c5 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/Kconfig</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig</span><br><span>@@ -1,4 +1,4 @@</span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8</span><br><span> </span><br><span> config BOARD_SPECIFIC_OPTIONS</span><br><span> def_bool y</span><br><span>@@ -13,6 +13,7 @@</span><br><span> select DRIVERS_I2C_GENERIC</span><br><span> select SOC_INTEL_COFFEELAKE</span><br><span> select SOC_INTEL_CANNONLAKE_MEMCFG_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8</span><br><span> </span><br><span> config MAINBOARD_DIR</span><br><span> string</span><br><span>@@ -23,6 +24,7 @@</span><br><span> default "cfl_u" if BOARD_INTEL_COFFEELAKE_RVPU</span><br><span> default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11</span><br><span> default "whl_u" if BOARD_INTEL_WHISKEYLAKE_RVP</span><br><span style="color: hsl(120, 100%, 40%);">+ default "cfl_s" if BOARD_INTEL_COFFEELAKE_RVP8</span><br><span> </span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span>@@ -38,6 +40,7 @@</span><br><span> </span><br><span> config MAX_CPUS</span><br><span> int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 12 if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8</span><br><span> default 8</span><br><span> </span><br><span> config DEVICETREE</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name</span><br><span>index f9f82a2..773c83a 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name</span><br><span>@@ -6,3 +6,5 @@</span><br><span> bool "-> Coffeelake H SO-DIMM DDR4 RVP11"</span><br><span> config BOARD_INTEL_WHISKEYLAKE_RVP</span><br><span> bool "-> Whiskeylake U DDR4 RVP"</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_INTEL_COFFEELAKE_RVP8</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "-> Coffeelake S U-DIMM DDR4 RVP8"</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c</span><br><span>index 821cba3..fc35050 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c</span><br><span>@@ -17,6 +17,7 @@</span><br><span> #include <baseboard/variants.h></span><br><span> #include <commonlib/helpers.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if !IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)</span><br><span> static const struct pad_config gpio_table[] = {</span><br><span> /* GPPC */</span><br><span> /* A0 : RCINB_TIME_SYNC_1 */</span><br><span>@@ -285,6 +286,310 @@</span><br><span> /* GPD_11 : LANPHYPC */</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPPC */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A0 : RCIN_ESPI_ALERT1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A1 : ESPI_IO_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A2 : ESPI_IO_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A3 : ESPI_IO_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A4 : ESPI_IO_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A5 : ESPI_CSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A6 : SERIRQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A7 : PRIQAB_ESPI_ALERT0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A8 : CLKRUNB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_A8, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A9 : CLKOUT_LPC_0_ESPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A10 : CLKOUT_LPC_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A11 : I2S_CODEC_INT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_LOW(GPP_A11, UP_20K, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A12 : BM_BUSYB_ISH__GP_6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A13 : SUSWARNB_SUSPWRDNACK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_A13, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A14 : SUS_STATB_ESPI_RESETB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A15 : SUSACKB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_A15, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A16 : TCH_PAD_INT_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_A16, NONE, PLTRST, LEVEL, INVERT),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A18 : ISH_GP_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A19 : ISH_GP_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A20 : ISH_GP_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A21 : ISH_GP_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A22 : ISH_GP_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A23 : ISH_GP_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B0 : SPI_TPM_INIT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_B0, UP_20K, DEEP, EDGE_SINGLE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B1 : GSPI1_CS1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B2 : VRALERTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP, LEVEL, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B3 : BT_RF_KILL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B3, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B4 : WIFI_RF_KILL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B4, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B5 : SRCCLKREQB_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B6 : SRCCLKREQB_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B7 : SRCCLKREQB_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B8 : SRCCLKREQB_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B9 : SRCCLKREQB_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B10 : SRCCLKREQB_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B11 : I2S_MCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B12 : SLP_S0B */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B13 : PLTRSTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B14 : SPKR */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B14, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B15 : GSPI0_CS0B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B15, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B16 : GSPI0_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B17 : GSPI0_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B17, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B18 : I2C_TCH_PNL_PWREN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B18, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B19 : GSPI1_CS0B */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B20 : GSPI1_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B21 : GSPI1_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B22 : GSP1_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B23 : EC_SLP_S0_CS_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B23, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C0 : SMBCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C1 : SMBDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C2 : SMBALERTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C2, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C3 : SML0CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C4 : SML0DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C5 : WIFI_WAKE_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C6 : SML1CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C7 : SML1DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C8 : UART0_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_C8, UP_20K, DEEP, LEVEL, INVERT),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C9 : UART0_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C10 : UART0_RTSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C10, 0, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C11 : UART0_CTSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_TERM_GPO(GPP_C11, 1, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C12 : UART1_RXD_ISH_UART1_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C12, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C13 : UART1_RXD_ISH_UART1_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C14 : SSD1_RESET */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C14, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C15 : SSD2_RESET */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C15, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C16 : I2C0_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C17 : I2C0_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C18 : I2C1_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C19 : I2C1_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C20 : UART2_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C21 : UART2_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C22 : UART2_RTSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C23 : UART2_CTSB */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D0 : SPI1_CSB_BK_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D1 : SPI1_CLK_BK_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D2 : SPI1_MISO_IO_1_BK_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D3 : SPI1_MOSI_IO_0_BK_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D4 : IMGCLKOUT_0_BK_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D5 : ISH_I2C0_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D6 : ISH_I2C0_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D7 : SSP2_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_INT(GPP_D7, NONE, PLTRST, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D8 : SSP2_SCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_INT(GPP_D8, NONE, PLTRST, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D9 : ISH_SPI_CSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_D9, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D10 : ISH_SPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_D10, UP_20K, PLTRST, LEVEL, INVERT),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D11 : ISH_SPI_MISO_GP_BSSB_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D12 : ISH_SPI_MOSI_GP_BSSB_DI */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D13 : ISH_UART0_RXD_SML0BDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_D13, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D14 : ISH_UART0_TXD_SML0BCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_D14, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D16 : ISH_UART0_CTSB_SML0BALERTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D17 : DMIC_CLK_1_SNDW3_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D18 : DMIC_DATA_1_SNDW3_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D19 : DMIC_CLK_0_SNDW4_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D20 : DMIC_DATA_0_SNDW4_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D21 : SPI1_IO_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D22 : SPI1_IO_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D23 : ISH_I2C2_SCL_I2C3_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E0 : SATAXPCIE_0_SATAGP_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E1 : SATAXPCIE_1_SATAGP_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E2 : SATAXPCIE_2_SATAGP_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E3 : EC_SMI_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E4 : SATA_DEVSLP_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E5 : SATA_DEVSLP_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E6 : SATA_DEVSLP_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E7 : CPU_GP_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E8 : SATA_LEDB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E9 : USB2_OCB_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E10 : USB2_OCB_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E11 : USB2_OCB_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E12 : USB2_OCB_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F0 : SATAXPCIE_3_SATAGP_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F1 : SATAXPCIE_4_SATAGP_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F2 : SATAXPCIE_5_SATAGP_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F3 : SATAXPCIE_6_SATAGP_6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F4 : SLOT2_RST_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_F4, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F5 : SATA_DEVSLP_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F6 : SATA_DEVSLP_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F7 : ME_PG_LED */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F8 : SATA_DEVSLP_6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F9 : PEG_SLOT_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_F9, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F10 : BIOS_RECOVERY */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_INT(GPP_F10, NONE, PLTRST, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F11 : SATA_SLOAD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F12 : SATA_S-DATA_OUT1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F13 : SATA_S-DATA_OUT0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F14 : PS_ON */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F15 : USB2_OC_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F16 : USB2_OC_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F17 : USB2_OC_6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F18 : USB2_OC_7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F19 : EDP_VDDEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F20 : EDP_BKLTEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F21 : EDP_BKLTCTL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F22 : DDPF_C_TRLCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F23 : DDPF_C_TRLDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G0 : SD_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G1 : SD_DATA0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G2 : SD_DATA1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G3 : SD_DATA2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G4 : SD_DATA3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G5 : GPP_G_5_SD3_CDB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G5, UP_20K, DEEP, GPIO),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G6 : SD_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G7 : GPP_G_7_SD3_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, GPIO),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H0 : SRCCLKREQB_6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H1 : SRCCLKREQB_7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H2 : SRCCLKREQB_8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H3 : SRCCLKREQB_9 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H4 : SRCCLKREQB_10 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H5 : SRCCLKREQB_11 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H6 : SRCCLKREQB_12 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H7 : SRCCLKREQB_13 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H8 : SRCCLKREQB_14 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H9 : SRCCLKREQB_15 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H10 : Audio Power Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H10, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H11 : SML_2_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H12 : SML_2_ALERT */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H13 : SML_3_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H14 : SML_3_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H15 : SML_3_ALERT */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H16 : TBT_CIO_PWREN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H16, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H17 : TBT_FORCE_PWR */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H17, 0, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H18 : SML_4_ALERT */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H19 : ISH_I2C0_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H20 : ISH_I2C0_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H21 : ISH_I2C1_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H22 : ISH_I2C1_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H23 : TBT_CIO_PLUG_EVENT_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_H23, NONE, PLTRST, EDGE_SINGLE),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I0 : DDPB_HPD_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I1 : DDPC_HPD_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I2 : DPPD_HPD_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I3 : DPPE_HPD_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I4 : EDP_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I5 : DDPB_C_TRLCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I6 : DDPB_C_TRLDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I7 : DDPC_C_TRLCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I8 : DDPC_C_TRLDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I9 : DDPD_C_TRLCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I10 : DDPD_C_TRLDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I11 : M2_SKT2_C_FG0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I12 : M2_SKT2_CFG1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I13 : M2_SKT2_C_FG2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I14 : M2_SKT2_C_FG3 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* J0 : I2C_TCH_PNL_INT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_J0, UP_20K, PLTRST, EDGE_SINGLE, INVERT),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* J1 : CPU_C10_GATE */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* J2 : FPS_INT_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_J2, NONE, PLTRST, EDGE_SINGLE, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* J3 : FPS_RST_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_J3, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* J4 : CNV_BRI_DT_UART0_RTS */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* J5 : CNV_BRI_RSP_UART0_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* J6 : CNV_RGI_DT_UART0_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* J7 : CNV_RGI_RSP_UART0_CTS */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* J8 : CNV_M_FUART2_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* J9 : CNV_M_FUART2_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* J10 : I2C_TCH_PNL_RST_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_J10, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* J11 : SPEAKER_PD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_J11, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K0 : GPP_K0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K1 : SATA_ODD_PWRGT_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_K1, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K2 : SATA_ODD_DA_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_HIGH(GPP_K2, NONE, PLTRST, EDGE_SINGLE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K3 : GPP_K3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K4 : GPP_K4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K5 : GPP_K5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K6 : GPP_K6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K7 : GPP_K7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K8 : GPP_K8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K9 : GPP_K9 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K10 : GPP_K10 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K11 : RUNTIME_SCI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_K11, UP_20K, PLTRST, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K12 : GSXDOUT */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K13 : GSXSLOAD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K14 : GSXDIN */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K15 : GSXSRESET */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K16 : GSXCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K17 : ADR_COMPLETE */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K18 : SLOT2_WAKE_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_K18, NONE, PLTRST, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K19 : SMI */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K20 : GPP_K20 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K21 : GPP_K21 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K22 : IMGCLKOUT_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* K23 : IMGCLKOUT_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_0 : BATLOWB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_1 : ACPRESENT */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_2 : LAN_WAKEB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_3 : PWRBTNB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_4 : SLP_S3B */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_5 : SLP_S4B */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_6 : SLP_AB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_7 : GPD_7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD-8 : SUSCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD-9 : SLP_WLANB */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD-10 : SLP_5B */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD_11 : LANPHYPC */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Early pad configuration in bootblock */</span><br><span> static const struct pad_config early_gpio_table[] = {</span><br><span> </span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>index 9115fd9..4a2fad9 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>@@ -6,31 +6,48 @@</span><br><span> </span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "RMT" = "1"</span><br><span> register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_MID(OC6)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"</span><br><span> register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"</span><br><span> register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[6]" = "USB2_PORT_EMPTY"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[7]" = "USB2_PORT_EMPTY"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[8]" = "USB2_PORT_EMPTY"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_MID(OC1)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[7]" = "USB2_PORT_MID(OC1)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_MID(OC2)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[9]" = "USB2_PORT_MID(OC7)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[10]" = "USB2_PORT_MID(OC7)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[11]" = "USB2_PORT_MID(OC3)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[12]" = "USB2_PORT_MID(OC3)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC7)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)"</span><br><span> register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span> register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC1)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC1)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC7)"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- register "PchHdaDspEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataSalpSupport" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaDspEnable" = "0"</span><br><span> register "PchHdaAudioLinkHda" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PchHdaAudioLinkSsp0" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PchHdaAudioLinkSsp1" = "1"</span><br><span> </span><br><span> register "PcieRpEnable[0]" = "1"</span><br><span> register "PcieRpEnable[1]" = "1"</span><br><span>@@ -46,13 +63,25 @@</span><br><span> register "PcieRpEnable[11]" = "1"</span><br><span> register "PcieRpEnable[12]" = "1"</span><br><span> register "PcieRpEnable[13]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[14]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[15]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[16]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[17]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[18]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[19]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[20]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[21]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[22]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[23]" = "1"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[0]" = "1"</span><br><span> register "PcieClkSrcUsage[1]" = "8"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[3]" = "14"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[3]" = "0x6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[4]" = "0x18"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[5]" = "14"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[8]" = "0x40"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[9]" = "PCIE_CLK_LAN"</span><br><span> </span><br><span> register "PcieClkSrcClkReq[0]" = "0"</span><br><span> register "PcieClkSrcClkReq[1]" = "1"</span><br><span>@@ -60,15 +89,14 @@</span><br><span> register "PcieClkSrcClkReq[3]" = "3"</span><br><span> register "PcieClkSrcClkReq[4]" = "4"</span><br><span> register "PcieClkSrcClkReq[5]" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[8]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[9]" = "9"</span><br><span> </span><br><span> # Enable "Intel Speed Shift Technology"</span><br><span> register "speed_shift_enable" = "1"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # GPIO for SD card detect</span><br><span style="color: hsl(0, 100%, 40%);">- register "sdcard_cd_gpio" = "GPP_G5"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # Enable S0ix</span><br><span style="color: hsl(0, 100%, 40%);">- register "s0ix_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # HECI</span><br><span style="color: hsl(120, 100%, 40%);">+ register "HeciEnabled" = "1"</span><br><span> </span><br><span> device domain 0 on</span><br><span> device pci 00.0 on end # Host Bridge</span><br><span>@@ -79,29 +107,19 @@</span><br><span> device pci 12.6 off end # GSPI #2</span><br><span> device pci 14.0 on end # USB xHCI</span><br><span> device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.3 on end # CNVi wifi</span><br><span> device pci 14.5 on end # SDCard</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/i2c/hid</span><br><span style="color: hsl(0, 100%, 40%);">- register "generic.hid" = ""ALPS0001""</span><br><span style="color: hsl(0, 100%, 40%);">- register "generic.desc" = ""Touchpad""</span><br><span style="color: hsl(0, 100%, 40%);">- register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "hid_desc_reg_offset" = "0x1"</span><br><span style="color: hsl(0, 100%, 40%);">- device i2c 2C on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end # I2C 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # I2C #0</span><br><span> device pci 15.1 on end # I2C #1</span><br><span> device pci 15.2 off end # I2C #2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.3 on end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 off end # I2C #3</span><br><span> device pci 16.0 on end # Management Engine Interface 1</span><br><span> device pci 16.1 off end # Management Engine Interface 2</span><br><span> device pci 16.2 off end # Management Engine IDE-R</span><br><span> device pci 16.3 off end # Management Engine KT Redirection</span><br><span> device pci 16.4 off end # Management Engine Interface 3</span><br><span> device pci 16.5 off end # Management Engine Interface 4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 17.0 off end # SATA</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.0 on end # I2C #4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.1 off end # I2C #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 off end # I2C #4</span><br><span> device pci 19.2 on end # UART #2</span><br><span> device pci 1a.0 on end # eMMC</span><br><span> device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1</span><br><span>@@ -128,9 +146,9 @@</span><br><span> end # LPC Interface</span><br><span> device pci 1f.1 on end # P2SB</span><br><span> device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.3 off end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # Intel HDA</span><br><span> device pci 1f.4 on end # SMBus</span><br><span> device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.6 off end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 on end # GbE</span><br><span> end</span><br><span> end</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..5a3d4ce</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb</span><br><span>@@ -0,0 +1,161 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/cannonlake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "RMT" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SmbusEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_MID(OC2)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[3]" = "USB2_PORT_MID(OC5)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_MID(OC5)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_MID(OC1)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[7]" = "USB2_PORT_MID(OC1)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_EMPTY"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[10]" = "USB2_PORT_MID(OC3)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[11]" = "USB2_PORT_MID(OC6)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[12]" = "USB2_PORT_MID(OC6)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[13]" = "USB2_PORT_EMPTY"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC5)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC1)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC1)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC3)"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataSalpSupport" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaDspEnable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaAudioLinkHda" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[9]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[12]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[13]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[14]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[15]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[16]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[17]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[18]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[19]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[20]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[21]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[22]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[23]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[1]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[3]" = "0x6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[4]" = "0x18"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[6]" = "0x8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[8]" = "0x40"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[10]" = "0x14"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[0]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[2]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[3]" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[4]" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[5]" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[6]" = "6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[8]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[9]" = "9"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[10]" = "10"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable "Intel Speed Shift Technology"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "speed_shift_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # HECI</span><br><span style="color: hsl(120, 100%, 40%);">+ register "HeciEnabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 on end # SA Thermal device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.5 off end # UFS SCS</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.6 off end # GSPI #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # USB xHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.3 on end # CNVi wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.5 on end # SDCard</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # I2C 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 on end # I2C #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 on end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 on end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.5 off end # Management Engine Interface 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 off end # I2C #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 on end # UART #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCI Express Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on end # PCI Express Port 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # PCI Express Port 9 X4 SLOT 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.4 off end # PCI Express Port 13</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.5 off end # PCI Express Port 14</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.6 off end # PCI Express Port 15</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.7 off end # PCI Express Port 16</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on end # PCI Express Port 17</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.4 on end # PCI Express Port 21 X4 SLOT 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # UART #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 off end # GSPI #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 on end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29066">change 29066</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iabd32eb43ee8e6b1a3993ba4e083a80c62485b14 </div>
<div style="display:none"> Gerrit-Change-Number: 29066 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> </div>