<p>Martin Roth <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/29015">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Richard Spiegel: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Rename CGPLL_CONFIG definitions<br><br>Shorten the names in the MISC CGPLL_CONFIG, and make the formatting match<br>the surrounding source.<br><br>Change-Id: I71cf1ff6bd4bca7a25484b4da9388c17cfecc043<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>Reviewed-on: https://review.coreboot.org/29015<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 34 insertions(+), 35 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 7f02811..896d494 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -110,35 +110,33 @@</span><br><span> #define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))</span><br><span> </span><br><span> /* FCH MISC Registers 0xfed80e00 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK_CNTRL 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK2_REQ_MAP_SHIFT 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK2_REQ_MAP_CLK_REQ2 3</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK0_REQ_MAP_SHIFT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK0_REQ_MAP_CLK_REQ0 1</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_CGPLL_CONFIG1 0x08</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_CGPLL_CONFIG3 0x10</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_REFDIV_SHIFT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_FBDIV_SHIFT 10</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_CGPLL_CONFIG4 0x14</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xffff << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SS_AMOUNT_DSFRAC_SHIFT 16</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xffff << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_CGPLL_CONFIG5 0x18</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xf << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_CGPLL_CONFIG6 0x1c</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_LF_MODE_SHIFT 9</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_CLK_CNTL1 0x40</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_FBDIV_TEST BIT(26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK_CNTRL 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK2_REQ_MAP_SHIFT 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK2_REQ_MAP_CLK_REQ2 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK0_REQ_MAP_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK0_REQ_MAP_CLK_REQ0 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG1 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG3 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_REFDIV_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_FBDIV_SHIFT 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG4 0x14</span><br><span style="color: hsl(120, 100%, 40%);">+#define SS_STEP_SIZE_DSFRAC_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SS_STEP_SIZE_DSFRAC_MASK (0xffff << SS_STEP_SIZE_DSFRAC_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SS_AMOUNT_DSFRAC_SHIFT 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define SS_AMOUNT_DSFRAC_MASK (0xffff << SS_AMOUNT_DSFRAC_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG5 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define SS_AMOUNT_NFRAC_SLIP_SHIFT 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define SS_AMOUNT_NFRAC_SLIP_MASK (0xf << SS_AMOUNT_NFRAC_SLIP_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG6 0x1c</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_LF_MODE_SHIFT 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CLK_CNTL1 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_FBDIV_TEST BIT(26)</span><br><span> </span><br><span> /* XHCI_PM Registers: 0xfed81c00 */</span><br><span> #define XHCI_PM_INDIRECT_INDEX 0x48</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 7f0318a..b7ddd57 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -589,15 +589,16 @@</span><br><span> misc_write32(MISC_CGPLL_CONFIG3, cfg3);</span><br><span> </span><br><span> uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5);</span><br><span style="color: hsl(0, 100%, 40%);">- cfg5 &= ~CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK;</span><br><span style="color: hsl(0, 100%, 40%);">- cfg5 |= (0x2 << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) & CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK;</span><br><span> misc_write32(MISC_CGPLL_CONFIG5, cfg5);</span><br><span> </span><br><span> uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4);</span><br><span style="color: hsl(0, 100%, 40%);">- cfg4 &= ~CG1PLL_SS_AMOUNT_DSFRAC_MASK;</span><br><span style="color: hsl(0, 100%, 40%);">- cfg4 |= (0xd000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK;</span><br><span style="color: hsl(0, 100%, 40%);">- cfg4 &= ~CG1PLL_SS_STEP_SIZE_DSFRAC_MASK;</span><br><span style="color: hsl(0, 100%, 40%);">- cfg4 |= (0x02d5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg4 &= ~SS_AMOUNT_DSFRAC_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ & SS_STEP_SIZE_DSFRAC_MASK;</span><br><span> misc_write32(MISC_CGPLL_CONFIG4, cfg4);</span><br><span> </span><br><span> rstcfg |= TOGGLE_ALL_PWR_GOOD;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29015">change 29015</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I71cf1ff6bd4bca7a25484b4da9388c17cfecc043 </div>
<div style="display:none"> Gerrit-Change-Number: 29015 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>