<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29057">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/amd/*/hudson: Use CF9 reset<br><br>Change-Id: I80801ba58b9d849ef5e14185510666bd312106c2<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/southbridge/amd/agesa/hudson/Kconfig<br>M src/southbridge/amd/agesa/hudson/reset.c<br>M src/southbridge/amd/pi/hudson/Kconfig<br>M src/southbridge/amd/pi/hudson/reset.c<br>4 files changed, 18 insertions(+), 41 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29057/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig</span><br><span>index 91ebe03..4f769fb 100644</span><br><span>--- a/src/southbridge/amd/agesa/hudson/Kconfig</span><br><span>+++ b/src/southbridge/amd/agesa/hudson/Kconfig</span><br><span>@@ -15,24 +15,22 @@</span><br><span> </span><br><span> config SOUTHBRIDGE_AMD_AGESA_BOLTON</span><br><span>  bool</span><br><span style="color: hsl(0, 100%, 40%);">-    select IOAPIC</span><br><span style="color: hsl(0, 100%, 40%);">-   select HAVE_USBDEBUG_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">-    select HAVE_HARD_RESET</span><br><span> </span><br><span> config SOUTHBRIDGE_AMD_AGESA_HUDSON</span><br><span>    bool</span><br><span style="color: hsl(0, 100%, 40%);">-    select IOAPIC</span><br><span style="color: hsl(0, 100%, 40%);">-   select HAVE_USBDEBUG_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">-    select HAVE_HARD_RESET</span><br><span> </span><br><span> config SOUTHBRIDGE_AMD_AGESA_YANGTZE</span><br><span>   bool</span><br><span style="color: hsl(0, 100%, 40%);">-    select IOAPIC</span><br><span style="color: hsl(0, 100%, 40%);">-   select HAVE_USBDEBUG_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">-    select HAVE_HARD_RESET</span><br><span> </span><br><span> if SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+       def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+    select IOAPIC</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_USBDEBUG_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+  select HAVE_CF9_RESET</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CF9_RESET_PREPARE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config BOOTBLOCK_SOUTHBRIDGE_INIT</span><br><span>         string</span><br><span>       default "southbridge/amd/agesa/hudson/bootblock.c"</span><br><span>diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c</span><br><span>index 315456d..7f61c83 100644</span><br><span>--- a/src/southbridge/amd/agesa/hudson/reset.c</span><br><span>+++ b/src/southbridge/amd/agesa/hudson/reset.c</span><br><span>@@ -17,26 +17,17 @@</span><br><span> #define __SIMPLE_DEVICE__</span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span> </span><br><span> #define HT_INIT_CONTROL     0x6c</span><br><span> #define HTIC_ColdR_Detect  (1<<4)</span><br><span> #define HTIC_BIOSR_Detect  (1<<5)</span><br><span> #define HTIC_INIT_Detect   (1<<6)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_bios_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void cf9_reset_prepare(void)</span><br><span> {</span><br><span>         u32 htic;</span><br><span>    htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);</span><br><span>   htic &= ~HTIC_BIOSR_Detect;</span><br><span>      pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-        set_bios_reset();</span><br><span style="color: hsl(0, 100%, 40%);">-       /* Try rebooting through port 0xcf9 */</span><br><span style="color: hsl(0, 100%, 40%);">-  /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */</span><br><span style="color: hsl(0, 100%, 40%);">-     outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);</span><br><span style="color: hsl(0, 100%, 40%);">-  outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig</span><br><span>index 5ac876f..9d803be 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/Kconfig</span><br><span>+++ b/src/southbridge/amd/pi/hudson/Kconfig</span><br><span>@@ -15,27 +15,25 @@</span><br><span> </span><br><span> config SOUTHBRIDGE_AMD_PI_BOLTON</span><br><span>       bool</span><br><span style="color: hsl(0, 100%, 40%);">-    select IOAPIC</span><br><span style="color: hsl(0, 100%, 40%);">-   select HAVE_USBDEBUG_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">-    select HAVE_HARD_RESET</span><br><span> </span><br><span> config SOUTHBRIDGE_AMD_PI_AVALON</span><br><span>       bool</span><br><span style="color: hsl(0, 100%, 40%);">-    select IOAPIC</span><br><span style="color: hsl(0, 100%, 40%);">-   select HAVE_USBDEBUG_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">-    select HAVE_HARD_RESET</span><br><span> </span><br><span> config SOUTHBRIDGE_AMD_PI_KERN</span><br><span>         bool</span><br><span style="color: hsl(0, 100%, 40%);">-    select IOAPIC</span><br><span style="color: hsl(0, 100%, 40%);">-   select HAVE_USBDEBUG_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">-    select HAVE_HARD_RESET</span><br><span> </span><br><span> config HUDSON_DISABLE_IMC</span><br><span>      bool</span><br><span> </span><br><span> if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+     def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+    select IOAPIC</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_USBDEBUG_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+  select HAVE_CF9_RESET</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CF9_RESET_PREPARE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config BOOTBLOCK_SOUTHBRIDGE_INIT</span><br><span>         string</span><br><span>       default "southbridge/amd/pi/hudson/bootblock.c"</span><br><span>diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c</span><br><span>index f80e2d4..7f61c83 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/reset.c</span><br><span>+++ b/src/southbridge/amd/pi/hudson/reset.c</span><br><span>@@ -17,27 +17,17 @@</span><br><span> #define __SIMPLE_DEVICE__</span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span> </span><br><span> #define HT_INIT_CONTROL     0x6c</span><br><span> #define HTIC_ColdR_Detect  (1<<4)</span><br><span> #define HTIC_BIOSR_Detect  (1<<5)</span><br><span> #define HTIC_INIT_Detect   (1<<6)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_bios_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void cf9_reset_prepare(void)</span><br><span> {</span><br><span>        u32 htic;</span><br><span>    htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);</span><br><span>   htic &= ~HTIC_BIOSR_Detect;</span><br><span>      pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-        set_bios_reset();</span><br><span style="color: hsl(0, 100%, 40%);">-       /* Try rebooting through port 0xcf9 */</span><br><span style="color: hsl(0, 100%, 40%);">-  /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */</span><br><span style="color: hsl(0, 100%, 40%);">-     outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);</span><br><span style="color: hsl(0, 100%, 40%);">-  outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29057">change 29057</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29057"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I80801ba58b9d849ef5e14185510666bd312106c2 </div>
<div style="display:none"> Gerrit-Change-Number: 29057 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>